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Thu, 16 Apr 2020 08:06:17 +0000 From: "Wu, Hao" To: "Xu, Yilun" , "mdf@kernel.org" , "linux-fpga@vger.kernel.org" , "linux-kernel@vger.kernel.org" CC: "trix@redhat.com" , "bhu@redhat.com" , Matthew Gerlach , "Xu, Yilun" Subject: RE: [PATCH 2/2] fpga: dfl: fix bug in port reset handshake Thread-Topic: [PATCH 2/2] fpga: dfl: fix bug in port reset handshake Thread-Index: AQHWE52IkB2SGtNF80OKjurJ2t/Pbah7ZCHw Date: Thu, 16 Apr 2020 08:06:17 +0000 Message-ID: References: <1587006712-22696-1-git-send-email-yilun.xu@intel.com> <1587006712-22696-3-git-send-email-yilun.xu@intel.com> In-Reply-To: <1587006712-22696-3-git-send-email-yilun.xu@intel.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-product: dlpe-windows dlp-reaction: no-action dlp-version: 11.2.0.6 authentication-results: spf=none (sender IP is ) smtp.mailfrom=hao.wu@intel.com; x-originating-ip: [192.102.204.36] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 5efc5064-f30c-45ef-5416-08d7e1dd0a68 x-ms-traffictypediagnostic: DM6PR11MB2809: x-ld-processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:4941; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 5efc5064-f30c-45ef-5416-08d7e1dd0a68 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Apr 2020 08:06:17.3376 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: OzO9Nhv19hktOBfWpDCQ5cWcMO+4IWiHgwmY/Zg8zqhhyH7H+X9lPPlFrW4OMECMjKDPmw+ZipTCohWCaYjysA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB2809 X-OriginatorOrg: intel.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: linux-fpga-owner@vger.kernel.org > On Behalf Of Xu Yilun > Sent: Thursday, April 16, 2020 11:12 AM > To: mdf@kernel.org; linux-fpga@vger.kernel.org; linux- > kernel@vger.kernel.org > Cc: trix@redhat.com; bhu@redhat.com; Matthew Gerlach > ; Xu, Yilun > Subject: [PATCH 2/2] fpga: dfl: fix bug in port reset handshake >=20 > From: Matthew Gerlach >=20 > When putting the port in reset, driver must wait for the soft reset > acknowledgment bit instead of the soft reset bit. >=20 > Fixes: 47c1b19c160f (fpga: dfl: afu: add port ops support) > Signed-off-by: Matthew Gerlach > Signed-off-by: Xu Yilun Thanks for catching this. Acked-by: Wu Hao > --- > drivers/fpga/dfl-afu-main.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c > index b0c3178..3fa2c59 100644 > --- a/drivers/fpga/dfl-afu-main.c > +++ b/drivers/fpga/dfl-afu-main.c > @@ -83,7 +83,8 @@ int __afu_port_disable(struct platform_device *pdev) > * on this port and minimum soft reset pulse width has elapsed. > * Driver polls port_soft_reset_ack to determine if reset done by HW. > */ > - if (readq_poll_timeout(base + PORT_HDR_CTRL, v, v & > PORT_CTRL_SFTRST, > + if (readq_poll_timeout(base + PORT_HDR_CTRL, v, > + v & PORT_CTRL_SFTRST_ACK, > RST_POLL_INVL, RST_POLL_TIMEOUT)) { > dev_err(&pdev->dev, "timeout, fail to reset device\n"); > return -ETIMEDOUT; > -- > 2.7.4 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: "Wu, Hao" Subject: RE: [PATCH 2/2] fpga: dfl: fix bug in port reset handshake Date: Thu, 16 Apr 2020 08:06:17 +0000 Message-ID: References: <1587006712-22696-1-git-send-email-yilun.xu@intel.com> <1587006712-22696-3-git-send-email-yilun.xu@intel.com> In-Reply-To: <1587006712-22696-3-git-send-email-yilun.xu@intel.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 To: "Xu, Yilun" , "mdf@kernel.org" , "linux-fpga@vger.kernel.org" , "linux-kernel@vger.kernel.org" Cc: "trix@redhat.com" , "bhu@redhat.com" , Matthew Gerlach List-ID: > -----Original Message----- > From: linux-fpga-owner@vger.kernel.org > On Behalf Of Xu Yilun > Sent: Thursday, April 16, 2020 11:12 AM > To: mdf@kernel.org; linux-fpga@vger.kernel.org; linux- > kernel@vger.kernel.org > Cc: trix@redhat.com; bhu@redhat.com; Matthew Gerlach > ; Xu, Yilun > Subject: [PATCH 2/2] fpga: dfl: fix bug in port reset handshake >=20 > From: Matthew Gerlach >=20 > When putting the port in reset, driver must wait for the soft reset > acknowledgment bit instead of the soft reset bit. >=20 > Fixes: 47c1b19c160f (fpga: dfl: afu: add port ops support) > Signed-off-by: Matthew Gerlach > Signed-off-by: Xu Yilun Thanks for catching this. Acked-by: Wu Hao > --- > drivers/fpga/dfl-afu-main.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) >=20 > diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c > index b0c3178..3fa2c59 100644 > --- a/drivers/fpga/dfl-afu-main.c > +++ b/drivers/fpga/dfl-afu-main.c > @@ -83,7 +83,8 @@ int __afu_port_disable(struct platform_device *pdev) > * on this port and minimum soft reset pulse width has elapsed. > * Driver polls port_soft_reset_ack to determine if reset done by HW. > */ > - if (readq_poll_timeout(base + PORT_HDR_CTRL, v, v & > PORT_CTRL_SFTRST, > + if (readq_poll_timeout(base + PORT_HDR_CTRL, v, > + v & PORT_CTRL_SFTRST_ACK, > RST_POLL_INVL, RST_POLL_TIMEOUT)) { > dev_err(&pdev->dev, "timeout, fail to reset device\n"); > return -ETIMEDOUT; > -- > 2.7.4