* [PATCH v2 1/5] platform/x86/intel: intel_pmc_core: Move intel_pmc_core* files to pmc subfolder
2021-07-08 2:07 [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Gayatri Kammela
@ 2021-07-08 2:07 ` Gayatri Kammela
2021-07-08 7:56 ` Andy Shevchenko
2021-07-08 2:07 ` [PATCH v2 2/5] platform/x86/intel: intel_pmc_core: Add Alderlake support to pmc_core driver Gayatri Kammela
` (4 subsequent siblings)
5 siblings, 1 reply; 12+ messages in thread
From: Gayatri Kammela @ 2021-07-08 2:07 UTC (permalink / raw)
To: platform-driver-x86
Cc: mgross, hdegoede, irenic.rajneesh, andriy.shevchenko,
vicamo.yang, srinivas.pandruvada, david.e.box, linux-kernel,
tamar.mashiah, gregkh, rajatja, Gayatri Kammela
As part of collecting Intel x86 specific drivers in their own
folder, move intel_pmc_core* files to its own subfolder there.
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: David Box <david.e.box@intel.com>
Cc: You-Sheng Yang <vicamo.yang@canonical.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
drivers/platform/x86/Kconfig | 21 ------------------
drivers/platform/x86/Makefile | 1 -
drivers/platform/x86/intel/Kconfig | 1 +
drivers/platform/x86/intel/Makefile | 1 +
drivers/platform/x86/intel/pmc/Kconfig | 22 +++++++++++++++++++
drivers/platform/x86/intel/pmc/Makefile | 5 +++++
.../x86/{ => intel/pmc}/intel_pmc_core.c | 0
.../x86/{ => intel/pmc}/intel_pmc_core.h | 0
.../{ => intel/pmc}/intel_pmc_core_pltdrv.c | 0
9 files changed, 29 insertions(+), 22 deletions(-)
create mode 100644 drivers/platform/x86/intel/pmc/Kconfig
create mode 100644 drivers/platform/x86/intel/pmc/Makefile
rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.c (100%)
rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.h (100%)
rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core_pltdrv.c (100%)
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 7d385c3b2239..cae72922f448 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -1184,27 +1184,6 @@ config INTEL_MRFLD_PWRBTN
To compile this driver as a module, choose M here: the module
will be called intel_mrfld_pwrbtn.
-config INTEL_PMC_CORE
- tristate "Intel PMC Core driver"
- depends on PCI
- depends on ACPI
- help
- The Intel Platform Controller Hub for Intel Core SoCs provides access
- to Power Management Controller registers via various interfaces. This
- driver can utilize debugging capabilities and supported features as
- exposed by the Power Management Controller. It also may perform some
- tasks in the PMC in order to enable transition into the SLPS0 state.
- It should be selected on all Intel platforms supported by the driver.
-
- Supported features:
- - SLP_S0_RESIDENCY counter
- - PCH IP Power Gating status
- - LTR Ignore / LTR Show
- - MPHY/PLL gating status (Sunrisepoint PCH only)
- - SLPS0 Debug registers (Cannonlake/Icelake PCH)
- - Low Power Mode registers (Tigerlake and beyond)
- - PMC quirks as needed to enable SLPS0/S0ix
-
config INTEL_PMT_CLASS
tristate
help
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 7ee369aab10d..43d36f8c36f1 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -128,7 +128,6 @@ obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL) += intel-uncore-frequency.o
obj-$(CONFIG_INTEL_BXTWC_PMIC_TMU) += intel_bxtwc_tmu.o
obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN) += intel_chtdc_ti_pwrbtn.o
obj-$(CONFIG_INTEL_MRFLD_PWRBTN) += intel_mrfld_pwrbtn.o
-obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o intel_pmc_core_pltdrv.o
obj-$(CONFIG_INTEL_PMT_CLASS) += intel_pmt_class.o
obj-$(CONFIG_INTEL_PMT_TELEMETRY) += intel_pmt_telemetry.o
obj-$(CONFIG_INTEL_PMT_CRASHLOG) += intel_pmt_crashlog.o
diff --git a/drivers/platform/x86/intel/Kconfig b/drivers/platform/x86/intel/Kconfig
index f2eef337eb98..8ca021785f67 100644
--- a/drivers/platform/x86/intel/Kconfig
+++ b/drivers/platform/x86/intel/Kconfig
@@ -18,5 +18,6 @@ if X86_PLATFORM_DRIVERS_INTEL
source "drivers/platform/x86/intel/int33fe/Kconfig"
source "drivers/platform/x86/intel/int3472/Kconfig"
+source "drivers/platform/x86/intel/pmc/Kconfig"
endif # X86_PLATFORM_DRIVERS_INTEL
diff --git a/drivers/platform/x86/intel/Makefile b/drivers/platform/x86/intel/Makefile
index 0653055942d5..49962f4dfdec 100644
--- a/drivers/platform/x86/intel/Makefile
+++ b/drivers/platform/x86/intel/Makefile
@@ -6,3 +6,4 @@
obj-$(CONFIG_INTEL_CHT_INT33FE) += int33fe/
obj-$(CONFIG_INTEL_SKL_INT3472) += int3472/
+obj-$(CONFIG_INTEL_PMC_CORE) += pmc/
diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/intel/pmc/Kconfig
new file mode 100644
index 000000000000..b4c955a35674
--- /dev/null
+++ b/drivers/platform/x86/intel/pmc/Kconfig
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-only
+
+config INTEL_PMC_CORE
+ tristate "Intel PMC Core driver"
+ depends on PCI
+ depends on ACPI
+ help
+ The Intel Platform Controller Hub for Intel Core SoCs provides access
+ to Power Management Controller registers via various interfaces. This
+ driver can utilize debugging capabilities and supported features as
+ exposed by the Power Management Controller. It also may perform some
+ tasks in the PMC in order to enable transition into the SLPS0 state.
+ It should be selected on all Intel platforms supported by the driver.
+
+ Supported features:
+ - SLP_S0_RESIDENCY counter
+ - PCH IP Power Gating status
+ - LTR Ignore / LTR Show
+ - MPHY/PLL gating status (Sunrisepoint PCH only)
+ - SLPS0 Debug registers (Cannonlake/Icelake PCH)
+ - Low Power Mode registers (Tigerlake and beyond)
+ - PMC quirks as needed to enable SLPS0/S0ix
diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86/intel/pmc/Makefile
new file mode 100644
index 000000000000..633a7598d6d6
--- /dev/null
+++ b/drivers/platform/x86/intel/pmc/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+
+obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
+obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o
diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
similarity index 100%
rename from drivers/platform/x86/intel_pmc_core.c
rename to drivers/platform/x86/intel/pmc/intel_pmc_core.c
diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
similarity index 100%
rename from drivers/platform/x86/intel_pmc_core.h
rename to drivers/platform/x86/intel/pmc/intel_pmc_core.h
diff --git a/drivers/platform/x86/intel_pmc_core_pltdrv.c b/drivers/platform/x86/intel/pmc/intel_pmc_core_pltdrv.c
similarity index 100%
rename from drivers/platform/x86/intel_pmc_core_pltdrv.c
rename to drivers/platform/x86/intel/pmc/intel_pmc_core_pltdrv.c
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 1/5] platform/x86/intel: intel_pmc_core: Move intel_pmc_core* files to pmc subfolder
2021-07-08 2:07 ` [PATCH v2 1/5] platform/x86/intel: intel_pmc_core: Move intel_pmc_core* files to pmc subfolder Gayatri Kammela
@ 2021-07-08 7:56 ` Andy Shevchenko
2021-07-09 17:39 ` Kammela, Gayatri
0 siblings, 1 reply; 12+ messages in thread
From: Andy Shevchenko @ 2021-07-08 7:56 UTC (permalink / raw)
To: Gayatri Kammela
Cc: Platform Driver, Mark Gross, Hans de Goede, Rajneesh Bhardwaj,
Andy Shevchenko, You-Sheng Yang, Pandruvada, Srinivas, Box,
David E, Linux Kernel Mailing List, Tamar Mashiah,
Greg Kroah-Hartman, Rajat Jain
On Thu, Jul 8, 2021 at 5:10 AM Gayatri Kammela
<gayatri.kammela@intel.com> wrote:
>
> As part of collecting Intel x86 specific drivers in their own
> folder, move intel_pmc_core* files to its own subfolder there.
I'm fine with this, it is also possible I think to drop intel_pmc_
prefix from the file names (core.c, core.h, pltdrv.c). In any case it
may be done later on.
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> Cc: David Box <david.e.box@intel.com>
> Cc: You-Sheng Yang <vicamo.yang@canonical.com>
> Cc: Hans de Goede <hdegoede@redhat.com>
> Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
> ---
> drivers/platform/x86/Kconfig | 21 ------------------
> drivers/platform/x86/Makefile | 1 -
> drivers/platform/x86/intel/Kconfig | 1 +
> drivers/platform/x86/intel/Makefile | 1 +
> drivers/platform/x86/intel/pmc/Kconfig | 22 +++++++++++++++++++
> drivers/platform/x86/intel/pmc/Makefile | 5 +++++
> .../x86/{ => intel/pmc}/intel_pmc_core.c | 0
> .../x86/{ => intel/pmc}/intel_pmc_core.h | 0
> .../{ => intel/pmc}/intel_pmc_core_pltdrv.c | 0
> 9 files changed, 29 insertions(+), 22 deletions(-)
> create mode 100644 drivers/platform/x86/intel/pmc/Kconfig
> create mode 100644 drivers/platform/x86/intel/pmc/Makefile
> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.c (100%)
> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.h (100%)
> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core_pltdrv.c (100%)
>
> diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
> index 7d385c3b2239..cae72922f448 100644
> --- a/drivers/platform/x86/Kconfig
> +++ b/drivers/platform/x86/Kconfig
> @@ -1184,27 +1184,6 @@ config INTEL_MRFLD_PWRBTN
> To compile this driver as a module, choose M here: the module
> will be called intel_mrfld_pwrbtn.
>
> -config INTEL_PMC_CORE
> - tristate "Intel PMC Core driver"
> - depends on PCI
> - depends on ACPI
> - help
> - The Intel Platform Controller Hub for Intel Core SoCs provides access
> - to Power Management Controller registers via various interfaces. This
> - driver can utilize debugging capabilities and supported features as
> - exposed by the Power Management Controller. It also may perform some
> - tasks in the PMC in order to enable transition into the SLPS0 state.
> - It should be selected on all Intel platforms supported by the driver.
> -
> - Supported features:
> - - SLP_S0_RESIDENCY counter
> - - PCH IP Power Gating status
> - - LTR Ignore / LTR Show
> - - MPHY/PLL gating status (Sunrisepoint PCH only)
> - - SLPS0 Debug registers (Cannonlake/Icelake PCH)
> - - Low Power Mode registers (Tigerlake and beyond)
> - - PMC quirks as needed to enable SLPS0/S0ix
> -
> config INTEL_PMT_CLASS
> tristate
> help
> diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
> index 7ee369aab10d..43d36f8c36f1 100644
> --- a/drivers/platform/x86/Makefile
> +++ b/drivers/platform/x86/Makefile
> @@ -128,7 +128,6 @@ obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL) += intel-uncore-frequency.o
> obj-$(CONFIG_INTEL_BXTWC_PMIC_TMU) += intel_bxtwc_tmu.o
> obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN) += intel_chtdc_ti_pwrbtn.o
> obj-$(CONFIG_INTEL_MRFLD_PWRBTN) += intel_mrfld_pwrbtn.o
> -obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o intel_pmc_core_pltdrv.o
> obj-$(CONFIG_INTEL_PMT_CLASS) += intel_pmt_class.o
> obj-$(CONFIG_INTEL_PMT_TELEMETRY) += intel_pmt_telemetry.o
> obj-$(CONFIG_INTEL_PMT_CRASHLOG) += intel_pmt_crashlog.o
> diff --git a/drivers/platform/x86/intel/Kconfig b/drivers/platform/x86/intel/Kconfig
> index f2eef337eb98..8ca021785f67 100644
> --- a/drivers/platform/x86/intel/Kconfig
> +++ b/drivers/platform/x86/intel/Kconfig
> @@ -18,5 +18,6 @@ if X86_PLATFORM_DRIVERS_INTEL
>
> source "drivers/platform/x86/intel/int33fe/Kconfig"
> source "drivers/platform/x86/intel/int3472/Kconfig"
> +source "drivers/platform/x86/intel/pmc/Kconfig"
>
> endif # X86_PLATFORM_DRIVERS_INTEL
> diff --git a/drivers/platform/x86/intel/Makefile b/drivers/platform/x86/intel/Makefile
> index 0653055942d5..49962f4dfdec 100644
> --- a/drivers/platform/x86/intel/Makefile
> +++ b/drivers/platform/x86/intel/Makefile
> @@ -6,3 +6,4 @@
>
> obj-$(CONFIG_INTEL_CHT_INT33FE) += int33fe/
> obj-$(CONFIG_INTEL_SKL_INT3472) += int3472/
> +obj-$(CONFIG_INTEL_PMC_CORE) += pmc/
> diff --git a/drivers/platform/x86/intel/pmc/Kconfig b/drivers/platform/x86/intel/pmc/Kconfig
> new file mode 100644
> index 000000000000..b4c955a35674
> --- /dev/null
> +++ b/drivers/platform/x86/intel/pmc/Kconfig
> @@ -0,0 +1,22 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +
> +config INTEL_PMC_CORE
> + tristate "Intel PMC Core driver"
> + depends on PCI
> + depends on ACPI
> + help
> + The Intel Platform Controller Hub for Intel Core SoCs provides access
> + to Power Management Controller registers via various interfaces. This
> + driver can utilize debugging capabilities and supported features as
> + exposed by the Power Management Controller. It also may perform some
> + tasks in the PMC in order to enable transition into the SLPS0 state.
> + It should be selected on all Intel platforms supported by the driver.
> +
> + Supported features:
> + - SLP_S0_RESIDENCY counter
> + - PCH IP Power Gating status
> + - LTR Ignore / LTR Show
> + - MPHY/PLL gating status (Sunrisepoint PCH only)
> + - SLPS0 Debug registers (Cannonlake/Icelake PCH)
> + - Low Power Mode registers (Tigerlake and beyond)
> + - PMC quirks as needed to enable SLPS0/S0ix
> diff --git a/drivers/platform/x86/intel/pmc/Makefile b/drivers/platform/x86/intel/pmc/Makefile
> new file mode 100644
> index 000000000000..633a7598d6d6
> --- /dev/null
> +++ b/drivers/platform/x86/intel/pmc/Makefile
> @@ -0,0 +1,5 @@
> +# SPDX-License-Identifier: GPL-2.0
> +#
> +
> +obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
> +obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o
> diff --git a/drivers/platform/x86/intel_pmc_core.c b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
> similarity index 100%
> rename from drivers/platform/x86/intel_pmc_core.c
> rename to drivers/platform/x86/intel/pmc/intel_pmc_core.c
> diff --git a/drivers/platform/x86/intel_pmc_core.h b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
> similarity index 100%
> rename from drivers/platform/x86/intel_pmc_core.h
> rename to drivers/platform/x86/intel/pmc/intel_pmc_core.h
> diff --git a/drivers/platform/x86/intel_pmc_core_pltdrv.c b/drivers/platform/x86/intel/pmc/intel_pmc_core_pltdrv.c
> similarity index 100%
> rename from drivers/platform/x86/intel_pmc_core_pltdrv.c
> rename to drivers/platform/x86/intel/pmc/intel_pmc_core_pltdrv.c
> --
> 2.25.1
>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH v2 1/5] platform/x86/intel: intel_pmc_core: Move intel_pmc_core* files to pmc subfolder
2021-07-08 7:56 ` Andy Shevchenko
@ 2021-07-09 17:39 ` Kammela, Gayatri
0 siblings, 0 replies; 12+ messages in thread
From: Kammela, Gayatri @ 2021-07-09 17:39 UTC (permalink / raw)
To: Andy Shevchenko
Cc: Platform Driver, Mark Gross, Hans de Goede, Rajneesh Bhardwaj,
Andy Shevchenko, You-Sheng Yang, Pandruvada, Srinivas, Box,
David E, Linux Kernel Mailing List, Mashiah, Tamar,
Greg Kroah-Hartman, Rajat Jain
> -----Original Message-----
> From: Andy Shevchenko <andy.shevchenko@gmail.com>
> Sent: Thursday, July 8, 2021 12:56 AM
> To: Kammela, Gayatri <gayatri.kammela@intel.com>
> Cc: Platform Driver <platform-driver-x86@vger.kernel.org>; Mark Gross
> <mgross@linux.intel.com>; Hans de Goede <hdegoede@redhat.com>;
> Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; You-Sheng Yang
> <vicamo.yang@canonical.com>; Pandruvada, Srinivas
> <srinivas.pandruvada@intel.com>; Box, David E <david.e.box@intel.com>;
> Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; Mashiah, Tamar
> <tamar.mashiah@intel.com>; Greg Kroah-Hartman
> <gregkh@linuxfoundation.org>; Rajat Jain <rajatja@google.com>
> Subject: Re: [PATCH v2 1/5] platform/x86/intel: intel_pmc_core: Move
> intel_pmc_core* files to pmc subfolder
>
> On Thu, Jul 8, 2021 at 5:10 AM Gayatri Kammela
> <gayatri.kammela@intel.com> wrote:
> >
> > As part of collecting Intel x86 specific drivers in their own folder,
> > move intel_pmc_core* files to its own subfolder there.
>
> I'm fine with this, it is also possible I think to drop intel_pmc_ prefix from the
> file names (core.c, core.h, pltdrv.c). In any case it may be done later on.
> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Thanks Andy! I will send v3 without intel_pmc_ prefix from the file names
>
> > Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> > Cc: David Box <david.e.box@intel.com>
> > Cc: You-Sheng Yang <vicamo.yang@canonical.com>
> > Cc: Hans de Goede <hdegoede@redhat.com>
> > Suggested-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
> > ---
> > drivers/platform/x86/Kconfig | 21 ------------------
> > drivers/platform/x86/Makefile | 1 -
> > drivers/platform/x86/intel/Kconfig | 1 +
> > drivers/platform/x86/intel/Makefile | 1 +
> > drivers/platform/x86/intel/pmc/Kconfig | 22 +++++++++++++++++++
> > drivers/platform/x86/intel/pmc/Makefile | 5 +++++
> > .../x86/{ => intel/pmc}/intel_pmc_core.c | 0
> > .../x86/{ => intel/pmc}/intel_pmc_core.h | 0
> > .../{ => intel/pmc}/intel_pmc_core_pltdrv.c | 0
> > 9 files changed, 29 insertions(+), 22 deletions(-) create mode
> > 100644 drivers/platform/x86/intel/pmc/Kconfig
> > create mode 100644 drivers/platform/x86/intel/pmc/Makefile
> > rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.c (100%)
> > rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.h (100%)
> > rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core_pltdrv.c
> > (100%)
> >
> > diff --git a/drivers/platform/x86/Kconfig
> > b/drivers/platform/x86/Kconfig index 7d385c3b2239..cae72922f448
> 100644
> > --- a/drivers/platform/x86/Kconfig
> > +++ b/drivers/platform/x86/Kconfig
> > @@ -1184,27 +1184,6 @@ config INTEL_MRFLD_PWRBTN
> > To compile this driver as a module, choose M here: the module
> > will be called intel_mrfld_pwrbtn.
> >
> > -config INTEL_PMC_CORE
> > - tristate "Intel PMC Core driver"
> > - depends on PCI
> > - depends on ACPI
> > - help
> > - The Intel Platform Controller Hub for Intel Core SoCs provides access
> > - to Power Management Controller registers via various interfaces. This
> > - driver can utilize debugging capabilities and supported features as
> > - exposed by the Power Management Controller. It also may perform
> some
> > - tasks in the PMC in order to enable transition into the SLPS0 state.
> > - It should be selected on all Intel platforms supported by the driver.
> > -
> > - Supported features:
> > - - SLP_S0_RESIDENCY counter
> > - - PCH IP Power Gating status
> > - - LTR Ignore / LTR Show
> > - - MPHY/PLL gating status (Sunrisepoint PCH only)
> > - - SLPS0 Debug registers (Cannonlake/Icelake PCH)
> > - - Low Power Mode registers (Tigerlake and beyond)
> > - - PMC quirks as needed to enable SLPS0/S0ix
> > -
> > config INTEL_PMT_CLASS
> > tristate
> > help
> > diff --git a/drivers/platform/x86/Makefile
> > b/drivers/platform/x86/Makefile index 7ee369aab10d..43d36f8c36f1
> > 100644
> > --- a/drivers/platform/x86/Makefile
> > +++ b/drivers/platform/x86/Makefile
> > @@ -128,7 +128,6 @@ obj-$(CONFIG_INTEL_UNCORE_FREQ_CONTROL)
> += intel-uncore-frequency.o
> > obj-$(CONFIG_INTEL_BXTWC_PMIC_TMU) += intel_bxtwc_tmu.o
> > obj-$(CONFIG_INTEL_CHTDC_TI_PWRBTN) += intel_chtdc_ti_pwrbtn.o
> > obj-$(CONFIG_INTEL_MRFLD_PWRBTN) += intel_mrfld_pwrbtn.o
> > -obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
> intel_pmc_core_pltdrv.o
> > obj-$(CONFIG_INTEL_PMT_CLASS) += intel_pmt_class.o
> > obj-$(CONFIG_INTEL_PMT_TELEMETRY) += intel_pmt_telemetry.o
> > obj-$(CONFIG_INTEL_PMT_CRASHLOG) += intel_pmt_crashlog.o
> > diff --git a/drivers/platform/x86/intel/Kconfig
> > b/drivers/platform/x86/intel/Kconfig
> > index f2eef337eb98..8ca021785f67 100644
> > --- a/drivers/platform/x86/intel/Kconfig
> > +++ b/drivers/platform/x86/intel/Kconfig
> > @@ -18,5 +18,6 @@ if X86_PLATFORM_DRIVERS_INTEL
> >
> > source "drivers/platform/x86/intel/int33fe/Kconfig"
> > source "drivers/platform/x86/intel/int3472/Kconfig"
> > +source "drivers/platform/x86/intel/pmc/Kconfig"
> >
> > endif # X86_PLATFORM_DRIVERS_INTEL
> > diff --git a/drivers/platform/x86/intel/Makefile
> > b/drivers/platform/x86/intel/Makefile
> > index 0653055942d5..49962f4dfdec 100644
> > --- a/drivers/platform/x86/intel/Makefile
> > +++ b/drivers/platform/x86/intel/Makefile
> > @@ -6,3 +6,4 @@
> >
> > obj-$(CONFIG_INTEL_CHT_INT33FE) += int33fe/
> > obj-$(CONFIG_INTEL_SKL_INT3472) += int3472/
> > +obj-$(CONFIG_INTEL_PMC_CORE) += pmc/
> > diff --git a/drivers/platform/x86/intel/pmc/Kconfig
> > b/drivers/platform/x86/intel/pmc/Kconfig
> > new file mode 100644
> > index 000000000000..b4c955a35674
> > --- /dev/null
> > +++ b/drivers/platform/x86/intel/pmc/Kconfig
> > @@ -0,0 +1,22 @@
> > +# SPDX-License-Identifier: GPL-2.0-only
> > +
> > +config INTEL_PMC_CORE
> > + tristate "Intel PMC Core driver"
> > + depends on PCI
> > + depends on ACPI
> > + help
> > + The Intel Platform Controller Hub for Intel Core SoCs provides access
> > + to Power Management Controller registers via various interfaces.
> This
> > + driver can utilize debugging capabilities and supported features as
> > + exposed by the Power Management Controller. It also may perform
> some
> > + tasks in the PMC in order to enable transition into the SLPS0 state.
> > + It should be selected on all Intel platforms supported by the driver.
> > +
> > + Supported features:
> > + - SLP_S0_RESIDENCY counter
> > + - PCH IP Power Gating status
> > + - LTR Ignore / LTR Show
> > + - MPHY/PLL gating status (Sunrisepoint PCH only)
> > + - SLPS0 Debug registers (Cannonlake/Icelake PCH)
> > + - Low Power Mode registers (Tigerlake and beyond)
> > + - PMC quirks as needed to enable SLPS0/S0ix
> > diff --git a/drivers/platform/x86/intel/pmc/Makefile
> > b/drivers/platform/x86/intel/pmc/Makefile
> > new file mode 100644
> > index 000000000000..633a7598d6d6
> > --- /dev/null
> > +++ b/drivers/platform/x86/intel/pmc/Makefile
> > @@ -0,0 +1,5 @@
> > +# SPDX-License-Identifier: GPL-2.0
> > +#
> > +
> > +obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core.o
> > +obj-$(CONFIG_INTEL_PMC_CORE) += intel_pmc_core_pltdrv.o
> > diff --git a/drivers/platform/x86/intel_pmc_core.c
> > b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
> > similarity index 100%
> > rename from drivers/platform/x86/intel_pmc_core.c
> > rename to drivers/platform/x86/intel/pmc/intel_pmc_core.c
> > diff --git a/drivers/platform/x86/intel_pmc_core.h
> > b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
> > similarity index 100%
> > rename from drivers/platform/x86/intel_pmc_core.h
> > rename to drivers/platform/x86/intel/pmc/intel_pmc_core.h
> > diff --git a/drivers/platform/x86/intel_pmc_core_pltdrv.c
> > b/drivers/platform/x86/intel/pmc/intel_pmc_core_pltdrv.c
> > similarity index 100%
> > rename from drivers/platform/x86/intel_pmc_core_pltdrv.c
> > rename to drivers/platform/x86/intel/pmc/intel_pmc_core_pltdrv.c
> > --
> > 2.25.1
> >
>
>
> --
> With Best Regards,
> Andy Shevchenko
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 2/5] platform/x86/intel: intel_pmc_core: Add Alderlake support to pmc_core driver
2021-07-08 2:07 [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Gayatri Kammela
2021-07-08 2:07 ` [PATCH v2 1/5] platform/x86/intel: intel_pmc_core: Move intel_pmc_core* files to pmc subfolder Gayatri Kammela
@ 2021-07-08 2:07 ` Gayatri Kammela
2021-07-08 2:07 ` [PATCH v2 3/5] platform/x86/intel: intel_pmc_core: Add Latency Tolerance Reporting (LTR) support to Alder Lake Gayatri Kammela
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Gayatri Kammela @ 2021-07-08 2:07 UTC (permalink / raw)
To: platform-driver-x86
Cc: mgross, hdegoede, irenic.rajneesh, andriy.shevchenko,
vicamo.yang, srinivas.pandruvada, david.e.box, linux-kernel,
tamar.mashiah, gregkh, rajatja, Gayatri Kammela
Add Alder Lake client and mobile support to pmc_core driver.
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
.../platform/x86/intel/pmc/intel_pmc_core.c | 68 +++++++++++++++++++
.../platform/x86/intel/pmc/intel_pmc_core.h | 2 +
2 files changed, 70 insertions(+)
diff --git a/drivers/platform/x86/intel/pmc/intel_pmc_core.c b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
index b0e486a6bdfb..441018e3ce96 100644
--- a/drivers/platform/x86/intel/pmc/intel_pmc_core.c
+++ b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
@@ -645,6 +645,73 @@ static void pmc_core_get_tgl_lpm_reqs(struct platform_device *pdev)
ACPI_FREE(out_obj);
}
+/* Alder Lake: PGD PFET Enable Ack Status Register(s) bitmap */
+static const struct pmc_bit_map adl_pfear_map[] = {
+ {"SPI/eSPI", BIT(2)},
+ {"XHCI", BIT(3)},
+ {"SPA", BIT(4)},
+ {"SPB", BIT(5)},
+ {"SPC", BIT(6)},
+ {"GBE", BIT(7)},
+
+ {"SATA", BIT(0)},
+ {"HDA_PGD0", BIT(1)},
+ {"HDA_PGD1", BIT(2)},
+ {"HDA_PGD2", BIT(3)},
+ {"HDA_PGD3", BIT(4)},
+ {"SPD", BIT(5)},
+ {"LPSS", BIT(6)},
+
+ {"SMB", BIT(0)},
+ {"ISH", BIT(1)},
+ {"ITH", BIT(3)},
+
+ {"XDCI", BIT(1)},
+ {"DCI", BIT(2)},
+ {"CSE", BIT(3)},
+ {"CSME_KVM", BIT(4)},
+ {"CSME_PMT", BIT(5)},
+ {"CSME_CLINK", BIT(6)},
+ {"CSME_PTIO", BIT(7)},
+
+ {"CSME_USBR", BIT(0)},
+ {"CSME_SUSRAM", BIT(1)},
+ {"CSME_SMT1", BIT(2)},
+ {"CSME_SMS2", BIT(4)},
+ {"CSME_SMS1", BIT(5)},
+ {"CSME_RTC", BIT(6)},
+ {"CSME_PSF", BIT(7)},
+
+ {"CNVI", BIT(3)},
+
+ {"HDA_PGD4", BIT(2)},
+ {"HDA_PGD5", BIT(3)},
+ {"HDA_PGD6", BIT(4)},
+ {}
+};
+
+static const struct pmc_bit_map *ext_adl_pfear_map[] = {
+ /*
+ * Check intel_pmc_core_ids[] users of cnp_reg_map for
+ * a list of core SoCs using this.
+ */
+ adl_pfear_map,
+ NULL
+};
+
+static const struct pmc_reg_map adl_reg_map = {
+ .pfear_sts = ext_adl_pfear_map,
+ .slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
+ .slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+ .msr_sts = msr_map,
+ .ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
+ .regmap_length = CNP_PMC_MMIO_REG_LEN,
+ .ppfear0_offset = CNP_PMC_HOST_PPFEAR0A,
+ .ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
+ .pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
+ .pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+};
+
static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
{
return readl(pmcdev->regbase + reg_offset);
@@ -1574,6 +1641,7 @@ static const struct x86_cpu_id intel_pmc_core_ids[] = {
X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_L, &icl_reg_map),
X86_MATCH_INTEL_FAM6_MODEL(ROCKETLAKE, &tgl_reg_map),
X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, &tgl_reg_map),
+ X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE, &adl_reg_map),
{}
};
diff --git a/drivers/platform/x86/intel/pmc/intel_pmc_core.h b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
index e8dae9c6c45f..c0ca20b32c6b 100644
--- a/drivers/platform/x86/intel/pmc/intel_pmc_core.h
+++ b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
@@ -197,6 +197,8 @@ enum ppfear_regs {
#define TGL_NUM_IP_IGN_ALLOWED 23
#define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */
+#define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098
+
/*
* Tigerlake Power Management Controller register offsets
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 3/5] platform/x86/intel: intel_pmc_core: Add Latency Tolerance Reporting (LTR) support to Alder Lake
2021-07-08 2:07 [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Gayatri Kammela
2021-07-08 2:07 ` [PATCH v2 1/5] platform/x86/intel: intel_pmc_core: Move intel_pmc_core* files to pmc subfolder Gayatri Kammela
2021-07-08 2:07 ` [PATCH v2 2/5] platform/x86/intel: intel_pmc_core: Add Alderlake support to pmc_core driver Gayatri Kammela
@ 2021-07-08 2:07 ` Gayatri Kammela
2021-07-08 2:07 ` [PATCH v2 4/5] platform/x86/intel: intel_pmc_core: Add Alder Lake low power mode support for pmc_core Gayatri Kammela
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Gayatri Kammela @ 2021-07-08 2:07 UTC (permalink / raw)
To: platform-driver-x86
Cc: mgross, hdegoede, irenic.rajneesh, andriy.shevchenko,
vicamo.yang, srinivas.pandruvada, david.e.box, linux-kernel,
tamar.mashiah, gregkh, rajatja, Gayatri Kammela
Add support to show the Latency Tolerance Reporting for the IPs on
the Alder Lake PCH as reported by the PMC. This LTR support on
Alder Lake is slightly different from the Cannon lake PCH that is being
reused by all platforms till Tiger Lake.
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
.../platform/x86/intel/pmc/intel_pmc_core.c | 39 +++++++++++++++++++
.../platform/x86/intel/pmc/intel_pmc_core.h | 2 +
2 files changed, 41 insertions(+)
diff --git a/drivers/platform/x86/intel/pmc/intel_pmc_core.c b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
index 441018e3ce96..611019bfe685 100644
--- a/drivers/platform/x86/intel/pmc/intel_pmc_core.c
+++ b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
@@ -699,10 +699,48 @@ static const struct pmc_bit_map *ext_adl_pfear_map[] = {
NULL
};
+static const struct pmc_bit_map adl_ltr_show_map[] = {
+ {"SOUTHPORT_A", CNP_PMC_LTR_SPA},
+ {"SOUTHPORT_B", CNP_PMC_LTR_SPB},
+ {"SATA", CNP_PMC_LTR_SATA},
+ {"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
+ {"XHCI", CNP_PMC_LTR_XHCI},
+ {"SOUTHPORT_F", ADL_PMC_LTR_SPF},
+ {"ME", CNP_PMC_LTR_ME},
+ /* EVA is Enterprise Value Add, doesn't really exist on PCH */
+ {"SATA1", CNP_PMC_LTR_EVA},
+ {"SOUTHPORT_C", CNP_PMC_LTR_SPC},
+ {"HD_AUDIO", CNP_PMC_LTR_AZ},
+ {"CNV", CNP_PMC_LTR_CNV},
+ {"LPSS", CNP_PMC_LTR_LPSS},
+ {"SOUTHPORT_D", CNP_PMC_LTR_SPD},
+ {"SOUTHPORT_E", CNP_PMC_LTR_SPE},
+ {"SATA2", CNP_PMC_LTR_CAM},
+ {"ESPI", CNP_PMC_LTR_ESPI},
+ {"SCC", CNP_PMC_LTR_SCC},
+ {"ISH", CNP_PMC_LTR_ISH},
+ {"UFSX2", CNP_PMC_LTR_UFSX2},
+ {"EMMC", CNP_PMC_LTR_EMMC},
+ /*
+ * Check intel_pmc_core_ids[] users of cnp_reg_map for
+ * a list of core SoCs using this.
+ */
+ {"WIGIG", ICL_PMC_LTR_WIGIG},
+ {"THC0", TGL_PMC_LTR_THC0},
+ {"THC1", TGL_PMC_LTR_THC1},
+ {"SOUTHPORT_G", CNP_PMC_LTR_RESERVED},
+
+ /* Below two cannot be used for LTR_IGNORE */
+ {"CURRENT_PLATFORM", CNP_PMC_LTR_CUR_PLT},
+ {"AGGREGATED_SYSTEM", CNP_PMC_LTR_CUR_ASLT},
+ {}
+};
+
static const struct pmc_reg_map adl_reg_map = {
.pfear_sts = ext_adl_pfear_map,
.slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
.slp_s0_res_counter_step = TGL_PMC_SLP_S0_RES_COUNTER_STEP,
+ .ltr_show_sts = adl_ltr_show_map,
.msr_sts = msr_map,
.ltr_ignore_offset = CNP_PMC_LTR_IGNORE_OFFSET,
.regmap_length = CNP_PMC_MMIO_REG_LEN,
@@ -710,6 +748,7 @@ static const struct pmc_reg_map adl_reg_map = {
.ppfear_buckets = CNP_PPFEAR_NUM_ENTRIES,
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
+ .ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
};
static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
diff --git a/drivers/platform/x86/intel/pmc/intel_pmc_core.h b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
index c0ca20b32c6b..45b352ece6db 100644
--- a/drivers/platform/x86/intel/pmc/intel_pmc_core.h
+++ b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
@@ -197,6 +197,8 @@ enum ppfear_regs {
#define TGL_NUM_IP_IGN_ALLOWED 23
#define TGL_PMC_LPM_RES_COUNTER_STEP_X2 61 /* 30.5us * 2 */
+#define ADL_PMC_LTR_SPF 0x1C00
+#define ADL_NUM_IP_IGN_ALLOWED 23
#define ADL_PMC_SLP_S0_RES_COUNTER_OFFSET 0x1098
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 4/5] platform/x86/intel: intel_pmc_core: Add Alder Lake low power mode support for pmc_core
2021-07-08 2:07 [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Gayatri Kammela
` (2 preceding siblings ...)
2021-07-08 2:07 ` [PATCH v2 3/5] platform/x86/intel: intel_pmc_core: Add Latency Tolerance Reporting (LTR) support to Alder Lake Gayatri Kammela
@ 2021-07-08 2:07 ` Gayatri Kammela
2021-07-08 2:07 ` [PATCH v2 5/5] platform/x86/intel: intel_pmc_core: Add GBE Package C10 fix for Alder Lake PCH Gayatri Kammela
2021-07-08 17:32 ` [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Rajneesh Bhardwaj
5 siblings, 0 replies; 12+ messages in thread
From: Gayatri Kammela @ 2021-07-08 2:07 UTC (permalink / raw)
To: platform-driver-x86
Cc: mgross, hdegoede, irenic.rajneesh, andriy.shevchenko,
vicamo.yang, srinivas.pandruvada, david.e.box, linux-kernel,
tamar.mashiah, gregkh, rajatja, Gayatri Kammela
Alder Lake has 14 status registers that are memory mapped. These
registers show the status of the low power mode requirements. The
registers are latched on every C10 entry or exit and on every s0ix.y
entry/exit. Accessing these registers is useful for debugging any low
power related activities.
Thus, add debugfs entry to access low power mode status registers.
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: David Box <david.e.box@intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
---
.../platform/x86/intel/pmc/intel_pmc_core.c | 194 ++++++++++++++++++
.../platform/x86/intel/pmc/intel_pmc_core.h | 13 ++
2 files changed, 207 insertions(+)
diff --git a/drivers/platform/x86/intel/pmc/intel_pmc_core.c b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
index 611019bfe685..27346ff5a924 100644
--- a/drivers/platform/x86/intel/pmc/intel_pmc_core.c
+++ b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
@@ -736,6 +736,189 @@ static const struct pmc_bit_map adl_ltr_show_map[] = {
{}
};
+static const struct pmc_bit_map adl_clocksource_status_map[] = {
+ {"CLKPART1_OFF_STS", BIT(0)},
+ {"CLKPART2_OFF_STS", BIT(1)},
+ {"CLKPART3_OFF_STS", BIT(2)},
+ {"CLKPART4_OFF_STS", BIT(3)},
+ {"CLKPART5_OFF_STS", BIT(4)},
+ {"CLKPART6_OFF_STS", BIT(5)},
+ {"CLKPART7_OFF_STS", BIT(6)},
+ {"CLKPART8_OFF_STS", BIT(7)},
+ {"PCIE0PLL_OFF_STS", BIT(10)},
+ {"PCIE1PLL_OFF_STS", BIT(11)},
+ {"PCIE2PLL_OFF_STS", BIT(12)},
+ {"PCIE3PLL_OFF_STS", BIT(13)},
+ {"PCIE4PLL_OFF_STS", BIT(14)},
+ {"PCIE5PLL_OFF_STS", BIT(15)},
+ {"PCIE6PLL_OFF_STS", BIT(16)},
+ {"USB2PLL_OFF_STS", BIT(18)},
+ {"OCPLL_OFF_STS", BIT(22)},
+ {"AUDIOPLL_OFF_STS", BIT(23)},
+ {"GBEPLL_OFF_STS", BIT(24)},
+ {"Fast_XTAL_Osc_OFF_STS", BIT(25)},
+ {"AC_Ring_Osc_OFF_STS", BIT(26)},
+ {"MC_Ring_Osc_OFF_STS", BIT(27)},
+ {"SATAPLL_OFF_STS", BIT(29)},
+ {"USB3PLL_OFF_STS", BIT(31)},
+ {}
+};
+
+static const struct pmc_bit_map adl_power_gating_status_0_map[] = {
+ {"PMC_PGD0_PG_STS", BIT(0)},
+ {"DMI_PGD0_PG_STS", BIT(1)},
+ {"ESPISPI_PGD0_PG_STS", BIT(2)},
+ {"XHCI_PGD0_PG_STS", BIT(3)},
+ {"SPA_PGD0_PG_STS", BIT(4)},
+ {"SPB_PGD0_PG_STS", BIT(5)},
+ {"SPC_PGD0_PG_STS", BIT(6)},
+ {"GBE_PGD0_PG_STS", BIT(7)},
+ {"SATA_PGD0_PG_STS", BIT(8)},
+ {"DSP_PGD0_PG_STS", BIT(9)},
+ {"DSP_PGD1_PG_STS", BIT(10)},
+ {"DSP_PGD2_PG_STS", BIT(11)},
+ {"DSP_PGD3_PG_STS", BIT(12)},
+ {"SPD_PGD0_PG_STS", BIT(13)},
+ {"LPSS_PGD0_PG_STS", BIT(14)},
+ {"SMB_PGD0_PG_STS", BIT(16)},
+ {"ISH_PGD0_PG_STS", BIT(17)},
+ {"NPK_PGD0_PG_STS", BIT(19)},
+ {"PECI_PGD0_PG_STS", BIT(21)},
+ {"XDCI_PGD0_PG_STS", BIT(25)},
+ {"EXI_PGD0_PG_STS", BIT(26)},
+ {"CSE_PGD0_PG_STS", BIT(27)},
+ {"KVMCC_PGD0_PG_STS", BIT(28)},
+ {"PMT_PGD0_PG_STS", BIT(29)},
+ {"CLINK_PGD0_PG_STS", BIT(30)},
+ {"PTIO_PGD0_PG_STS", BIT(31)},
+ {}
+};
+
+static const struct pmc_bit_map adl_power_gating_status_1_map[] = {
+ {"USBR0_PGD0_PG_STS", BIT(0)},
+ {"SMT1_PGD0_PG_STS", BIT(2)},
+ {"CSMERTC_PGD0_PG_STS", BIT(6)},
+ {"CSMEPSF_PGD0_PG_STS", BIT(7)},
+ {"CNVI_PGD0_PG_STS", BIT(19)},
+ {"DSP_PGD4_PG_STS", BIT(26)},
+ {"SPG_PGD0_PG_STS", BIT(27)},
+ {"SPE_PGD0_PG_STS", BIT(28)},
+ {}
+};
+
+static const struct pmc_bit_map adl_power_gating_status_2_map[] = {
+ {"THC0_PGD0_PG_STS", BIT(7)},
+ {"THC1_PGD0_PG_STS", BIT(8)},
+ {"SPF_PGD0_PG_STS", BIT(14)},
+ {}
+};
+
+static const struct pmc_bit_map adl_d3_status_0_map[] = {
+ {"ISH_D3_STS", BIT(2)},
+ {"LPSS_D3_STS", BIT(3)},
+ {"XDCI_D3_STS", BIT(4)},
+ {"XHCI_D3_STS", BIT(5)},
+ {"SPA_D3_STS", BIT(12)},
+ {"SPB_D3_STS", BIT(13)},
+ {"SPC_D3_STS", BIT(14)},
+ {"SPD_D3_STS", BIT(15)},
+ {"SPE_D3_STS", BIT(16)},
+ {"DSP_D3_STS", BIT(19)},
+ {"SATA_D3_STS", BIT(20)},
+ {"DMI_D3_STS", BIT(22)},
+ {}
+};
+
+static const struct pmc_bit_map adl_d3_status_1_map[] = {
+ {"GBE_D3_STS", BIT(19)},
+ {"CNVI_D3_STS", BIT(27)},
+ {}
+};
+
+static const struct pmc_bit_map adl_d3_status_2_map[] = {
+ {"CSMERTC_D3_STS", BIT(1)},
+ {"CSE_D3_STS", BIT(4)},
+ {"KVMCC_D3_STS", BIT(5)},
+ {"USBR0_D3_STS", BIT(6)},
+ {"SMT1_D3_STS", BIT(8)},
+ {"PTIO_D3_STS", BIT(16)},
+ {"PMT_D3_STS", BIT(17)},
+ {}
+};
+
+static const struct pmc_bit_map adl_d3_status_3_map[] = {
+ {"THC0_D3_STS", BIT(14)},
+ {"THC1_D3_STS", BIT(15)},
+ {}
+};
+
+static const struct pmc_bit_map adl_vnn_req_status_0_map[] = {
+ {"ISH_VNN_REQ_STS", BIT(2)},
+ {"ESPISPI_VNN_REQ_STS", BIT(18)},
+ {"DSP_VNN_REQ_STS", BIT(19)},
+ {}
+};
+
+static const struct pmc_bit_map adl_vnn_req_status_1_map[] = {
+ {"NPK_VNN_REQ_STS", BIT(4)},
+ {"EXI_VNN_REQ_STS", BIT(9)},
+ {"GBE_VNN_REQ_STS", BIT(19)},
+ {"SMB_VNN_REQ_STS", BIT(25)},
+ {"CNVI_VNN_REQ_STS", BIT(27)},
+ {}
+};
+
+static const struct pmc_bit_map adl_vnn_req_status_2_map[] = {
+ {"CSMERTC_VNN_REQ_STS", BIT(1)},
+ {"CSE_VNN_REQ_STS", BIT(4)},
+ {"SMT1_VNN_REQ_STS", BIT(8)},
+ {"CLINK_VNN_REQ_STS", BIT(14)},
+ {"GPIOCOM4_VNN_REQ_STS", BIT(20)},
+ {"GPIOCOM3_VNN_REQ_STS", BIT(21)},
+ {"GPIOCOM2_VNN_REQ_STS", BIT(22)},
+ {"GPIOCOM1_VNN_REQ_STS", BIT(23)},
+ {"GPIOCOM0_VNN_REQ_STS", BIT(24)},
+ {}
+};
+
+static const struct pmc_bit_map adl_vnn_req_status_3_map[] = {
+ {"GPIOCOM5_VNN_REQ_STS", BIT(11)},
+ {}
+};
+
+static const struct pmc_bit_map adl_vnn_misc_status_map[] = {
+ {"CPU_C10_REQ_STS", BIT(0)},
+ {"PCIe_LPM_En_REQ_STS", BIT(3)},
+ {"ITH_REQ_STS", BIT(5)},
+ {"CNVI_REQ_STS", BIT(6)},
+ {"ISH_REQ_STS", BIT(7)},
+ {"USB2_SUS_PG_Sys_REQ_STS", BIT(10)},
+ {"PCIe_Clk_REQ_STS", BIT(12)},
+ {"MPHY_Core_DL_REQ_STS", BIT(16)},
+ {"Break-even_En_REQ_STS", BIT(17)},
+ {"MPHY_SUS_REQ_STS", BIT(22)},
+ {"xDCI_attached_REQ_STS", BIT(24)},
+ {}
+};
+
+static const struct pmc_bit_map *adl_lpm_maps[] = {
+ adl_clocksource_status_map,
+ adl_power_gating_status_0_map,
+ adl_power_gating_status_1_map,
+ adl_power_gating_status_2_map,
+ adl_d3_status_0_map,
+ adl_d3_status_1_map,
+ adl_d3_status_2_map,
+ adl_d3_status_3_map,
+ adl_vnn_req_status_0_map,
+ adl_vnn_req_status_1_map,
+ adl_vnn_req_status_2_map,
+ adl_vnn_req_status_3_map,
+ adl_vnn_misc_status_map,
+ tgl_signal_status_map,
+ NULL
+};
+
static const struct pmc_reg_map adl_reg_map = {
.pfear_sts = ext_adl_pfear_map,
.slp_s0_offset = ADL_PMC_SLP_S0_RES_COUNTER_OFFSET,
@@ -749,6 +932,17 @@ static const struct pmc_reg_map adl_reg_map = {
.pm_cfg_offset = CNP_PMC_PM_CFG_OFFSET,
.pm_read_disable_bit = CNP_PMC_READ_DISABLE_BIT,
.ltr_ignore_max = ADL_NUM_IP_IGN_ALLOWED,
+ .lpm_num_modes = ADL_LPM_NUM_MODES,
+ .lpm_num_maps = ADL_LPM_NUM_MAPS,
+ .lpm_res_counter_step_x2 = TGL_PMC_LPM_RES_COUNTER_STEP_X2,
+ .etr3_offset = ETR3_OFFSET,
+ .lpm_sts_latch_en_offset = ADL_LPM_STATUS_LATCH_EN_OFFSET,
+ .lpm_priority_offset = ADL_LPM_PRI_OFFSET,
+ .lpm_en_offset = ADL_LPM_EN_OFFSET,
+ .lpm_residency_offset = ADL_LPM_RESIDENCY_OFFSET,
+ .lpm_sts = adl_lpm_maps,
+ .lpm_status_offset = ADL_LPM_STATUS_OFFSET,
+ .lpm_live_status_offset = ADL_LPM_LIVE_STATUS_OFFSET,
};
static inline u32 pmc_core_reg_read(struct pmc_dev *pmcdev, int reg_offset)
diff --git a/drivers/platform/x86/intel/pmc/intel_pmc_core.h b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
index 45b352ece6db..333e25981e8e 100644
--- a/drivers/platform/x86/intel/pmc/intel_pmc_core.h
+++ b/drivers/platform/x86/intel/pmc/intel_pmc_core.h
@@ -222,6 +222,18 @@ enum ppfear_regs {
/* Extended Test Mode Register LPM bits (TGL and later */
#define ETR3_CLEAR_LPM_EVENTS BIT(28)
+/* Alder Lake Power Management Controller register offsets */
+#define ADL_LPM_EN_OFFSET 0x179C
+#define ADL_LPM_RESIDENCY_OFFSET 0x17A4
+#define ADL_LPM_NUM_MODES 2
+#define ADL_LPM_NUM_MAPS 14
+
+/* Alder Lake Low Power Mode debug registers */
+#define ADL_LPM_STATUS_OFFSET 0x170C
+#define ADL_LPM_PRI_OFFSET 0x17A0
+#define ADL_LPM_STATUS_LATCH_EN_OFFSET 0x1704
+#define ADL_LPM_LIVE_STATUS_OFFSET 0x1764
+
const char *pmc_lpm_modes[] = {
"S0i2.0",
"S0i2.1",
@@ -281,6 +293,7 @@ struct pmc_reg_map {
const u32 pm_vric1_offset;
/* Low Power Mode registers */
const int lpm_num_maps;
+ const int lpm_num_modes;
const int lpm_res_counter_step_x2;
const u32 lpm_sts_latch_en_offset;
const u32 lpm_en_offset;
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH v2 5/5] platform/x86/intel: intel_pmc_core: Add GBE Package C10 fix for Alder Lake PCH
2021-07-08 2:07 [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Gayatri Kammela
` (3 preceding siblings ...)
2021-07-08 2:07 ` [PATCH v2 4/5] platform/x86/intel: intel_pmc_core: Add Alder Lake low power mode support for pmc_core Gayatri Kammela
@ 2021-07-08 2:07 ` Gayatri Kammela
2021-07-08 17:32 ` [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Rajneesh Bhardwaj
5 siblings, 0 replies; 12+ messages in thread
From: Gayatri Kammela @ 2021-07-08 2:07 UTC (permalink / raw)
To: platform-driver-x86
Cc: mgross, hdegoede, irenic.rajneesh, andriy.shevchenko,
vicamo.yang, srinivas.pandruvada, david.e.box, linux-kernel,
tamar.mashiah, gregkh, rajatja, David E. Box
From: "David E. Box" <david.e.box@linux.intel.com>
Alder PCH uses the same Gigabit Ethernet (GBE) device as Tiger Lake PCH
which cannot achieve PC10 without ignoring the PMC GBE LTR. Add this
work around for Alder Lake PCH as well.
Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Tested-by: You-Sheng Yang <vicamo.yang@canonical.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
---
drivers/platform/x86/intel/pmc/intel_pmc_core.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/platform/x86/intel/pmc/intel_pmc_core.c b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
index 27346ff5a924..84b58b557a49 100644
--- a/drivers/platform/x86/intel/pmc/intel_pmc_core.c
+++ b/drivers/platform/x86/intel/pmc/intel_pmc_core.c
@@ -1983,10 +1983,10 @@ static int pmc_core_probe(struct platform_device *pdev)
pmc_core_get_tgl_lpm_reqs(pdev);
/*
- * On TGL, due to a hardware limitation, the GBE LTR blocks PC10 when
- * a cable is attached. Tell the PMC to ignore it.
+ * On TGL and ADL, due to a hardware limitation, the GBE LTR blocks PC10
+ * when a cable is attached. Tell the PMC to ignore it.
*/
- if (pmcdev->map == &tgl_reg_map) {
+ if (pmcdev->map == &tgl_reg_map || pmcdev->map == &adl_reg_map) {
dev_dbg(&pdev->dev, "ignoring GBE LTR\n");
pmc_core_send_ltr_ignore(pmcdev, 3);
}
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver
2021-07-08 2:07 [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Gayatri Kammela
` (4 preceding siblings ...)
2021-07-08 2:07 ` [PATCH v2 5/5] platform/x86/intel: intel_pmc_core: Add GBE Package C10 fix for Alder Lake PCH Gayatri Kammela
@ 2021-07-08 17:32 ` Rajneesh Bhardwaj
2021-07-09 17:40 ` Kammela, Gayatri
5 siblings, 1 reply; 12+ messages in thread
From: Rajneesh Bhardwaj @ 2021-07-08 17:32 UTC (permalink / raw)
To: Gayatri Kammela
Cc: platform-driver-x86, mgross, hdegoede, Andy Shevchenko,
vicamo.yang, Srinivas Pandruvada, Box, David E, linux-kernel,
tamar.mashiah, gregkh, rajatja, Shyam-sundar.S-k,
Alexander.Deucher, mlimonci
Series looks good to me.
Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
+ AMD folks
Hi Alex, Mario and Shaym - Perhaps AMD PMC files should also follow
the similar convention and it could probably evolve in future where
both x86 based PMC drivers might use some common library helper
functions. What do you think?
On Wed, Jul 7, 2021 at 10:10 PM Gayatri Kammela
<gayatri.kammela@intel.com> wrote:
>
> Hi,
> The patch series move intel_pmc_core* files to pmc subfolder as well as
> add Alder Lake PCH-S support to PMC core driver.
>
> Patch 1: Move intel_pmc_core* files to pmc subfolder
> Patch 2: Add Alderlake support to pmc_core driver
> Patch 3: Add Latency Tolerance Reporting (LTR) support to Alder Lake
> Patch 4: Add Alder Lake low power mode support for pmc_core
> Patch 5: Add GBE Package C10 fix for Alder Lake
>
> Changes since v1:
> 1) Add patch 1 to v2 i.e., Move intel_pmc_core* files to pmc subfolder
> 2) Modify commit message for patch 2.
>
> David E. Box (1):
> platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
> PCH
>
> Gayatri Kammela (4):
> platform/x86: intel_pmc_core: Move intel_pmc_core* files to pmc
> subfolder
> platform/x86/intel: intel_pmc_core: Add Alderlake support to pmc_core
> driver
> platform/x86/intel: intel_pmc_core: Add Latency Tolerance Reporting
> (LTR) support to Alder Lake
> platform/x86/intel: intel_pmc_core: Add Alder Lake low power mode
> support for pmc_core
>
> drivers/platform/x86/Kconfig | 21 --
> drivers/platform/x86/Makefile | 1 -
> drivers/platform/x86/intel/Kconfig | 1 +
> drivers/platform/x86/intel/Makefile | 1 +
> drivers/platform/x86/intel/pmc/Kconfig | 22 ++
> drivers/platform/x86/intel/pmc/Makefile | 5 +
> .../x86/{ => intel/pmc}/intel_pmc_core.c | 307 +++++++++++++++++-
> .../x86/{ => intel/pmc}/intel_pmc_core.h | 17 +
> .../{ => intel/pmc}/intel_pmc_core_pltdrv.c | 0
> 9 files changed, 350 insertions(+), 25 deletions(-)
> create mode 100644 drivers/platform/x86/intel/pmc/Kconfig
> create mode 100644 drivers/platform/x86/intel/pmc/Makefile
> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.c (85%)
> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.h (95%)
> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core_pltdrv.c (100%)
>
> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> Cc: David Box <david.e.box@intel.com>
> Cc: You-Sheng Yang <vicamo.yang@canonical.com>
> Cc: Hans de Goede <hdegoede@redhat.com>
>
> base-commit: a931dd33d370896a683236bba67c0d6f3d01144d
> --
> 2.25.1
>
--
Thanks,
Rajneesh
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver
2021-07-08 17:32 ` [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver Rajneesh Bhardwaj
@ 2021-07-09 17:40 ` Kammela, Gayatri
2021-07-09 18:30 ` Limonciello, Mario
0 siblings, 1 reply; 12+ messages in thread
From: Kammela, Gayatri @ 2021-07-09 17:40 UTC (permalink / raw)
To: Rajneesh Bhardwaj
Cc: platform-driver-x86, mgross, hdegoede, Andy Shevchenko,
vicamo.yang, Pandruvada, Srinivas, Box, David E, linux-kernel,
Mashiah, Tamar, gregkh, rajatja, Shyam-sundar.S-k,
Alexander.Deucher, mlimonci
> -----Original Message-----
> From: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
> Sent: Thursday, July 8, 2021 10:33 AM
> To: Kammela, Gayatri <gayatri.kammela@intel.com>
> Cc: platform-driver-x86@vger.kernel.org; mgross@linux.intel.com;
> hdegoede@redhat.com; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; vicamo.yang@canonical.com;
> Pandruvada, Srinivas <srinivas.pandruvada@intel.com>; Box, David E
> <david.e.box@intel.com>; linux-kernel@vger.kernel.org; Mashiah, Tamar
> <tamar.mashiah@intel.com>; gregkh@linuxfoundation.org;
> rajatja@google.com; Shyam-sundar.S-k@amd.com;
> Alexander.Deucher@amd.com; mlimonci@amd.com
> Subject: Re: [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver
>
> Series looks good to me.
>
> Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
Thanks Rajneesh!
>
> + AMD folks
>
> Hi Alex, Mario and Shaym - Perhaps AMD PMC files should also follow the
> similar convention and it could probably evolve in future where both x86
> based PMC drivers might use some common library helper functions. What
> do you think?
>
>
> On Wed, Jul 7, 2021 at 10:10 PM Gayatri Kammela
> <gayatri.kammela@intel.com> wrote:
> >
> > Hi,
> > The patch series move intel_pmc_core* files to pmc subfolder as well
> > as add Alder Lake PCH-S support to PMC core driver.
> >
> > Patch 1: Move intel_pmc_core* files to pmc subfolder Patch 2: Add
> > Alderlake support to pmc_core driver Patch 3: Add Latency Tolerance
> > Reporting (LTR) support to Alder Lake Patch 4: Add Alder Lake low
> > power mode support for pmc_core Patch 5: Add GBE Package C10 fix for
> > Alder Lake
> >
> > Changes since v1:
> > 1) Add patch 1 to v2 i.e., Move intel_pmc_core* files to pmc subfolder
> > 2) Modify commit message for patch 2.
> >
> > David E. Box (1):
> > platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
> > PCH
> >
> > Gayatri Kammela (4):
> > platform/x86: intel_pmc_core: Move intel_pmc_core* files to pmc
> > subfolder
> > platform/x86/intel: intel_pmc_core: Add Alderlake support to pmc_core
> > driver
> > platform/x86/intel: intel_pmc_core: Add Latency Tolerance Reporting
> > (LTR) support to Alder Lake
> > platform/x86/intel: intel_pmc_core: Add Alder Lake low power mode
> > support for pmc_core
> >
> > drivers/platform/x86/Kconfig | 21 --
> > drivers/platform/x86/Makefile | 1 -
> > drivers/platform/x86/intel/Kconfig | 1 +
> > drivers/platform/x86/intel/Makefile | 1 +
> > drivers/platform/x86/intel/pmc/Kconfig | 22 ++
> > drivers/platform/x86/intel/pmc/Makefile | 5 +
> > .../x86/{ => intel/pmc}/intel_pmc_core.c | 307 +++++++++++++++++-
> > .../x86/{ => intel/pmc}/intel_pmc_core.h | 17 +
> > .../{ => intel/pmc}/intel_pmc_core_pltdrv.c | 0
> > 9 files changed, 350 insertions(+), 25 deletions(-) create mode
> > 100644 drivers/platform/x86/intel/pmc/Kconfig
> > create mode 100644 drivers/platform/x86/intel/pmc/Makefile
> > rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.c (85%)
> > rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.h (95%)
> > rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core_pltdrv.c
> > (100%)
> >
> > Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> > Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> > Cc: David Box <david.e.box@intel.com>
> > Cc: You-Sheng Yang <vicamo.yang@canonical.com>
> > Cc: Hans de Goede <hdegoede@redhat.com>
> >
> > base-commit: a931dd33d370896a683236bba67c0d6f3d01144d
> > --
> > 2.25.1
> >
>
>
> --
> Thanks,
> Rajneesh
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver
2021-07-09 17:40 ` Kammela, Gayatri
@ 2021-07-09 18:30 ` Limonciello, Mario
2021-07-09 23:01 ` Kammela, Gayatri
0 siblings, 1 reply; 12+ messages in thread
From: Limonciello, Mario @ 2021-07-09 18:30 UTC (permalink / raw)
To: Kammela, Gayatri, Rajneesh Bhardwaj
Cc: platform-driver-x86, mgross, hdegoede, Andy Shevchenko,
vicamo.yang, Pandruvada, Srinivas, Box, David E, linux-kernel,
Mashiah, Tamar, gregkh, rajatja, Shyam-sundar.S-k,
Alexander.Deucher, mlimonci
On 7/9/2021 12:40, Kammela, Gayatri wrote:
>> -----Original Message-----
>> From: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
>> Sent: Thursday, July 8, 2021 10:33 AM
>> To: Kammela, Gayatri <gayatri.kammela@intel.com>
>> Cc: platform-driver-x86@vger.kernel.org; mgross@linux.intel.com;
>> hdegoede@redhat.com; Andy Shevchenko
>> <andriy.shevchenko@linux.intel.com>; vicamo.yang@canonical.com;
>> Pandruvada, Srinivas <srinivas.pandruvada@intel.com>; Box, David E
>> <david.e.box@intel.com>; linux-kernel@vger.kernel.org; Mashiah, Tamar
>> <tamar.mashiah@intel.com>; gregkh@linuxfoundation.org;
>> rajatja@google.com; Shyam-sundar.S-k@amd.com;
>> Alexander.Deucher@amd.com; mlimonci@amd.com
>> Subject: Re: [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver
>>
>> Series looks good to me.
>>
>> Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
> Thanks Rajneesh!
>>
>> + AMD folks
>>
>> Hi Alex, Mario and Shaym - Perhaps AMD PMC files should also follow the
>> similar convention and it could probably evolve in future where both x86
>> based PMC drivers might use some common library helper functions. What
>> do you think?
Gayatri,
If there is going to be PMC subfolder, then yes of course amd-pmc.c
should move into it too.
Are you also thinking to move uPEP code from drivers/acpi/x86/s2idle.c
into the PMC drivers? Or do you have some suggestions on what code
could be shared between AMD and Intel PMC drivers?
Thanks,
>>
>>
>> On Wed, Jul 7, 2021 at 10:10 PM Gayatri Kammela
>> <gayatri.kammela@intel.com> wrote:
>>>
>>> Hi,
>>> The patch series move intel_pmc_core* files to pmc subfolder as well
>>> as add Alder Lake PCH-S support to PMC core driver.
>>>
>>> Patch 1: Move intel_pmc_core* files to pmc subfolder Patch 2: Add
>>> Alderlake support to pmc_core driver Patch 3: Add Latency Tolerance
>>> Reporting (LTR) support to Alder Lake Patch 4: Add Alder Lake low
>>> power mode support for pmc_core Patch 5: Add GBE Package C10 fix for
>>> Alder Lake
>>>
>>> Changes since v1:
>>> 1) Add patch 1 to v2 i.e., Move intel_pmc_core* files to pmc subfolder
>>> 2) Modify commit message for patch 2.
>>>
>>> David E. Box (1):
>>> platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
>>> PCH
>>>
>>> Gayatri Kammela (4):
>>> platform/x86: intel_pmc_core: Move intel_pmc_core* files to pmc
>>> subfolder
>>> platform/x86/intel: intel_pmc_core: Add Alderlake support to pmc_core
>>> driver
>>> platform/x86/intel: intel_pmc_core: Add Latency Tolerance Reporting
>>> (LTR) support to Alder Lake
>>> platform/x86/intel: intel_pmc_core: Add Alder Lake low power mode
>>> support for pmc_core
>>>
>>> drivers/platform/x86/Kconfig | 21 --
>>> drivers/platform/x86/Makefile | 1 -
>>> drivers/platform/x86/intel/Kconfig | 1 +
>>> drivers/platform/x86/intel/Makefile | 1 +
>>> drivers/platform/x86/intel/pmc/Kconfig | 22 ++
>>> drivers/platform/x86/intel/pmc/Makefile | 5 +
>>> .../x86/{ => intel/pmc}/intel_pmc_core.c | 307 +++++++++++++++++-
>>> .../x86/{ => intel/pmc}/intel_pmc_core.h | 17 +
>>> .../{ => intel/pmc}/intel_pmc_core_pltdrv.c | 0
>>> 9 files changed, 350 insertions(+), 25 deletions(-) create mode
>>> 100644 drivers/platform/x86/intel/pmc/Kconfig
>>> create mode 100644 drivers/platform/x86/intel/pmc/Makefile
>>> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.c (85%)
>>> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.h (95%)
>>> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core_pltdrv.c
>>> (100%)
>>>
>>> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
>>> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
>>> Cc: David Box <david.e.box@intel.com>
>>> Cc: You-Sheng Yang <vicamo.yang@canonical.com>
>>> Cc: Hans de Goede <hdegoede@redhat.com>
>>>
>>> base-commit: a931dd33d370896a683236bba67c0d6f3d01144d
>>> --
>>> 2.25.1
>>>
>>
>>
>> --
>> Thanks,
>> Rajneesh
^ permalink raw reply [flat|nested] 12+ messages in thread* RE: [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver
2021-07-09 18:30 ` Limonciello, Mario
@ 2021-07-09 23:01 ` Kammela, Gayatri
0 siblings, 0 replies; 12+ messages in thread
From: Kammela, Gayatri @ 2021-07-09 23:01 UTC (permalink / raw)
To: Limonciello, Mario, Rajneesh Bhardwaj
Cc: platform-driver-x86, mgross, hdegoede, Andy Shevchenko,
vicamo.yang, Pandruvada, Srinivas, Box, David E, linux-kernel,
Mashiah, Tamar, gregkh, rajatja, Shyam-sundar.S-k,
Alexander.Deucher, mlimonci
> -----Original Message-----
> From: Limonciello, Mario <mario.limonciello@amd.com>
> Sent: Friday, July 9, 2021 11:31 AM
> To: Kammela, Gayatri <gayatri.kammela@intel.com>; Rajneesh Bhardwaj
> <irenic.rajneesh@gmail.com>
> Cc: platform-driver-x86@vger.kernel.org; mgross@linux.intel.com;
> hdegoede@redhat.com; Andy Shevchenko
> <andriy.shevchenko@linux.intel.com>; vicamo.yang@canonical.com;
> Pandruvada, Srinivas <srinivas.pandruvada@intel.com>; Box, David E
> <david.e.box@intel.com>; linux-kernel@vger.kernel.org; Mashiah, Tamar
> <tamar.mashiah@intel.com>; gregkh@linuxfoundation.org;
> rajatja@google.com; Shyam-sundar.S-k@amd.com;
> Alexander.Deucher@amd.com; mlimonci@amd.com
> Subject: Re: [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core driver
>
> On 7/9/2021 12:40, Kammela, Gayatri wrote:
> >> -----Original Message-----
> >> From: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
> >> Sent: Thursday, July 8, 2021 10:33 AM
> >> To: Kammela, Gayatri <gayatri.kammela@intel.com>
> >> Cc: platform-driver-x86@vger.kernel.org; mgross@linux.intel.com;
> >> hdegoede@redhat.com; Andy Shevchenko
> >> <andriy.shevchenko@linux.intel.com>; vicamo.yang@canonical.com;
> >> Pandruvada, Srinivas <srinivas.pandruvada@intel.com>; Box, David E
> >> <david.e.box@intel.com>; linux-kernel@vger.kernel.org; Mashiah, Tamar
> >> <tamar.mashiah@intel.com>; gregkh@linuxfoundation.org;
> >> rajatja@google.com; Shyam-sundar.S-k@amd.com;
> >> Alexander.Deucher@amd.com; mlimonci@amd.com
> >> Subject: Re: [PATCH v2 0/5] Add Alder Lake PCH-S support to PMC core
> >> driver
> >>
> >> Series looks good to me.
> >>
> >> Acked-by: Rajneesh Bhardwaj <irenic.rajneesh@gmail.com>
> > Thanks Rajneesh!
> >>
> >> + AMD folks
> >>
> >> Hi Alex, Mario and Shaym - Perhaps AMD PMC files should also follow
> >> the similar convention and it could probably evolve in future where
> >> both x86 based PMC drivers might use some common library helper
> >> functions. What do you think?
>
> Gayatri,
>
> If there is going to be PMC subfolder, then yes of course amd-pmc.c should
> move into it too.
>
> Are you also thinking to move uPEP code from drivers/acpi/x86/s2idle.c into
> the PMC drivers? Or do you have some suggestions on what code could be
> shared between AMD and Intel PMC drivers?
Hi Mario! I am not planning on moving any other code to pmc subfolder. I don’t have any suggestions, but we could ask Andy and Hans on these files.
>
> Thanks,
>
> >>
> >>
> >> On Wed, Jul 7, 2021 at 10:10 PM Gayatri Kammela
> >> <gayatri.kammela@intel.com> wrote:
> >>>
> >>> Hi,
> >>> The patch series move intel_pmc_core* files to pmc subfolder as well
> >>> as add Alder Lake PCH-S support to PMC core driver.
> >>>
> >>> Patch 1: Move intel_pmc_core* files to pmc subfolder Patch 2: Add
> >>> Alderlake support to pmc_core driver Patch 3: Add Latency Tolerance
> >>> Reporting (LTR) support to Alder Lake Patch 4: Add Alder Lake low
> >>> power mode support for pmc_core Patch 5: Add GBE Package C10 fix for
> >>> Alder Lake
> >>>
> >>> Changes since v1:
> >>> 1) Add patch 1 to v2 i.e., Move intel_pmc_core* files to pmc
> >>> subfolder
> >>> 2) Modify commit message for patch 2.
> >>>
> >>> David E. Box (1):
> >>> platform/x86: intel_pmc_core: Add GBE Package C10 fix for Alder Lake
> >>> PCH
> >>>
> >>> Gayatri Kammela (4):
> >>> platform/x86: intel_pmc_core: Move intel_pmc_core* files to pmc
> >>> subfolder
> >>> platform/x86/intel: intel_pmc_core: Add Alderlake support to
> pmc_core
> >>> driver
> >>> platform/x86/intel: intel_pmc_core: Add Latency Tolerance Reporting
> >>> (LTR) support to Alder Lake
> >>> platform/x86/intel: intel_pmc_core: Add Alder Lake low power mode
> >>> support for pmc_core
> >>>
> >>> drivers/platform/x86/Kconfig | 21 --
> >>> drivers/platform/x86/Makefile | 1 -
> >>> drivers/platform/x86/intel/Kconfig | 1 +
> >>> drivers/platform/x86/intel/Makefile | 1 +
> >>> drivers/platform/x86/intel/pmc/Kconfig | 22 ++
> >>> drivers/platform/x86/intel/pmc/Makefile | 5 +
> >>> .../x86/{ => intel/pmc}/intel_pmc_core.c | 307 +++++++++++++++++-
> >>> .../x86/{ => intel/pmc}/intel_pmc_core.h | 17 +
> >>> .../{ => intel/pmc}/intel_pmc_core_pltdrv.c | 0
> >>> 9 files changed, 350 insertions(+), 25 deletions(-) create mode
> >>> 100644 drivers/platform/x86/intel/pmc/Kconfig
> >>> create mode 100644 drivers/platform/x86/intel/pmc/Makefile
> >>> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.c (85%)
> >>> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core.h (95%)
> >>> rename drivers/platform/x86/{ => intel/pmc}/intel_pmc_core_pltdrv.c
> >>> (100%)
> >>>
> >>> Cc: Srinivas Pandruvada <srinivas.pandruvada@intel.com>
> >>> Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
> >>> Cc: David Box <david.e.box@intel.com>
> >>> Cc: You-Sheng Yang <vicamo.yang@canonical.com>
> >>> Cc: Hans de Goede <hdegoede@redhat.com>
> >>>
> >>> base-commit: a931dd33d370896a683236bba67c0d6f3d01144d
> >>> --
> >>> 2.25.1
> >>>
> >>
> >>
> >> --
> >> Thanks,
> >> Rajneesh
^ permalink raw reply [flat|nested] 12+ messages in thread