From: "Quan, Evan" <Evan.Quan@amd.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: "Deucher, Alexander" <Alexander.Deucher@amd.com>,
amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH 2/2] drm/amd/pm: optimize the link width/speed retrieving
Date: Tue, 23 Feb 2021 02:03:36 +0000 [thread overview]
Message-ID: <DM6PR12MB2619B7625866332A0E44EB4AE4809@DM6PR12MB2619.namprd12.prod.outlook.com> (raw)
In-Reply-To: <CADnq5_N0=a_5wd1aLhvMPeX2_SnyTvA3+7tyt14Bx8mRo3-6PA@mail.gmail.com>
[AMD Official Use Only - Internal Distribution Only]
PMFW of Arcturus does not expose us those information.
So, we have to stick to current implementation(smu_v11_0_get_current_pcie_link_width/speed) for Arcturus.
Regards
Evan
-----Original Message-----
From: Alex Deucher <alexdeucher@gmail.com>
Sent: Tuesday, February 23, 2021 5:48 AM
To: Quan, Evan <Evan.Quan@amd.com>
Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>; Deucher, Alexander <Alexander.Deucher@amd.com>
Subject: Re: [PATCH 2/2] drm/amd/pm: optimize the link width/speed retrieving
On Sun, Feb 21, 2021 at 11:04 PM Evan Quan <evan.quan@amd.com> wrote:
>
> By using the information provided by PMFW when available.
>
> Change-Id: I1afec4cd07ac9608861ee07c449e320e3f36a932
> Signed-off-by: Evan Quan <evan.quan@amd.com>
What about arcturus?
Acked-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> .../gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c | 17 ++++++++++----
> .../amd/pm/swsmu/smu11/sienna_cichlid_ppt.c | 22 +++++++++++++++----
> 2 files changed, 31 insertions(+), 8 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> index 29e04f33f276..7fe2876c99fe 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
> @@ -72,6 +72,8 @@
>
> #define SMU_11_0_GFX_BUSY_THRESHOLD 15
>
> +static uint16_t link_speed[] = {25, 50, 80, 160};
> +
> static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
> MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
> @@ -2391,10 +2393,17 @@ static ssize_t navi10_get_gpu_metrics(struct
> smu_context *smu,
>
> gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
>
> - gpu_metrics->pcie_link_width =
> - smu_v11_0_get_current_pcie_link_width(smu);
> - gpu_metrics->pcie_link_speed =
> - smu_v11_0_get_current_pcie_link_speed(smu);
> + if (((adev->asic_type == CHIP_NAVI14) && smu_version > 0x00351F00) ||
> + ((adev->asic_type == CHIP_NAVI12) && smu_version > 0x00341C00) ||
> + ((adev->asic_type == CHIP_NAVI10) && smu_version > 0x002A3B00)) {
> + gpu_metrics->pcie_link_width = (uint16_t)metrics.PcieWidth;
> + gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
> + } else {
> + gpu_metrics->pcie_link_width =
> + smu_v11_0_get_current_pcie_link_width(smu);
> + gpu_metrics->pcie_link_speed =
> + smu_v11_0_get_current_pcie_link_speed(smu);
> + }
>
> gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
>
> diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> index e74299da1739..6fd95764c952 100644
> --- a/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> +++ b/drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
> @@ -73,6 +73,8 @@
>
> #define SMU_11_0_7_GFX_BUSY_THRESHOLD 15
>
> +static uint16_t link_speed[] = {25, 50, 80, 160};
> +
> static struct cmn2asic_msg_mapping sienna_cichlid_message_map[SMU_MSG_MAX_COUNT] = {
> MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
> MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
> @@ -3124,6 +3126,8 @@ static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
> SmuMetricsExternal_t metrics_external;
> SmuMetrics_t *metrics =
> &(metrics_external.SmuMetrics);
> + struct amdgpu_device *adev = smu->adev;
> + uint32_t smu_version;
> int ret = 0;
>
> ret = smu_cmn_get_metrics_table(smu, @@ -3170,10 +3174,20 @@
> static ssize_t sienna_cichlid_get_gpu_metrics(struct smu_context *smu,
>
> gpu_metrics->current_fan_speed = metrics->CurrFanSpeed;
>
> - gpu_metrics->pcie_link_width =
> - smu_v11_0_get_current_pcie_link_width(smu);
> - gpu_metrics->pcie_link_speed =
> - smu_v11_0_get_current_pcie_link_speed(smu);
> + ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
> + if (ret)
> + return ret;
> +
> + if (((adev->asic_type == CHIP_SIENNA_CICHLID) && smu_version > 0x003A1E00) ||
> + ((adev->asic_type == CHIP_NAVY_FLOUNDER) && smu_version > 0x00410400)) {
> + gpu_metrics->pcie_link_width = (uint16_t)metrics->PcieWidth;
> + gpu_metrics->pcie_link_speed = link_speed[metrics->PcieRate];
> + } else {
> + gpu_metrics->pcie_link_width =
> + smu_v11_0_get_current_pcie_link_width(smu);
> + gpu_metrics->pcie_link_speed =
> + smu_v11_0_get_current_pcie_link_speed(smu);
> + }
>
> gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
>
> --
> 2.29.0
>
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next prev parent reply other threads:[~2021-02-23 2:03 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-22 4:03 [PATCH 1/2] drm/amd/pm: correct gpu metrics related data structures Evan Quan
2021-02-22 4:03 ` [PATCH 2/2] drm/amd/pm: optimize the link width/speed retrieving Evan Quan
2021-02-22 21:47 ` Alex Deucher
2021-02-23 2:03 ` Quan, Evan [this message]
2021-02-22 21:45 ` [PATCH 1/2] drm/amd/pm: correct gpu metrics related data structures Alex Deucher
2021-02-23 11:48 ` Tom St Denis
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