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From: "Zhuo, Qingqing" <Qingqing.Zhuo@amd.com>
To: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: Mark Yacoub <markyacoub@chromium.org>,
	"Siqueira, Rodrigo" <Rodrigo.Siqueira@amd.com>,
	amd-gfx mailing list <amd-gfx@lists.freedesktop.org>,
	"Wheeler, Daniel" <Daniel.Wheeler@amd.com>,
	"Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"Kazlauskas, Nicholas" <Nicholas.Kazlauskas@amd.com>
Subject: RE: [PATCH 1/2] drm/amd/display: Update modifier list for gfx10_3
Date: Thu, 15 Apr 2021 16:06:48 +0000	[thread overview]
Message-ID: <DM6PR12MB2939FC23A4404409980F7D1AFB4D9@DM6PR12MB2939.namprd12.prod.outlook.com> (raw)
In-Reply-To: <CAP+8YyHU8GtCzFk71h1qjQWKYQpMwrA=s88dw2Fu3_0LXSMEWA@mail.gmail.com>


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[AMD Public Use]

Inline.

From: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Sent: Thursday, April 15, 2021 7:26 AM
To: Zhuo, Qingqing <Qingqing.Zhuo@amd.com>
Cc: amd-gfx mailing list <amd-gfx@lists.freedesktop.org>; Mark Yacoub <markyacoub@chromium.org>; Deucher, Alexander <Alexander.Deucher@amd.com>; Wheeler, Daniel <Daniel.Wheeler@amd.com>; Siqueira, Rodrigo <Rodrigo.Siqueira@amd.com>; Kazlauskas, Nicholas <Nicholas.Kazlauskas@amd.com>
Subject: Re: [PATCH 1/2] drm/amd/display: Update modifier list for gfx10_3



On Thu, Apr 15, 2021 at 1:35 AM Qingqing Zhuo <qingqing.zhuo@amd.com<mailto:qingqing.zhuo@amd.com>> wrote:
[Why]
Current list only includes modifiers where DCC_MAX_COMPRESSED_BLOCK
is set to AMD_FMT_MOD_DCC_BLOCK_128B, while AMD_FMT_MOD_DCC_BLOCK_64B
is also supported and used by userspace.

[How]
Add AMD_FMT_MOD_DCC_BLOCK_64B to modifiers with DCC supported.

Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com<mailto:qingqing.zhuo@amd.com>>
---
 .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 23 +++++++++++++++++++
 1 file changed, 23 insertions(+)

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e29cb2e956db..c3cbc3d298e7 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4535,6 +4535,17 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
        int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes);
        int pkrs = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs);

+       add_modifier(mods, size, capacity, AMD_FMT_MOD |
+                   AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+                   AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+                   AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+                   AMD_FMT_MOD_SET(PACKERS, pkrs) |
+                   AMD_FMT_MOD_SET(DCC, 1) |
+                   AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+                   AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+                   AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+                   AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));

Thanks for finding this issue. Looking at it it looks to me like the original entries are mistaken. Can we just change the  DCC_MAX_COMPRESSED_BLOCK in the already existing DCC entries? Looks like Mesa always uses the AMD_FMT_MOD_DCC_BLOCK_64B anyway, and I don't think DCC_INDEPENDENT_64B=1 + DCC_MAX_COMPRESSED_BLOCK=AMD_FMT_MOD_DCC_BLOCK_128B makes sense.

Thanks for the suggestion. Will send out an updated version soon.

+
        add_modifier(mods, size, capacity, AMD_FMT_MOD |
                    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
                    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
@@ -4546,6 +4557,18 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
                    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
                    AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));

+       add_modifier(mods, size, capacity, AMD_FMT_MOD |
+                   AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
+                   AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
+                   AMD_FMT_MOD_SET(PIPE_XOR_BITS, pipe_xor_bits) |
+                   AMD_FMT_MOD_SET(PACKERS, pkrs) |
+                   AMD_FMT_MOD_SET(DCC, 1) |
+                   AMD_FMT_MOD_SET(DCC_RETILE, 1) |
+                   AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
+                   AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
+                   AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
+                   AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
+
        add_modifier(mods, size, capacity, AMD_FMT_MOD |
                    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
                    AMD_FMT_MOD_SET(TILE_VERSION, AMD_FMT_MOD_TILE_VER_GFX10_RBPLUS) |
--
2.17.1

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_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

  reply	other threads:[~2021-04-15 16:06 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-14 23:35 [PATCH 1/2] drm/amd/display: Update modifier list for gfx10_3 Qingqing Zhuo
2021-04-14 23:35 ` [PATCH 2/2] Revert "Revert "drm/amdgpu: Ensure that the modifier requested is supported by plane."" Qingqing Zhuo
2021-04-15 14:20   ` Mark Yacoub
2021-05-09 12:10   ` youling257
2021-05-09 15:52     ` Alex Deucher
2021-05-09 20:51       ` youling 257
2021-05-09 20:57         ` Bas Nieuwenhuizen
2021-05-09 21:42           ` youling 257
2021-05-10  2:09             ` youling 257
2021-05-10 15:18               ` Mark Yacoub
2021-05-10 16:32                 ` youling 257
2021-05-10 16:45                   ` youling 257
2021-05-10 16:50                     ` Mark Yacoub
2021-05-10 17:05                       ` youling 257
2021-05-10 17:24                         ` youling 257
2022-06-13 23:37                           ` Mike Lothian
2021-05-10 17:30                       ` youling 257
2021-04-15 11:25 ` [PATCH 1/2] drm/amd/display: Update modifier list for gfx10_3 Bas Nieuwenhuizen
2021-04-15 16:06   ` Zhuo, Qingqing [this message]
2021-04-15 16:27     ` Bas Nieuwenhuizen
2021-04-15 17:37       ` Zhuo, Qingqing

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