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Wed, 3 Jun 2020 11:20:16 +0000 Received: from DM6PR18MB2425.namprd18.prod.outlook.com ([fe80::9da1:54e3:fdf6:e746]) by DM6PR18MB2425.namprd18.prod.outlook.com ([fe80::9da1:54e3:fdf6:e746%6]) with mapi id 15.20.3045.024; Wed, 3 Jun 2020 11:20:16 +0000 From: Kamlakant Patel To: Bhupesh Sharma , "linux-arm-kernel@lists.infradead.org" , "x86@kernel.org" CC: Mark Rutland , Kazuhito Hagio , Steve Capper , Catalin Marinas , Ard Biesheuvel , "kexec@lists.infradead.org" , "linux-kernel@vger.kernel.org" , James Morse , Dave Anderson , "bhupesh.linux@gmail.com" , Will Deacon , Ganapatrao Kulkarni Subject: RE: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Thread-Topic: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Thread-Index: AQHWK50dN2j16dwzSEeEnQAXi/17t6jG1pOA Date: Wed, 3 Jun 2020 11:20:16 +0000 Message-ID: References: <1589395957-24628-1-git-send-email-bhsharma@redhat.com> <1589395957-24628-3-git-send-email-bhsharma@redhat.com> In-Reply-To: <1589395957-24628-3-git-send-email-bhsharma@redhat.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: redhat.com; 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x-ms-exchange-antispam-messagedata: qe2q4cY66ujk0ubpqiINerKCNVPDnbXZOB7mPtkviMENfMa1Bq9uTo8c3SJWeDTg6RSVtVBCnAmodeWpcgtIW5+a/3zlmWhT7GLYGj7hfKHj/Sm2+9GY9gQuxpmQbGU1pzJ2ZJdMHMQWLVGVP4Y1KHGK7j8aYz12Zg9Wg8zKy3Y5M3CP15iIpMNoPi3NLUKvkFwaSe568svPCOzHHYh7uSguzCo1WV0CrPzzEEz4EkfcByW/09vw55cv756zxKmraEG0I5jssG/VF54GdanmkdNyDigkw404l8XrTrQnew3pPZy/Hrlj8cGE28CjVCMzVWGO53++ErZ+D8/L6RaP5OtyrZf5tb0uZTFYZ/hLK4rTqTSHFf4GbBRxO5kogtTG3aJlDYKzMyj3DlvYFeg5vlgL/K3WqdKVjnO4ka1fOesZHHt3ObEK/5RkEs6cfu1PdXl03dpjMi17ISaAyBOzQIkBQqDxJIpSDxEuvJ828iQ= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f3144eb2-82c1-4d07-4150-08d807b017da X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Jun 2020 11:20:16.7044 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vaqvLrTQXECV2S9t15CiXFOX1IJsc3rXXbLRH4Vnz1knl+FejX95hQwzbIdplZGzturl8EHX38VG6zaYj2ey2Q== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR18MB3604 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.216,18.0.687 definitions=2020-06-03_11:2020-06-02,2020-06-03 signatures=0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bhupesh, > -----Original Message----- > From: kexec On Behalf Of Bhupesh > Sharma > Sent: Thursday, May 14, 2020 12:23 AM > To: linux-arm-kernel@lists.infradead.org; x86@kernel.org > Cc: Mark Rutland ; Kazuhito Hagio hagio@ab.jp.nec.com>; Steve Capper ; Catalin > Marinas ; bhsharma@redhat.com; Ard Biesheuvel > ; kexec@lists.infradead.org; linux- > kernel@vger.kernel.org; James Morse ; Dave > Anderson ; bhupesh.linux@gmail.com; Will Deacon > > Subject: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcorein= fo >=20 > vabits_actual variable on arm64 indicates the actual VA space size, and a= llows a > single binary to support both 48-bit and 52-bit VA spaces. >=20 > If the ARMv8.2-LVA optional feature is present, and we are running with a= 64KB > page size; then it is possible to use 52-bits of address space for both u= serspace > and kernel addresses. However, any kernel binary that supports 52-bit mus= t also > be able to fall back to 48-bit at early boot time if the hardware feature= is not > present. >=20 > Since TCR_EL1.T1SZ indicates the size offset of the memory region address= ed by > TTBR1_EL1 (and hence can be used for determining the vabits_actual value)= it > makes more sense to export the same in vmcoreinfo rather than vabits_actu= al > variable, as the name of the variable can change in future kernel version= s, but > the architectural constructs like TCR_EL1.T1SZ can be used better to indi= cate > intended specific fields to user-space. >=20 > User-space utilities like makedumpfile and crash-utility, need to read th= is value > from vmcoreinfo for determining if a virtual address lies in the linear m= ap range. >=20 > While at it also add documentation for TCR_EL1.T1SZ variable being added = to > vmcoreinfo. >=20 > It indicates the size offset of the memory region addressed by TTBR1_EL1 >=20 > Cc: James Morse > Cc: Mark Rutland > Cc: Will Deacon > Cc: Steve Capper > Cc: Catalin Marinas > Cc: Ard Biesheuvel > Cc: Dave Anderson > Cc: Kazuhito Hagio > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: kexec@lists.infradead.org > Tested-by: John Donnelly > Signed-off-by: Bhupesh Sharma > --- > Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ > arch/arm64/include/asm/pgtable-hwdef.h | 1 + > arch/arm64/kernel/crash_core.c | 10 ++++++++++ > 3 files changed, 22 insertions(+) >=20 > diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst > b/Documentation/admin-guide/kdump/vmcoreinfo.rst > index 2a632020f809..2baad0bfb09d 100644 > --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst > +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst > @@ -404,6 +404,17 @@ KERNELPACMASK > The mask to extract the Pointer Authentication Code from a kernel virtua= l > address. >=20 > +TCR_EL1.T1SZ > +------------ > + > +Indicates the size offset of the memory region addressed by TTBR1_EL1. > +The region size is 2^(64-T1SZ) bytes. > + > +TTBR1_EL1 is the table base address register specified by ARMv8-A > +architecture which is used to lookup the page-tables for the Virtual > +addresses in the higher VA range (refer to ARMv8 ARM document for more > +details). > + > arm > =3D=3D=3D >=20 > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h > b/arch/arm64/include/asm/pgtable-hwdef.h > index 6bf5e650da78..a1861af97ac9 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -216,6 +216,7 @@ > #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) > #define TCR_TxSZ_WIDTH 6 > #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << > TCR_T0SZ_OFFSET) > +#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << > TCR_T1SZ_OFFSET) >=20 > #define TCR_EPD0_SHIFT 7 > #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) > diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_cor= e.c > index 1f646b07e3e9..314391a156ee 100644 > --- a/arch/arm64/kernel/crash_core.c > +++ b/arch/arm64/kernel/crash_core.c > @@ -7,6 +7,14 @@ > #include > #include > #include > +#include > + > +static inline u64 get_tcr_el1_t1sz(void); > + > +static inline u64 get_tcr_el1_t1sz(void) { > + return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; } >=20 > void arch_crash_save_vmcoreinfo(void) > { > @@ -16,6 +24,8 @@ void arch_crash_save_vmcoreinfo(void) > kimage_voffset); > vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=3D0x%llx\n", > PHYS_OFFSET); > + vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=3D0x%llx\n", > + get_tcr_el1_t1sz()); I tested this patch on top of upstream kernel v5.7 and I am getting "crash:= cannot determine VA_BITS_ACTUAL" error with crash tool. I looked into crash-utility source and it is expecting tcr_el1_t1sz not TCR= _EL1_T1SZ. Could you please check. Thanks, Kamlakant Patel > vmcoreinfo_append_str("KERNELOFFSET=3D%lx\n", kaslr_offset()); > vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=3D0x%llx\n", >=20 > system_supports_address_auth() ? > -- > 2.7.4 >=20 >=20 > _______________________________________________ > kexec mailing list > kexec@lists.infradead.org > https://urldefense.proofpoint.com/v2/url?u=3Dhttp- > 3A__lists.infradead.org_mailman_listinfo_kexec&d=3DDwICAg&c=3DnKjWec2b6R0= m > OyPaz7xtfQ&r=3DXecQZQJWhG6- > mN8sWxffFOgUXg4irGP3Sjuy6RxdacQ&m=3DoeLdIVaWScimdfEc4dNhRI0tT24IgzG > 7LkpAE5P11JQ&s=3DLLjHpz349DuDtORX4xywCxzbGUOagoq4JXosStycqI4&e=3D From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A850C433E0 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Bhupesh, > -----Original Message----- > From: kexec On Behalf Of Bhupesh > Sharma > Sent: Thursday, May 14, 2020 12:23 AM > To: linux-arm-kernel@lists.infradead.org; x86@kernel.org > Cc: Mark Rutland ; Kazuhito Hagio hagio@ab.jp.nec.com>; Steve Capper ; Catalin > Marinas ; bhsharma@redhat.com; Ard Biesheuvel > ; kexec@lists.infradead.org; linux- > kernel@vger.kernel.org; James Morse ; Dave > Anderson ; bhupesh.linux@gmail.com; Will Deacon > > Subject: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo > > vabits_actual variable on arm64 indicates the actual VA space size, and allows a > single binary to support both 48-bit and 52-bit VA spaces. > > If the ARMv8.2-LVA optional feature is present, and we are running with a 64KB > page size; then it is possible to use 52-bits of address space for both userspace > and kernel addresses. However, any kernel binary that supports 52-bit must also > be able to fall back to 48-bit at early boot time if the hardware feature is not > present. > > Since TCR_EL1.T1SZ indicates the size offset of the memory region addressed by > TTBR1_EL1 (and hence can be used for determining the vabits_actual value) it > makes more sense to export the same in vmcoreinfo rather than vabits_actual > variable, as the name of the variable can change in future kernel versions, but > the architectural constructs like TCR_EL1.T1SZ can be used better to indicate > intended specific fields to user-space. > > User-space utilities like makedumpfile and crash-utility, need to read this value > from vmcoreinfo for determining if a virtual address lies in the linear map range. > > While at it also add documentation for TCR_EL1.T1SZ variable being added to > vmcoreinfo. > > It indicates the size offset of the memory region addressed by TTBR1_EL1 > > Cc: James Morse > Cc: Mark Rutland > Cc: Will Deacon > Cc: Steve Capper > Cc: Catalin Marinas > Cc: Ard Biesheuvel > Cc: Dave Anderson > Cc: Kazuhito Hagio > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: kexec@lists.infradead.org > Tested-by: John Donnelly > Signed-off-by: Bhupesh Sharma > --- > Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ > arch/arm64/include/asm/pgtable-hwdef.h | 1 + > arch/arm64/kernel/crash_core.c | 10 ++++++++++ > 3 files changed, 22 insertions(+) > > diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst > b/Documentation/admin-guide/kdump/vmcoreinfo.rst > index 2a632020f809..2baad0bfb09d 100644 > --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst > +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst > @@ -404,6 +404,17 @@ KERNELPACMASK > The mask to extract the Pointer Authentication Code from a kernel virtual > address. > > +TCR_EL1.T1SZ > +------------ > + > +Indicates the size offset of the memory region addressed by TTBR1_EL1. > +The region size is 2^(64-T1SZ) bytes. > + > +TTBR1_EL1 is the table base address register specified by ARMv8-A > +architecture which is used to lookup the page-tables for the Virtual > +addresses in the higher VA range (refer to ARMv8 ARM document for more > +details). > + > arm > === > > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h > b/arch/arm64/include/asm/pgtable-hwdef.h > index 6bf5e650da78..a1861af97ac9 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -216,6 +216,7 @@ > #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) > #define TCR_TxSZ_WIDTH 6 > #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << > TCR_T0SZ_OFFSET) > +#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << > TCR_T1SZ_OFFSET) > > #define TCR_EPD0_SHIFT 7 > #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) > diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c > index 1f646b07e3e9..314391a156ee 100644 > --- a/arch/arm64/kernel/crash_core.c > +++ b/arch/arm64/kernel/crash_core.c > @@ -7,6 +7,14 @@ > #include > #include > #include > +#include > + > +static inline u64 get_tcr_el1_t1sz(void); > + > +static inline u64 get_tcr_el1_t1sz(void) { > + return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; } > > void arch_crash_save_vmcoreinfo(void) > { > @@ -16,6 +24,8 @@ void arch_crash_save_vmcoreinfo(void) > kimage_voffset); > vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n", > PHYS_OFFSET); > + vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n", > + get_tcr_el1_t1sz()); I tested this patch on top of upstream kernel v5.7 and I am getting "crash: cannot determine VA_BITS_ACTUAL" error with crash tool. I looked into crash-utility source and it is expecting tcr_el1_t1sz not TCR_EL1_T1SZ. Could you please check. Thanks, Kamlakant Patel > vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset()); > vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n", > > system_supports_address_auth() ? > -- > 2.7.4 > > > _______________________________________________ > kexec mailing list > kexec@lists.infradead.org > https://urldefense.proofpoint.com/v2/url?u=http- > 3A__lists.infradead.org_mailman_listinfo_kexec&d=DwICAg&c=nKjWec2b6R0m > OyPaz7xtfQ&r=XecQZQJWhG6- > mN8sWxffFOgUXg4irGP3Sjuy6RxdacQ&m=oeLdIVaWScimdfEc4dNhRI0tT24IgzG > 7LkpAE5P11JQ&s=LLjHpz349DuDtORX4xywCxzbGUOagoq4JXosStycqI4&e= _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: From: Kamlakant Patel Subject: RE: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo Date: Wed, 3 Jun 2020 11:20:16 +0000 Message-ID: References: <1589395957-24628-1-git-send-email-bhsharma@redhat.com> <1589395957-24628-3-git-send-email-bhsharma@redhat.com> In-Reply-To: <1589395957-24628-3-git-send-email-bhsharma@redhat.com> Content-Language: en-US MIME-Version: 1.0 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kexec" Errors-To: kexec-bounces+dwmw2=infradead.org@lists.infradead.org To: Bhupesh Sharma , "linux-arm-kernel@lists.infradead.org" , "x86@kernel.org" Cc: Mark Rutland , Kazuhito Hagio , Ganapatrao Kulkarni , Ard Biesheuvel , Catalin Marinas , Steve Capper , "kexec@lists.infradead.org" , "linux-kernel@vger.kernel.org" , James Morse , Dave Anderson , "bhupesh.linux@gmail.com" , Will Deacon Hi Bhupesh, > -----Original Message----- > From: kexec On Behalf Of Bhupesh > Sharma > Sent: Thursday, May 14, 2020 12:23 AM > To: linux-arm-kernel@lists.infradead.org; x86@kernel.org > Cc: Mark Rutland ; Kazuhito Hagio hagio@ab.jp.nec.com>; Steve Capper ; Catalin > Marinas ; bhsharma@redhat.com; Ard Biesheuvel > ; kexec@lists.infradead.org; linux- > kernel@vger.kernel.org; James Morse ; Dave > Anderson ; bhupesh.linux@gmail.com; Will Deacon > > Subject: [PATCH v6 2/2] arm64/crash_core: Export TCR_EL1.T1SZ in vmcoreinfo > > vabits_actual variable on arm64 indicates the actual VA space size, and allows a > single binary to support both 48-bit and 52-bit VA spaces. > > If the ARMv8.2-LVA optional feature is present, and we are running with a 64KB > page size; then it is possible to use 52-bits of address space for both userspace > and kernel addresses. However, any kernel binary that supports 52-bit must also > be able to fall back to 48-bit at early boot time if the hardware feature is not > present. > > Since TCR_EL1.T1SZ indicates the size offset of the memory region addressed by > TTBR1_EL1 (and hence can be used for determining the vabits_actual value) it > makes more sense to export the same in vmcoreinfo rather than vabits_actual > variable, as the name of the variable can change in future kernel versions, but > the architectural constructs like TCR_EL1.T1SZ can be used better to indicate > intended specific fields to user-space. > > User-space utilities like makedumpfile and crash-utility, need to read this value > from vmcoreinfo for determining if a virtual address lies in the linear map range. > > While at it also add documentation for TCR_EL1.T1SZ variable being added to > vmcoreinfo. > > It indicates the size offset of the memory region addressed by TTBR1_EL1 > > Cc: James Morse > Cc: Mark Rutland > Cc: Will Deacon > Cc: Steve Capper > Cc: Catalin Marinas > Cc: Ard Biesheuvel > Cc: Dave Anderson > Cc: Kazuhito Hagio > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Cc: kexec@lists.infradead.org > Tested-by: John Donnelly > Signed-off-by: Bhupesh Sharma > --- > Documentation/admin-guide/kdump/vmcoreinfo.rst | 11 +++++++++++ > arch/arm64/include/asm/pgtable-hwdef.h | 1 + > arch/arm64/kernel/crash_core.c | 10 ++++++++++ > 3 files changed, 22 insertions(+) > > diff --git a/Documentation/admin-guide/kdump/vmcoreinfo.rst > b/Documentation/admin-guide/kdump/vmcoreinfo.rst > index 2a632020f809..2baad0bfb09d 100644 > --- a/Documentation/admin-guide/kdump/vmcoreinfo.rst > +++ b/Documentation/admin-guide/kdump/vmcoreinfo.rst > @@ -404,6 +404,17 @@ KERNELPACMASK > The mask to extract the Pointer Authentication Code from a kernel virtual > address. > > +TCR_EL1.T1SZ > +------------ > + > +Indicates the size offset of the memory region addressed by TTBR1_EL1. > +The region size is 2^(64-T1SZ) bytes. > + > +TTBR1_EL1 is the table base address register specified by ARMv8-A > +architecture which is used to lookup the page-tables for the Virtual > +addresses in the higher VA range (refer to ARMv8 ARM document for more > +details). > + > arm > === > > diff --git a/arch/arm64/include/asm/pgtable-hwdef.h > b/arch/arm64/include/asm/pgtable-hwdef.h > index 6bf5e650da78..a1861af97ac9 100644 > --- a/arch/arm64/include/asm/pgtable-hwdef.h > +++ b/arch/arm64/include/asm/pgtable-hwdef.h > @@ -216,6 +216,7 @@ > #define TCR_TxSZ(x) (TCR_T0SZ(x) | TCR_T1SZ(x)) > #define TCR_TxSZ_WIDTH 6 > #define TCR_T0SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << > TCR_T0SZ_OFFSET) > +#define TCR_T1SZ_MASK (((UL(1) << TCR_TxSZ_WIDTH) - 1) << > TCR_T1SZ_OFFSET) > > #define TCR_EPD0_SHIFT 7 > #define TCR_EPD0_MASK (UL(1) << TCR_EPD0_SHIFT) > diff --git a/arch/arm64/kernel/crash_core.c b/arch/arm64/kernel/crash_core.c > index 1f646b07e3e9..314391a156ee 100644 > --- a/arch/arm64/kernel/crash_core.c > +++ b/arch/arm64/kernel/crash_core.c > @@ -7,6 +7,14 @@ > #include > #include > #include > +#include > + > +static inline u64 get_tcr_el1_t1sz(void); > + > +static inline u64 get_tcr_el1_t1sz(void) { > + return (read_sysreg(tcr_el1) & TCR_T1SZ_MASK) >> TCR_T1SZ_OFFSET; } > > void arch_crash_save_vmcoreinfo(void) > { > @@ -16,6 +24,8 @@ void arch_crash_save_vmcoreinfo(void) > kimage_voffset); > vmcoreinfo_append_str("NUMBER(PHYS_OFFSET)=0x%llx\n", > PHYS_OFFSET); > + vmcoreinfo_append_str("NUMBER(TCR_EL1_T1SZ)=0x%llx\n", > + get_tcr_el1_t1sz()); I tested this patch on top of upstream kernel v5.7 and I am getting "crash: cannot determine VA_BITS_ACTUAL" error with crash tool. I looked into crash-utility source and it is expecting tcr_el1_t1sz not TCR_EL1_T1SZ. Could you please check. Thanks, Kamlakant Patel > vmcoreinfo_append_str("KERNELOFFSET=%lx\n", kaslr_offset()); > vmcoreinfo_append_str("NUMBER(KERNELPACMASK)=0x%llx\n", > > system_supports_address_auth() ? > -- > 2.7.4 > > > _______________________________________________ > kexec mailing list > kexec@lists.infradead.org > https://urldefense.proofpoint.com/v2/url?u=http- > 3A__lists.infradead.org_mailman_listinfo_kexec&d=DwICAg&c=nKjWec2b6R0m > OyPaz7xtfQ&r=XecQZQJWhG6- > mN8sWxffFOgUXg4irGP3Sjuy6RxdacQ&m=oeLdIVaWScimdfEc4dNhRI0tT24IgzG > 7LkpAE5P11JQ&s=LLjHpz349DuDtORX4xywCxzbGUOagoq4JXosStycqI4&e= _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec