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From: "Ravich, Leonid" <Leonid.Ravich@dell.com>
To: "gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
	"Idgar, Or" <Or.Idgar@Dell.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-mm@kvack.org" <linux-mm@kvack.org>
Subject: RE: CMA enhancement - non-default areas in x86
Date: Wed, 13 May 2020 08:29:16 +0000	[thread overview]
Message-ID: <DM6PR19MB26827EFC4DDC6CB9DD5C52D098BF0@DM6PR19MB2682.namprd19.prod.outlook.com> (raw)
In-Reply-To: <20200513071413.GB766804@kroah.com>

PCIe NTB 
Documentation/driver-api/ntb.rst

1) Basically PCI bridge between to root complex / PCI switches 
2) using out of OS memory is one solution but then this memory is
Limited for usage by other stack, ex: get_user_pages on this memory will fail, 
Therefore attempting to use it for block layer with (o_direct) will fail. 
 
Acutely any generic stack which attempts to "pin" this memory will fail.

Leonid Ravich 
> -----Original Message-----
> From: gregkh@linuxfoundation.org <gregkh@linuxfoundation.org>
> Sent: Wednesday, May 13, 2020 10:14 AM
> To: Idgar, Or
> Cc: linux-kernel@vger.kernel.org; linux-mm@kvack.org; Ravich, Leonid
> Subject: Re: CMA enhancement - non-default areas in x86
> 
> On Wed, May 13, 2020 at 07:00:12AM +0000, Idgar, Or wrote:
> > > For what type of device?
> > NTB (Non-Transparent Bridge).
> 
> 
> Very odd quoting style...
> 
> Anyway, what exactly is a non-transparent bridge, and why doesn't your
> bios/uefi implementation properly reserve the memory for it so that the OS
> does not use it?
> 
> thanks,
> 
> greg k-h

  reply	other threads:[~2020-05-13  8:29 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-13  6:13 CMA enhancement - non-default areas in x86 Idgar, Or
2020-05-13  6:47 ` gregkh
2020-05-13  7:00   ` Idgar, Or
2020-05-13  7:14     ` gregkh
2020-05-13  8:29       ` Ravich, Leonid [this message]
2020-05-13  8:33         ` gregkh
2020-05-13  9:43           ` Ravich, Leonid
2020-05-13 10:04             ` gregkh

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