From: "Zhou, Peng Ju" <PengJu.Zhou@amd.com>
To: "Sun, Roy" <Roy.Sun@amd.com>, "Sun, Roy" <Roy.Sun@amd.com>,
"amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH] drm/amdgpu: change the imprecise function name
Date: Tue, 13 Jul 2021 06:23:28 +0000 [thread overview]
Message-ID: <DM8PR12MB54783747F1CA59D5275B6C39F8149@DM8PR12MB5478.namprd12.prod.outlook.com> (raw)
In-Reply-To: <CY4PR12MB16061F0BE2713F05A08E3675FF199@CY4PR12MB1606.namprd12.prod.outlook.com>
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[AMD Official Use Only]
Reviewed-by: Peng Ju Zhou <PengJu.Zhou@amd.com>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Sun,
> Roy
> Sent: Thursday, July 8, 2021 6:25 PM
> To: Sun, Roy <Roy.Sun@amd.com>; amd-gfx@lists.freedesktop.org
> Subject: RE: [PATCH] drm/amdgpu: change the imprecise function name
>
> [AMD Official Use Only]
>
> Ping
>
> -----Original Message-----
> From: Roy Sun <Roy.Sun@amd.com>
> Sent: Wednesday, July 7, 2021 4:11 PM
> To: amd-gfx@lists.freedesktop.org
> Cc: Sun, Roy <Roy.Sun@amd.com>
> Subject: [PATCH] drm/amdgpu: change the imprecise function name
>
> The callback functions are used for SRIOV read/write instead of just for rlcg
> read/write
>
> Signed-off-by: Roy Sun <Roy.Sun@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 4 ++--
> drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 8 ++++----
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 4 ++--
> drivers/gpu/drm/amd/amdgpu/soc15_common.h | 8 ++++----
> 5 files changed, 13 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index eb1f3f42e00b..aa94ad0e9973 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -508,7 +508,7 @@ void amdgpu_mm_wreg_mmio_rlc(struct
> amdgpu_device *adev,
> adev->gfx.rlc.funcs &&
> adev->gfx.rlc.funcs->is_rlcg_access_range) {
> if (adev->gfx.rlc.funcs->is_rlcg_access_range(adev, reg))
> - return adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, v, 0,
> 0);
> + return adev->gfx.rlc.funcs->sriov_wreg(adev, reg, v, 0,
> 0);
> } else {
> writel(v, ((void __iomem *)adev->rmmio) + (reg * 4));
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> index 7a4775ab6804..00afd0dcae86 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h
> @@ -127,8 +127,8 @@ struct amdgpu_rlc_funcs {
> void (*reset)(struct amdgpu_device *adev);
> void (*start)(struct amdgpu_device *adev);
> void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned
> vmid);
> - void (*rlcg_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> acc_flags, u32 hwip);
> - u32 (*rlcg_rreg)(struct amdgpu_device *adev, u32 offset, u32 acc_flags,
> u32 hwip);
> + void (*sriov_wreg)(struct amdgpu_device *adev, u32 offset, u32 v, u32
> acc_flags, u32 hwip);
> + u32 (*sriov_rreg)(struct amdgpu_device *adev, u32 offset, u32
> +acc_flags, u32 hwip);
> bool (*is_rlcg_access_range)(struct amdgpu_device *adev, uint32_t
> reg); };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 705fa3027199..bc4347a72301 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -1542,7 +1542,7 @@ static u32 gfx_v10_rlcg_rw(struct amdgpu_device
> *adev, u32 offset, u32 v, uint32
> return ret;
> }
>
> -static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32
> value, u32 acc_flags, u32 hwip)
> +static void gfx_v10_sriov_wreg(struct amdgpu_device *adev, u32 offset,
> +u32 value, u32 acc_flags, u32 hwip)
> {
> u32 rlcg_flag;
>
> @@ -1558,7 +1558,7 @@ static void gfx_v10_rlcg_wreg(struct amdgpu_device
> *adev, u32 offset, u32 value,
> WREG32(offset, value);
> }
>
> -static u32 gfx_v10_rlcg_rreg(struct amdgpu_device *adev, u32 offset, u32
> acc_flags, u32 hwip)
> +static u32 gfx_v10_sriov_rreg(struct amdgpu_device *adev, u32 offset,
> +u32 acc_flags, u32 hwip)
> {
> u32 rlcg_flag;
>
> @@ -8269,8 +8269,8 @@ static const struct amdgpu_rlc_funcs
> gfx_v10_0_rlc_funcs_sriov = {
> .reset = gfx_v10_0_rlc_reset,
> .start = gfx_v10_0_rlc_start,
> .update_spm_vmid = gfx_v10_0_update_spm_vmid,
> - .rlcg_wreg = gfx_v10_rlcg_wreg,
> - .rlcg_rreg = gfx_v10_rlcg_rreg,
> + .sriov_wreg = gfx_v10_sriov_wreg,
> + .sriov_rreg = gfx_v10_sriov_rreg,
> .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range, };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 044076ec1d03..03acc777adf7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -787,7 +787,7 @@ static void gfx_v9_0_rlcg_w(struct amdgpu_device
> *adev, u32 offset, u32 v, u32 f
>
> }
>
> -static void gfx_v9_0_rlcg_wreg(struct amdgpu_device *adev, u32 offset,
> +static void gfx_v9_0_sriov_wreg(struct amdgpu_device *adev, u32 offset,
> u32 v, u32 acc_flags, u32 hwip) {
> if ((acc_flags & AMDGPU_REGS_RLC) &&
> @@ -5131,7 +5131,7 @@ static const struct amdgpu_rlc_funcs
> gfx_v9_0_rlc_funcs = {
> .reset = gfx_v9_0_rlc_reset,
> .start = gfx_v9_0_rlc_start,
> .update_spm_vmid = gfx_v9_0_update_spm_vmid,
> - .rlcg_wreg = gfx_v9_0_rlcg_wreg,
> + .sriov_wreg = gfx_v9_0_sriov_wreg,
> .is_rlcg_access_range = gfx_v9_0_is_rlcg_access_range, };
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> index 0eeb5e073be8..8a9ca87d8663 100644
> --- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> +++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
> @@ -28,13 +28,13 @@
> #define SOC15_REG_OFFSET(ip, inst, reg) (adev-
> >reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>
> #define __WREG32_SOC15_RLC__(reg, value, flag, hwip) \
> - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev-
> >gfx.rlc.funcs->rlcg_wreg) ? \
> - adev->gfx.rlc.funcs->rlcg_wreg(adev, reg, value, flag, hwip) : \
> + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev-
> >gfx.rlc.funcs->sriov_wreg) ? \
> + adev->gfx.rlc.funcs->sriov_wreg(adev, reg, value, flag, hwip) : \
> WREG32(reg, value))
>
> #define __RREG32_SOC15_RLC__(reg, flag, hwip) \
> - ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev-
> >gfx.rlc.funcs->rlcg_rreg) ? \
> - adev->gfx.rlc.funcs->rlcg_rreg(adev, reg, flag, hwip) : \
> + ((amdgpu_sriov_vf(adev) && adev->gfx.rlc.funcs && adev-
> >gfx.rlc.funcs->sriov_rreg) ? \
> + adev->gfx.rlc.funcs->sriov_rreg(adev, reg, flag, hwip) : \
> RREG32(reg))
>
> #define WREG32_FIELD15(ip, idx, reg, field, val) \
> --
> 2.32.0
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prev parent reply other threads:[~2021-07-13 6:23 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-07 8:10 [PATCH] drm/amdgpu: change the imprecise function name Roy Sun
2021-07-08 10:24 ` Sun, Roy
2021-07-13 6:23 ` Zhou, Peng Ju [this message]
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