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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DU0PR04MB9417.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: fe53a7d6-3831-4786-9a52-08dad0ec7f70 X-MS-Exchange-CrossTenant-originalarrivaltime: 28 Nov 2022 02:58:59.4823 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jJeyjhT4MXKBuN0XKSta7eCt1IibjbD9F+mw6j9wYFnN3M58jt1+Lx5YU9KySItpsjbZu5nmjbaOYaifAyDnEA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM0PR04MB6849 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org > Subject: [PATCH 5/5] thermal/drivers/imx: Add support for loading calibra= tion > data from OCOTP >=20 > The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with > calibration values in OCOTP. Add support for reading the OCOTP calibratio= n > data and programming those into the TMU hardware. >=20 > The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 > uses 4, the programming differs in each case. >=20 > Based on U-Boot commits: > 70487ff386c ("imx8mm: Load fuse for TMU TCALIV and TASR") ebb9aab318b > ("imx: load calibration parameters from fuse for i.MX8MP") >=20 > Signed-off-by: Marek Vasut Looks good to me Reviewed-by: Peng Fan > --- > Cc: Adam Ford > Cc: Alice Guo > Cc: Amit Kucheria > Cc: Daniel Lezcano > Cc: Fabio Estevam > Cc: Krzysztof Kozlowski > Cc: Li Jun > Cc: Lucas Stach > Cc: Markus Niebel > Cc: NXP Linux Team > Cc: Peng Fan > Cc: Pengutronix Kernel Team > Cc: Rafael J. Wysocki > Cc: Richard Cochran > Cc: Rob Herring > Cc: Sascha Hauer > Cc: Shawn Guo > Cc: Zhang Rui > Cc: devicetree@vger.kernel.org > To: linux-pm@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > drivers/thermal/imx8mm_thermal.c | 163 > +++++++++++++++++++++++++++++++ > 1 file changed, 163 insertions(+) >=20 > diff --git a/drivers/thermal/imx8mm_thermal.c > b/drivers/thermal/imx8mm_thermal.c > index e2c2673025a7a..da09c00ac663a 100644 > --- a/drivers/thermal/imx8mm_thermal.c > +++ b/drivers/thermal/imx8mm_thermal.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -20,6 +21,22 @@ > #define TER 0x0 /* TMU enable */ > #define TPS 0x4 > #define TRITSR 0x20 /* TMU immediate temp */ > +/* TMU calibration data registers */ > +#define TASR 0x28 > +#define TASR_BUF_SLOPE_MASK GENMASK(19, 16) > +#define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */ > +#define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */ > +#define TCALIV(n) (0x30 + ((n) * 4)) > +#define TCALIV_EN BIT(31) > +#define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 > */ > +#define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */ > +#define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 > */ > +#define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 > */ > +#define TRIM 0x3c > +#define TRIM_BJT_CUR_MASK GENMASK(23, 20) > +#define TRIM_BGR_MASK GENMASK(31, 28) > +#define TRIM_VLSB_MASK GENMASK(15, 12) > +#define TRIM_EN_CH BIT(7) >=20 > #define TER_ADC_PD BIT(30) > #define TER_EN BIT(31) > @@ -32,6 +49,25 @@ > #define SIGN_BIT BIT(7) > #define TEMP_VAL_MASK GENMASK(6, 0) >=20 > +/* TMU OCOTP calibration data bitfields */ > +#define ANA0_EN BIT(25) > +#define ANA0_BUF_VREF_MASK GENMASK(24, 20) > +#define ANA0_BUF_SLOPE_MASK GENMASK(19, 16) > +#define ANA0_HR_MASK GENMASK(15, 8) > +#define ANA0_RT_MASK GENMASK(7, 0) > +#define TRIM2_VLSB_MASK GENMASK(23, 20) > +#define TRIM2_BGR_MASK GENMASK(19, 16) > +#define TRIM2_BJT_CUR_MASK GENMASK(15, 12) > +#define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8) > +#define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6) > +#define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28) > +#define TRIM3_TCA40_0_MASK GENMASK(27, 16) > +#define TRIM4_TCA40_1_MASK GENMASK(31, 20) > +#define TRIM4_TCA105_0_MASK GENMASK(19, 8) > +#define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0) > +#define TRIM5_TCA105_1_MASK GENMASK(23, 12) > +#define TRIM5_TCA25_1_MASK GENMASK(11, 0) > + > #define VER1_TEMP_LOW_LIMIT 10000 > #define VER2_TEMP_LOW_LIMIT -40000 > #define VER2_TEMP_HIGH_LIMIT 125000 > @@ -128,6 +164,129 @@ static void imx8mm_tmu_probe_sel_all(struct > imx8mm_tmu *tmu) > writel_relaxed(val, tmu->base + TPS); > } >=20 > +static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev, > + struct imx8mm_tmu *tmu) > +{ > + struct device *dev =3D &pdev->dev; > + u32 ana0; > + int ret; > + > + ret =3D nvmem_cell_read_u32(&pdev->dev, "calib", &ana0); > + if (ret) { > + dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n", > ret); > + return ret; > + } > + > + writel(FIELD_PREP(TASR_BUF_VREF_MASK, > + FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) | > + FIELD_PREP(TASR_BUF_SLOPE_MASK, > + FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)), > + tmu->base + TASR); > + > + writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, > ana0)) | > + FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0)) > | > + ((ana0 & ANA0_EN) ? TCALIV_EN : 0), > + tmu->base + TCALIV(0)); > + > + return 0; > +} > + > +static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev, > + struct imx8mm_tmu *tmu) > +{ > + struct device *dev =3D &pdev->dev; > + struct nvmem_cell *cell; > + u32 trim[4] =3D { 0 }; > + size_t len; > + void *buf; > + > + cell =3D nvmem_cell_get(dev, "calib"); > + if (IS_ERR(cell)) > + return PTR_ERR(cell); > + > + buf =3D nvmem_cell_read(cell, &len); > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) > + return PTR_ERR(buf); > + > + memcpy(trim, buf, min(len, sizeof(trim))); > + kfree(buf); > + > + if (len !=3D 16) { > + dev_err(dev, > + "OCOTP nvmem cell length is %ld, must be 16.\n", len); > + return -EINVAL; > + } > + > + /* Blank sample hardware */ > + if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) { > + /* Use a default 25C binary codes */ > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c), > + tmu->base + TCALIV(0)); > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c), > + tmu->base + TCALIV(1)); > + return 0; > + } > + > + writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK, > + FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) | > + FIELD_PREP(TASR_BUF_SLOPE_MASK, > + FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])), > + tmu->base + TASR); > + > + writel(FIELD_PREP(TRIM_BJT_CUR_MASK, > + FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) | > + FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK, > trim[0])) | > + FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK, > trim[0])) | > + TRIM_EN_CH, > + tmu->base + TRIM); > + > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, > + FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) | > + (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) << > 4)) | > + FIELD_PREP(TCALIV_SNSR105C_MASK, > + FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])), > + tmu->base + TCALIV(0)); > + > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, > + FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) | > + FIELD_PREP(TCALIV_SNSR105C_MASK, > + FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])), > + tmu->base + TCALIV(1)); > + > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, > + FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) | > + FIELD_PREP(TCALIV_SNSR105C_MASK, > + FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])), > + tmu->base + TCALIV(2)); > + > + return 0; > +} > + > +static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev, > + struct imx8mm_tmu *tmu) > +{ > + struct device *dev =3D &pdev->dev; > + > + /* > + * Lack of calibration data OCOTP reference is not considered > + * fatal to retain compatibility with old DTs. It is however > + * strongly recommended to update such old DTs to get correct > + * temperature compensation values for each SoC. > + */ > + if (!of_find_property(pdev->dev.of_node, "nvmem-cells", NULL)) { > + dev_warn(dev, > + "No OCOTP nvmem reference found, SoC-specific > calibration not loaded. Please update your DT.\n"); > + return 0; > + } > + > + if (tmu->socdata->version =3D=3D TMU_VER1) > + return imx8mm_tmu_probe_set_calib_v1(pdev, tmu); > + > + return imx8mm_tmu_probe_set_calib_v2(pdev, tmu); } > + > static int imx8mm_tmu_probe(struct platform_device *pdev) { > const struct thermal_soc_data *data; > @@ -180,6 +339,10 @@ static int imx8mm_tmu_probe(struct platform_device > *pdev) >=20 > platform_set_drvdata(pdev, tmu); >=20 > + ret =3D imx8mm_tmu_probe_set_calib(pdev, tmu); > + if (ret) > + goto disable_clk; > + > /* enable all the probes for V2 TMU */ > if (tmu->socdata->version =3D=3D TMU_VER2) > imx8mm_tmu_probe_sel_all(tmu); > -- > 2.35.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id BD39DC43217 for ; Mon, 28 Nov 2022 03:00:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References: Message-ID:Date:Subject:CC:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=DXmzY8yoplud6gqWpymbrJlatD6WMOdWUA/BgWDATfk=; b=Bj9ztryGH0zHrL e6vZ9FtD3ImXtaQ0wGbk0VIh6ftFU9aoglRn1g3DITyojNKG+e8qQGr8BsIDtbpvmN9QyzcOD3PWk IB+/qm9uPthyDQB7bM5qaQT+e2ESjpHwLdz70K13F1dmXQfytgGNBG99/RakV0dCtU8xbyJipFkZl f7rB6EqA+kqXewOCqXCV1F+UfRdFZ3VNYvRuuacQVysM8umftW9eqnhSPfEcJ2XxhTJGuo0iAoFiY UDSEqYFWdeRsSxgppkIQ+wRfTsPXLEy44BXuRCQQN82RgNdRN/gl60oNJ4N4u5k21sPySaazPAj07 5tVq+SCQwOvw/C7FVRLQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozUMN-00FHU2-Ln; Mon, 28 Nov 2022 02:59:07 +0000 Received: from mail-vi1eur04on0603.outbound.protection.outlook.com ([2a01:111:f400:fe0e::603] helo=EUR04-VI1-obe.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ozUMJ-00FHPW-Tk for linux-arm-kernel@lists.infradead.org; Mon, 28 Nov 2022 02:59:06 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=nEZnTCGgeX2uZpu0wzjphSIYPxD7BbBlzeGTThxTGT4YKYasKd7L1qDhRIqek6DBT/GKLEB9C631TW2MrJ0RCftB3acvgsCXnKkHSADNm4Bep28i4eC5mv0xhwg7oCuVwJyajf2oyLOn0O/qAm61YAbT1Ocpkp5IjrUL8DfySszXoZ36oJmpQJtzRL/AEQuG+klZzGfdmnYLAZTg1bZOo49JILcvfKXSm1wUfDIQ1fhHqZCLNYneNYafKfqaVS36m2ZwiJewgCkrDT+mEwnqKzskVG2rEozIDtTz40iC+ENJBtu9KRKyv4WuguuGuF60LECpvUgBgjwqBHVgxYOJ5Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=/7GlVdLtf3f4Nj7jHevGh3aJaA9jT+mEvw9hMyD2NwY=; b=KdLCeW1L/tBb7JFthyy/+QC0gRtRMQ4T2L14ibi9h2RmqPJqeacySQrFWxBT/zUIAcZ5+ALUhmF7ZT/z3JQHSTUmCF5fb2gjV5QD8onek8ycaoAG1a9d/olKA8+jQQouNzrZkalzOgYgha97eOgbQLpd4F2aAl6a1724b5J0PCT6Z+cJ0dnuRu5KneXAplb51bY4g2k0L2qFLWzAQglQE8sUqC2Wh3NF8BdwxCwKvGv2ZIyuYENnkuJ5XcGFBDtynPcBWTNhYBulH4h2OGu/oRVMeIJTgtZr4l5/OMKrSyyVB3TTv0KF4idPmLvqygqT2lphl7ojPlS6rrEk+RmGSQ== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=nxp.com; dmarc=pass action=none header.from=nxp.com; dkim=pass header.d=nxp.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nxp.com; s=selector2; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=/7GlVdLtf3f4Nj7jHevGh3aJaA9jT+mEvw9hMyD2NwY=; b=EWAM8BdMWJxRBHgygDsZI/zYGANcwmLLxbdHoNTOAPP1w6uXRv7nVyYjZHi8O8l45fIY9Cng3Hky6avqwx60ZqY/4SIJnXRGPdFC/TYpYCZfKD0xjom/atVtupJetvdAcypsERVD9xxXpTLR5KUqm22vRNYAoGtaefjquw/f0u4= Received: from DU0PR04MB9417.eurprd04.prod.outlook.com (2603:10a6:10:358::11) by AM0PR04MB6849.eurprd04.prod.outlook.com (2603:10a6:208:181::7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5857.19; Mon, 28 Nov 2022 02:58:59 +0000 Received: from DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::e33c:46f9:ef88:8973]) by DU0PR04MB9417.eurprd04.prod.outlook.com ([fe80::e33c:46f9:ef88:8973%5]) with mapi id 15.20.5857.023; Mon, 28 Nov 2022 02:58:59 +0000 From: Peng Fan To: Marek Vasut , "linux-pm@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" CC: Adam Ford , Alice Guo , Amit Kucheria , Daniel Lezcano , Fabio Estevam , Krzysztof Kozlowski , Jun Li , Lucas Stach , Markus Niebel , dl-linux-imx , Pengutronix Kernel Team , "Rafael J . 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org > Subject: [PATCH 5/5] thermal/drivers/imx: Add support for loading calibration > data from OCOTP > > The TMU TASR, TCALIVn, TRIM registers must be explicitly programmed with > calibration values in OCOTP. Add support for reading the OCOTP calibration > data and programming those into the TMU hardware. > > The MX8MM/MX8MN TMUv1 uses only one OCOTP cell, while MX8MP TMUv2 > uses 4, the programming differs in each case. > > Based on U-Boot commits: > 70487ff386c ("imx8mm: Load fuse for TMU TCALIV and TASR") ebb9aab318b > ("imx: load calibration parameters from fuse for i.MX8MP") > > Signed-off-by: Marek Vasut Looks good to me Reviewed-by: Peng Fan > --- > Cc: Adam Ford > Cc: Alice Guo > Cc: Amit Kucheria > Cc: Daniel Lezcano > Cc: Fabio Estevam > Cc: Krzysztof Kozlowski > Cc: Li Jun > Cc: Lucas Stach > Cc: Markus Niebel > Cc: NXP Linux Team > Cc: Peng Fan > Cc: Pengutronix Kernel Team > Cc: Rafael J. Wysocki > Cc: Richard Cochran > Cc: Rob Herring > Cc: Sascha Hauer > Cc: Shawn Guo > Cc: Zhang Rui > Cc: devicetree@vger.kernel.org > To: linux-pm@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > drivers/thermal/imx8mm_thermal.c | 163 > +++++++++++++++++++++++++++++++ > 1 file changed, 163 insertions(+) > > diff --git a/drivers/thermal/imx8mm_thermal.c > b/drivers/thermal/imx8mm_thermal.c > index e2c2673025a7a..da09c00ac663a 100644 > --- a/drivers/thermal/imx8mm_thermal.c > +++ b/drivers/thermal/imx8mm_thermal.c > @@ -10,6 +10,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -20,6 +21,22 @@ > #define TER 0x0 /* TMU enable */ > #define TPS 0x4 > #define TRITSR 0x20 /* TMU immediate temp */ > +/* TMU calibration data registers */ > +#define TASR 0x28 > +#define TASR_BUF_SLOPE_MASK GENMASK(19, 16) > +#define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */ > +#define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */ > +#define TCALIV(n) (0x30 + ((n) * 4)) > +#define TCALIV_EN BIT(31) > +#define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 > */ > +#define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */ > +#define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 > */ > +#define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 > */ > +#define TRIM 0x3c > +#define TRIM_BJT_CUR_MASK GENMASK(23, 20) > +#define TRIM_BGR_MASK GENMASK(31, 28) > +#define TRIM_VLSB_MASK GENMASK(15, 12) > +#define TRIM_EN_CH BIT(7) > > #define TER_ADC_PD BIT(30) > #define TER_EN BIT(31) > @@ -32,6 +49,25 @@ > #define SIGN_BIT BIT(7) > #define TEMP_VAL_MASK GENMASK(6, 0) > > +/* TMU OCOTP calibration data bitfields */ > +#define ANA0_EN BIT(25) > +#define ANA0_BUF_VREF_MASK GENMASK(24, 20) > +#define ANA0_BUF_SLOPE_MASK GENMASK(19, 16) > +#define ANA0_HR_MASK GENMASK(15, 8) > +#define ANA0_RT_MASK GENMASK(7, 0) > +#define TRIM2_VLSB_MASK GENMASK(23, 20) > +#define TRIM2_BGR_MASK GENMASK(19, 16) > +#define TRIM2_BJT_CUR_MASK GENMASK(15, 12) > +#define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8) > +#define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6) > +#define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28) > +#define TRIM3_TCA40_0_MASK GENMASK(27, 16) > +#define TRIM4_TCA40_1_MASK GENMASK(31, 20) > +#define TRIM4_TCA105_0_MASK GENMASK(19, 8) > +#define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0) > +#define TRIM5_TCA105_1_MASK GENMASK(23, 12) > +#define TRIM5_TCA25_1_MASK GENMASK(11, 0) > + > #define VER1_TEMP_LOW_LIMIT 10000 > #define VER2_TEMP_LOW_LIMIT -40000 > #define VER2_TEMP_HIGH_LIMIT 125000 > @@ -128,6 +164,129 @@ static void imx8mm_tmu_probe_sel_all(struct > imx8mm_tmu *tmu) > writel_relaxed(val, tmu->base + TPS); > } > > +static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev, > + struct imx8mm_tmu *tmu) > +{ > + struct device *dev = &pdev->dev; > + u32 ana0; > + int ret; > + > + ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0); > + if (ret) { > + dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n", > ret); > + return ret; > + } > + > + writel(FIELD_PREP(TASR_BUF_VREF_MASK, > + FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) | > + FIELD_PREP(TASR_BUF_SLOPE_MASK, > + FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)), > + tmu->base + TASR); > + > + writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, > ana0)) | > + FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0)) > | > + ((ana0 & ANA0_EN) ? TCALIV_EN : 0), > + tmu->base + TCALIV(0)); > + > + return 0; > +} > + > +static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev, > + struct imx8mm_tmu *tmu) > +{ > + struct device *dev = &pdev->dev; > + struct nvmem_cell *cell; > + u32 trim[4] = { 0 }; > + size_t len; > + void *buf; > + > + cell = nvmem_cell_get(dev, "calib"); > + if (IS_ERR(cell)) > + return PTR_ERR(cell); > + > + buf = nvmem_cell_read(cell, &len); > + nvmem_cell_put(cell); > + > + if (IS_ERR(buf)) > + return PTR_ERR(buf); > + > + memcpy(trim, buf, min(len, sizeof(trim))); > + kfree(buf); > + > + if (len != 16) { > + dev_err(dev, > + "OCOTP nvmem cell length is %ld, must be 16.\n", len); > + return -EINVAL; > + } > + > + /* Blank sample hardware */ > + if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) { > + /* Use a default 25C binary codes */ > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c), > + tmu->base + TCALIV(0)); > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c), > + tmu->base + TCALIV(1)); > + return 0; > + } > + > + writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK, > + FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) | > + FIELD_PREP(TASR_BUF_SLOPE_MASK, > + FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])), > + tmu->base + TASR); > + > + writel(FIELD_PREP(TRIM_BJT_CUR_MASK, > + FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) | > + FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK, > trim[0])) | > + FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK, > trim[0])) | > + TRIM_EN_CH, > + tmu->base + TRIM); > + > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, > + FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) | > + (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) << > 4)) | > + FIELD_PREP(TCALIV_SNSR105C_MASK, > + FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])), > + tmu->base + TCALIV(0)); > + > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, > + FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) | > + FIELD_PREP(TCALIV_SNSR105C_MASK, > + FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])), > + tmu->base + TCALIV(1)); > + > + writel(FIELD_PREP(TCALIV_SNSR25C_MASK, > + FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) | > + FIELD_PREP(TCALIV_SNSR105C_MASK, > + FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])), > + tmu->base + TCALIV(2)); > + > + return 0; > +} > + > +static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev, > + struct imx8mm_tmu *tmu) > +{ > + struct device *dev = &pdev->dev; > + > + /* > + * Lack of calibration data OCOTP reference is not considered > + * fatal to retain compatibility with old DTs. It is however > + * strongly recommended to update such old DTs to get correct > + * temperature compensation values for each SoC. > + */ > + if (!of_find_property(pdev->dev.of_node, "nvmem-cells", NULL)) { > + dev_warn(dev, > + "No OCOTP nvmem reference found, SoC-specific > calibration not loaded. Please update your DT.\n"); > + return 0; > + } > + > + if (tmu->socdata->version == TMU_VER1) > + return imx8mm_tmu_probe_set_calib_v1(pdev, tmu); > + > + return imx8mm_tmu_probe_set_calib_v2(pdev, tmu); } > + > static int imx8mm_tmu_probe(struct platform_device *pdev) { > const struct thermal_soc_data *data; > @@ -180,6 +339,10 @@ static int imx8mm_tmu_probe(struct platform_device > *pdev) > > platform_set_drvdata(pdev, tmu); > > + ret = imx8mm_tmu_probe_set_calib(pdev, tmu); > + if (ret) > + goto disable_clk; > + > /* enable all the probes for V2 TMU */ > if (tmu->socdata->version == TMU_VER2) > imx8mm_tmu_probe_sel_all(tmu); > -- > 2.35.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel