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Subject: Re: Memory Write Ordering Question
To: jim@intra.blueskylabs.com (James W. Lake)
Date: Thu, 2 Aug 2001 01:35:03 +0100 (BST)
Cc: linux-kernel@vger.kernel.org ("Linux Kernel Mailing List (E-mail)")
In-Reply-To: <no.id> from "James W. Lake" at Aug 01, 2001 11:44:10 AM
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From: Alan Cox <alan@lxorguk.ukuu.org.uk>
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> I'm wondering if anyone has any idea what exactly is causing this.  The
> readl is a so-so work around.  I'd like to figure out how to do it
> correctly.  Does anyone who knows more about Intel CPU's and write
> ordering and PCI have any ideas?

Its entirely a PCI issue. PCI writes are posted and may be deferred. However
a write cannot pass another write to the device, nor a read, so your read
is the real solution.

The full horror is in the PCI specs which you can get on CD nowdays fairly
sanely. Basically PCI is a message passing system disguised as a bus, treat
it as the former and you wont get too badly hurt