From mboxrd@z Thu Jan 1 00:00:00 1970 From: Philipp Tomsich Date: Sun, 06 Aug 2017 19:18:17 +0200 Subject: [U-Boot] [U-Boot, v4, 40/66] rockchip: clk: rk3368: do not change CPLL/GPLL before returning to BROM In-Reply-To: <1501706105-7490-41-git-send-email-philipp.tomsich@theobroma-systems.com> References: <1501706105-7490-41-git-send-email-philipp.tomsich@theobroma-systems.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de > The RK3368 has a somewhat temperamental BootROM (which I learned the > hard way) when it comes to reconfiguring the CPLL and GPLL (in fact, > experiments show that changing the GPLL broke things for me, while > changing the CPLL seems to be more benign). These should not be > modified by the SPL stage, if we intend to return to the BootROM for > chain booting the next stage. > > This commit changes the clock initialisation to not change CPLL/GPLL > before returning to the BootROM (i.e. in TPL). As it's safe to change > these settings if we no longer intend to return to U-Boot, we'll run > the full PLL setup a little later (i.e. in SPL). > > Signed-off-by: Philipp Tomsich > > Reviewed-by: Simon Glass > --- > > Changes in v4: None > Changes in v3: None > Changes in v2: None > > drivers/clk/rockchip/clk_rk3368.c | 18 +++++++++++++++++- > 1 file changed, 17 insertions(+), 1 deletion(-) > Applied to u-boot-rockchip, thanks!