From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.1 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C342C17443 for ; Sat, 9 Nov 2019 08:11:16 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 3913A21924 for ; Sat, 9 Nov 2019 08:11:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1573287076; bh=0l/xmVK8E54nV1NIINp5JylGsww5BvO6zdTFd0jE7to=; h=From:Date:Subject:To:Cc:Reply-to:List-ID:From; b=bFm1zWxJ0k4fpuzVcrrnYooIHJXTMrdMXZ7eGPnrNwhUZTIbF7fiZjjWdrfjip2mg zH3o458/gVe4v6Boa3euxpiB6yLqLAzDN0R2P74+3E11Eorz0VaOGfOEV57Q3NrmE6 +tD/3i30MiPS3ge90iwuWn3T3R2tbKz/Sj7pyDHw= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726282AbfKIILP (ORCPT ); Sat, 9 Nov 2019 03:11:15 -0500 Received: from www.linuxtv.org ([130.149.80.248]:46142 "EHLO www.linuxtv.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726260AbfKIILP (ORCPT ); Sat, 9 Nov 2019 03:11:15 -0500 Received: from mchehab by www.linuxtv.org with local (Exim 4.84_2) (envelope-from ) id 1iTLpu-00030k-G4; Sat, 09 Nov 2019 08:11:10 +0000 From: Mauro Carvalho Chehab Date: Sat, 09 Nov 2019 08:06:27 +0000 Subject: [git:media_tree/master] media: hantro: Fix picture order count table enable To: linuxtv-commits@linuxtv.org Cc: Jonas Karlman , Ezequiel Garcia , Hans Verkuil , Boris Brezillon , Francois Buergisser , stable@vger.kernel.org Mail-followup-to: linux-media@vger.kernel.org Forward-to: linux-media@vger.kernel.org Reply-to: linux-media@vger.kernel.org Message-Id: Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org This is an automatic generated email to let you know that the following patch were queued: Subject: media: hantro: Fix picture order count table enable Author: Francois Buergisser Date: Tue Oct 29 02:24:48 2019 +0100 The picture order count table only makes sense for profiles higher than Baseline. This is confirmed by the H.264 specification (See 8.2.1 Decoding process for picture order count), which clarifies how POC are used for features not present in Baseline. """ Picture order counts are used to determine initial picture orderings for reference pictures in the decoding of B slices, to represent picture order differences between frames or fields for motion vector derivation in temporal direct mode, for implicit mode weighted prediction in B slices, and for decoder conformance checking. """ As a side note, this change matches various vendors downstream codebases, including ChromiumOS and IMX VPU libraries. Fixes: dea0a82f3d22 ("media: hantro: Add support for H264 decoding on G1") Signed-off-by: Francois Buergisser Signed-off-by: Ezequiel Garcia Signed-off-by: Jonas Karlman Reviewed-by: Boris Brezillon Tested-by: Boris Brezillon Cc: # for v5.4 and up Signed-off-by: Hans Verkuil Signed-off-by: Mauro Carvalho Chehab drivers/staging/media/hantro/hantro_g1_h264_dec.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) --- diff --git a/drivers/staging/media/hantro/hantro_g1_h264_dec.c b/drivers/staging/media/hantro/hantro_g1_h264_dec.c index a1cb18680200..70a6b5b26477 100644 --- a/drivers/staging/media/hantro/hantro_g1_h264_dec.c +++ b/drivers/staging/media/hantro/hantro_g1_h264_dec.c @@ -34,9 +34,11 @@ static void set_params(struct hantro_ctx *ctx) reg = G1_REG_DEC_CTRL0_DEC_AXI_WR_ID(0x0); if (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD) reg |= G1_REG_DEC_CTRL0_SEQ_MBAFF_E; - reg |= G1_REG_DEC_CTRL0_PICORD_COUNT_E; - if (sps->profile_idc > 66 && dec_param->nal_ref_idc) - reg |= G1_REG_DEC_CTRL0_WRITE_MVS_E; + if (sps->profile_idc > 66) { + reg |= G1_REG_DEC_CTRL0_PICORD_COUNT_E; + if (dec_param->nal_ref_idc) + reg |= G1_REG_DEC_CTRL0_WRITE_MVS_E; + } if (!(sps->flags & V4L2_H264_SPS_FLAG_FRAME_MBS_ONLY) && (sps->flags & V4L2_H264_SPS_FLAG_MB_ADAPTIVE_FRAME_FIELD ||