diff for duplicates of <E7C9878FBA1C6D42A1CA3F62AEB6945F823E2E20@BGSMSX104.gar.corp.intel.com>

diff --git a/a/1.txt b/N1/1.txt
index 1cc6b15..6f7bf3f 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,214 +1,348 @@
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\ No newline at end of file
+
+
+> -----Original Message-----
+> From: Mun, Gwan-gyeong <gwan-gyeong.mun@intel.com>
+> Sent: Sunday, February 9, 2020 9:05 AM
+> To: Shankar, Uma <uma.shankar@intel.com>; intel-gfx@lists.freedesktop.org
+> Cc: dri-devel@lists.freedesktop.org; linux-fbdev@vger.kernel.org
+> Subject: Re: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data
+> Packet)
+> 
+> On Wed, 2020-02-05 at 21:39 +0530, Shankar, Uma wrote:
+> > > -----Original Message-----
+> > > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf
+> > > Of Gwan- gyeong Mun
+> > > Sent: Tuesday, February 4, 2020 4:50 AM
+> > > To: intel-gfx@lists.freedesktop.org
+> > > Cc: linux-fbdev@vger.kernel.org; dri-devel@lists.freedesktop.org
+> > > Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs
+> > > (Secondary Data
+> > > Packet)
+> >
+> > Drop things in (), not needed.
+> >
+> > > It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe
+> > > SDP.
+> > > In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack()
+> > > function.
+> > > It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and
+> > > [Table 2-117: VSC SDP Payload for DB16 through DB18]
+> > >
+> > > In order to pack DP HDR Metadata Infoframe SDP, it adds
+> > > intel_dp_hdr_metadata_infoframe_sdp_pack() function.
+> > > And it follows DP 1.4a spec.
+> > > ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126:
+> > > INFOFRAME
+> > > SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec.
+> > > [Table-42 Dynamic Range and Mastering InfoFrame].
+> > >
+> > > A machanism and a naming rule of intel_dp_set_infoframes() function
+> > > references
+> >
+> > Typo in mechanism.
+> >
+> > > intel_encoder->set_infoframes() of intel_hdmi.c .
+> > > VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats
+> > > cases.
+> > > Because PSR routine has its own routine of writing a VSC SDP, when
+> > > the PSR is enabled, intel_dp_set_infoframes() does not write a VSC
+> > > SDP.
+> > >
+> > > v3:
+> > >   - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They
+> > > will be
+> > >     used for HDMI), when intel_dp_set_infoframes() function will be
+> > > called.
+> > >   - Replace a structure name to drm_dp_vsc_sdp from
+> > > intel_dp_vsc_sdp.
+> > >
+> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
+> > > ---
+> > >  drivers/gpu/drm/i915/display/intel_dp.c | 194
+> > > ++++++++++++++++++++++++
+> > >  drivers/gpu/drm/i915/display/intel_dp.h |   3 +
+> > >  2 files changed, 197 insertions(+)
+> > >
+> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
+> > > b/drivers/gpu/drm/i915/display/intel_dp.c
+> > > index b265b5c599f2..dd7e5588001e 100644
+> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
+> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
+> > > @@ -4731,6 +4731,200 @@ intel_dp_needs_vsc_sdp(const struct
+> > > intel_crtc_state *crtc_state,
+> > >  	return false;
+> > >  }
+> > >
+> > > +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp
+> > > *vsc,
+> > > +				     struct dp_sdp *sdp, size_t size) {
+> > > +	size_t length = sizeof(struct dp_sdp);
+> > > +
+> > > +	if (size < length)
+> > > +		return -ENOSPC;
+> > > +
+> > > +	memset(sdp, 0, size);
+> > > +
+> > > +	/*
+> > > +	 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119
+> > > +	 * VSC SDP Header Bytes
+> > > +	 */
+> > > +	sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */
+> > > +	sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet
+> > > Type */
+> > > +	sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */
+> > > +	sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data
+> > > Bytes */
+> > > +
+> > > +	/* VSC SDP Payload for DB16 through DB18 */
+> > > +	/* Pixel Encoding and Colorimetry Formats  */
+> > > +	sdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */
+> > > +	sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */
+> > > +
+> > > +	switch (vsc->bpc) {
+> > > +	case 8:
+> > > +		sdp->db[17] = 0x1; /* DB17[3:0] */
+> > > +		break;
+> > > +	case 10:
+> > > +		sdp->db[17] = 0x2;
+> > > +		break;
+> > > +	case 12:
+> > > +		sdp->db[17] = 0x3;
+> > > +		break;
+> > > +	case 16:
+> > > +		sdp->db[17] = 0x4;
+> > > +		break;
+> > > +	default:
+> > > +		MISSING_CASE(vsc->bpc);
+> >
+> > 6bpc is not handled here, add that as well.
+> >
+> Yes, I missed 6bpc case, I'll update it.
+> > > +		break;
+> > > +	}
+> > > +	/* Dynamic Range and Component Bit Depth */
+> > > +	if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)
+> > > +		sdp->db[17] |= 0x80;  /* DB17[7] */
+> > > +
+> > > +	/* Content Type */
+> > > +	sdp->db[18] = vsc->content_type & 0x7;
+> > > +
+> > > +	return length;
+> > > +}
+> > > +
+> > > +static ssize_t
+> > > +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct
+> > > hdmi_drm_infoframe
+> > > *drm_infoframe,
+> > > +					 struct dp_sdp *sdp,
+> > > +					 size_t size)
+> > > +{
+> > > +	size_t length = sizeof(struct dp_sdp);
+> > > +	const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +
+> > > HDMI_DRM_INFOFRAME_SIZE;
+> > > +	unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +
+> > > HDMI_DRM_INFOFRAME_SIZE];
+> > > +	ssize_t len;
+> > > +
+> > > +	if (size < length)
+> > > +		return -ENOSPC;
+> > > +
+> > > +	memset(sdp, 0, size);
+> > > +
+> > > +	len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf,
+> > > sizeof(buf));
+> > > +	if (len < 0) {
+> > > +		DRM_DEBUG_KMS("buffer size is smaller than hdr metadata
+> > > infoframe\n");
+> > > +		return -ENOSPC;
+> > > +	}
+> > > +
+> > > +	if (len != infoframe_size) {
+> > > +		DRM_DEBUG_KMS("wrong static hdr metadata size\n");
+> > > +		return -ENOSPC;
+> > > +	}
+> > > +
+> > > +	/*
+> > > +	 * Set up the infoframe sdp packet for HDR static metadata.
+> > > +	 * Prepare VSC Header for SU as per DP 1.4a spec,
+> > > +	 * Table 2-100 and Table 2-101
+> > > +	 */
+> > > +
+> > > +	/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */
+> > > +	sdp->sdp_header.HB0 = 0;
+> > > +	/*
+> > > +	 * Packet Type 80h + Non-audio INFOFRAME Type value
+> > > +	 * HDMI_INFOFRAME_TYPE_DRM: 0x87
+> > > +	 * - 80h + Non-audio INFOFRAME Type value
+> > > +	 * - InfoFrame Type: 0x07
+> > > +	 *    [CTA-861-G Table-42 Dynamic Range and Mastering
+> > > InfoFrame]
+> > > +	 */
+> > > +	sdp->sdp_header.HB1 = drm_infoframe->type;
+> > > +	/*
+> > > +	 * Least Significant Eight Bits of (Data Byte Count – 1)
+> > > +	 * infoframe_size - 1
+> > > +	 */
+> > > +	sdp->sdp_header.HB2 = 0x1D;
+> > > +	/* INFOFRAME SDP Version Number */
+> > > +	sdp->sdp_header.HB3 = (0x13 << 2);
+> > > +	/* CTA Header Byte 2 (INFOFRAME Version Number) */
+> > > +	sdp->db[0] = drm_infoframe->version;
+> > > +	/* CTA Header Byte 3 (Length of INFOFRAME):
+> > > HDMI_DRM_INFOFRAME_SIZE */
+> > > +	sdp->db[1] = drm_infoframe->length;
+> > > +	/*
+> > > +	 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after
+> >
+> > Comment Looks incomplete.
+> >
+> I missed some comments, I'll update it.
+> > > +	 */
+> > > +	BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);
+> > > +	memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],
+> > > +	       HDMI_DRM_INFOFRAME_SIZE);
+> > > +
+> > > +	/*
+> > > +	 * Size of DP infoframe sdp packet for HDR static metadata is
+> > > consist of
+> >
+> > Drop "is"
+> >
+> Includes this, I'll polish polish commit message and comments.
+> 
+> > > +	 * - DP SDP Header(struct dp_sdp_header): 4 bytes
+> > > +	 * - Two Data Blocks: 2 bytes
+> > > +	 *    CTA Header Byte2 (INFOFRAME Version Number)
+> > > +	 *    CTA Header Byte3 (Length of INFOFRAME)
+> > > +	 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes
+> > > +	 *
+> > > +	 * Prior to GEN11's GMP register size is identical to DP HDR
+> > > static metadata
+> > > +	 * infoframe size. But GEN11+ has larger than that size,
+> > > write_infoframe
+> > > +	 * will pad rest of the size.
+> > > +	 */
+> > > +	return sizeof(struct dp_sdp_header) + 2 +
+> > > HDMI_DRM_INFOFRAME_SIZE; }
+> > > +
+> > > +static void intel_write_dp_sdp(struct intel_encoder *encoder,
+> > > +			       const struct intel_crtc_state
+> > > *crtc_state,
+> > > +			       unsigned int type)
+> > > +{
+> > > +	struct intel_digital_port *intel_dig_port =
+> > > enc_to_dig_port(encoder);
+> > > +	struct dp_sdp sdp = {};
+> > > +	ssize_t len;
+> > > +
+> > > +	if ((crtc_state->infoframes.enable &
+> > > +	     intel_hdmi_infoframe_enable(type)) == 0)
+> > > +		return;
+> > > +
+> > > +	switch (type) {
+> > > +	case DP_SDP_VSC:
+> > > +		len = intel_dp_vsc_sdp_pack(&crtc_state-
+> > > >infoframes.vsc, &sdp,
+> > > +					    sizeof(sdp));
+> > > +		break;
+> > > +	case HDMI_PACKET_TYPE_GAMUT_METADATA:
+> > > +		len =
+> > > intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state-
+> > > > infoframes.drm.drm,
+> > > +							       &sdp,
+> > > sizeof(sdp));
+> > > +		break;
+> > > +	default:
+> > > +		MISSING_CASE(type);
+> > > +		break;
+> > > +	}
+> > > +
+> > > +	if (WARN_ON(len < 0))
+> > > +		return;
+> > > +
+> > > +	intel_dig_port->write_infoframe(encoder, crtc_state, type,
+> > > &sdp, len);
+> > > +}
+> > > +
+> > > +void intel_dp_set_infoframes(struct intel_encoder *encoder,
+> > > +			     bool enable,
+> > > +			     const struct intel_crtc_state *crtc_state,
+> > > +			     const struct drm_connector_state
+> > > *conn_state) {
+> > > +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+> > > +	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+> > > +	i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state-
+> > > >cpu_transcoder);
+> > > +	u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |
+> > > VIDEO_DIP_ENABLE_GCP_HSW |
+> > > +			 VIDEO_DIP_ENABLE_VS_HSW |
+> > > VIDEO_DIP_ENABLE_GMP_HSW |
+> > > +			 VIDEO_DIP_ENABLE_SPD_HSW |
+> > > VIDEO_DIP_ENABLE_DRM_GLK;
+> > > +	u32 val = I915_READ(reg);
+> > > +
+> > > +	/* TODO: Add DSC case (DIP_ENABLE_PPS) */
+> > > +	/* When PSR is enabled, this routine doesn't disable VSC DIP */
+> > > +	if (intel_psr_enabled(intel_dp))
+> > > +		val &= ~dip_enable;
+> > > +	else
+> > > +		val &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);
+> >
+> > dip_enable has VIDEO_DIP_ENABLE_VSC_HSW already in it. Please fix
+> > this.
+> >
+> Declaring of dip_enable does not include VIDEO_DIP_ENABLE_VSC_HSW.
+> therefore we need it here to disable VSC SDP DIP.
+
+Oh ok, Took VS for VSC. Scratch my earlier comment, change is correct.
+
+> > > +
+> > > +	if (!enable) {
+> > > +		I915_WRITE(reg, val);
+> > > +		POSTING_READ(reg);
+> > > +		return;
+> > > +	}
+> > > +
+> > > +	I915_WRITE(reg, val);
+> > > +	POSTING_READ(reg);
+> > > +
+> > > +	/* When PSR is enabled, VSC SDP is handled by PSR routine */
+> > > +	if (!intel_psr_enabled(intel_dp))
+> > > +		intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);
+> > > +
+> > > +	intel_write_dp_sdp(encoder, crtc_state,
+> > > +HDMI_PACKET_TYPE_GAMUT_METADATA); }
+> > > +
+> > >  static void
+> > >  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,
+> > >  		       const struct intel_crtc_state *crtc_state, diff --git
+> > > a/drivers/gpu/drm/i915/display/intel_dp.h
+> > > b/drivers/gpu/drm/i915/display/intel_dp.h
+> > > index 3da166054788..0dc09a463ee1 100644
+> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
+> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
+> > > @@ -116,6 +116,9 @@ void intel_dp_vsc_enable(struct intel_dp
+> > > *intel_dp,  void intel_dp_hdr_metadata_enable(struct intel_dp
+> > > *intel_dp,
+> > >  				  const struct intel_crtc_state *crtc_state,
+> > >  				  const struct drm_connector_state *conn_state);
+> > > +void intel_dp_set_infoframes(struct intel_encoder *encoder, bool
+> > > enable,
+> > > +			     const struct intel_crtc_state *crtc_state,
+> > > +			     const struct drm_connector_state
+> > > *conn_state);
+> > >  bool intel_digital_port_connected(struct intel_encoder *encoder);
+> > >
+> > >  static inline unsigned int intel_dp_unused_lane_mask(int
+> > > lane_count)
+> > > --
+> > > 2.24.1
+> > >
+> > > _______________________________________________
+> > > dri-devel mailing list
+> > > dri-devel@lists.freedesktop.org
+> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel
+_______________________________________________
+dri-devel mailing list
+dri-devel@lists.freedesktop.org
+https://lists.freedesktop.org/mailman/listinfo/dri-devel
\ No newline at end of file
diff --git a/a/content_digest b/N1/content_digest
index cba0622..c46e2a0 100644
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+++ b/N1/content_digest
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+  "\n",
+  "\n",
+  "> -----Original Message-----\n",
+  "> From: Mun, Gwan-gyeong <gwan-gyeong.mun\@intel.com>\n",
+  "> Sent: Sunday, February 9, 2020 9:05 AM\n",
+  "> To: Shankar, Uma <uma.shankar\@intel.com>; intel-gfx\@lists.freedesktop.org\n",
+  "> Cc: dri-devel\@lists.freedesktop.org; linux-fbdev\@vger.kernel.org\n",
+  "> Subject: Re: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs (Secondary Data\n",
+  "> Packet)\n",
+  "> \n",
+  "> On Wed, 2020-02-05 at 21:39 +0530, Shankar, Uma wrote:\n",
+  "> > > -----Original Message-----\n",
+  "> > > From: dri-devel <dri-devel-bounces\@lists.freedesktop.org> On Behalf\n",
+  "> > > Of Gwan- gyeong Mun\n",
+  "> > > Sent: Tuesday, February 4, 2020 4:50 AM\n",
+  "> > > To: intel-gfx\@lists.freedesktop.org\n",
+  "> > > Cc: linux-fbdev\@vger.kernel.org; dri-devel\@lists.freedesktop.org\n",
+  "> > > Subject: [PATCH v3 04/17] drm/i915/dp: Add writing of DP SDPs\n",
+  "> > > (Secondary Data\n",
+  "> > > Packet)\n",
+  "> >\n",
+  "> > Drop things in (), not needed.\n",
+  "> >\n",
+  "> > > It adds routines that write DP VSC SDP and DP HDR Metadata Infoframe\n",
+  "> > > SDP.\n",
+  "> > > In order to pack DP VSC SDP, it adds intel_dp_vsc_sdp_pack()\n",
+  "> > > function.\n",
+  "> > > It follows DP 1.4a spec. [Table 2-116: VSC SDP Header Bytes] and\n",
+  "> > > [Table 2-117: VSC SDP Payload for DB16 through DB18]\n",
+  "> > >\n",
+  "> > > In order to pack DP HDR Metadata Infoframe SDP, it adds\n",
+  "> > > intel_dp_hdr_metadata_infoframe_sdp_pack() function.\n",
+  "> > > And it follows DP 1.4a spec.\n",
+  "> > > ([Table 2-125: INFOFRAME SDP v1.2 Header Bytes] and [Table 2-126:\n",
+  "> > > INFOFRAME\n",
+  "> > > SDP v1.2 Payload Data Bytes - DB0 through DB31]) and CTA-861-G spec.\n",
+  "> > > [Table-42 Dynamic Range and Mastering InfoFrame].\n",
+  "> > >\n",
+  "> > > A machanism and a naming rule of intel_dp_set_infoframes() function\n",
+  "> > > references\n",
+  "> >\n",
+  "> > Typo in mechanism.\n",
+  "> >\n",
+  "> > > intel_encoder->set_infoframes() of intel_hdmi.c .\n",
+  "> > > VSC SDP is used for PSR and Pixel Encoding and Colorimetry Formats\n",
+  "> > > cases.\n",
+  "> > > Because PSR routine has its own routine of writing a VSC SDP, when\n",
+  "> > > the PSR is enabled, intel_dp_set_infoframes() does not write a VSC\n",
+  "> > > SDP.\n",
+  "> > >\n",
+  "> > > v3:\n",
+  "> > >   - Explicitly disable unused DIPs (AVI, GCP, VS, SPD, DRM. They\n",
+  "> > > will be\n",
+  "> > >     used for HDMI), when intel_dp_set_infoframes() function will be\n",
+  "> > > called.\n",
+  "> > >   - Replace a structure name to drm_dp_vsc_sdp from\n",
+  "> > > intel_dp_vsc_sdp.\n",
+  "> > >\n",
+  "> > > Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun\@intel.com>\n",
+  "> > > ---\n",
+  "> > >  drivers/gpu/drm/i915/display/intel_dp.c | 194\n",
+  "> > > ++++++++++++++++++++++++\n",
+  "> > >  drivers/gpu/drm/i915/display/intel_dp.h |   3 +\n",
+  "> > >  2 files changed, 197 insertions(+)\n",
+  "> > >\n",
+  "> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c\n",
+  "> > > b/drivers/gpu/drm/i915/display/intel_dp.c\n",
+  "> > > index b265b5c599f2..dd7e5588001e 100644\n",
+  "> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c\n",
+  "> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c\n",
+  "> > > \@\@ -4731,6 +4731,200 \@\@ intel_dp_needs_vsc_sdp(const struct\n",
+  "> > > intel_crtc_state *crtc_state,\n",
+  "> > >  \treturn false;\n",
+  "> > >  }\n",
+  "> > >\n",
+  "> > > +static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp\n",
+  "> > > *vsc,\n",
+  "> > > +\t\t\t\t     struct dp_sdp *sdp, size_t size) {\n",
+  "> > > +\tsize_t length = sizeof(struct dp_sdp);\n",
+  "> > > +\n",
+  "> > > +\tif (size < length)\n",
+  "> > > +\t\treturn -ENOSPC;\n",
+  "> > > +\n",
+  "> > > +\tmemset(sdp, 0, size);\n",
+  "> > > +\n",
+  "> > > +\t/*\n",
+  "> > > +\t * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119\n",
+  "> > > +\t * VSC SDP Header Bytes\n",
+  "> > > +\t */\n",
+  "> > > +\tsdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */\n",
+  "> > > +\tsdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet\n",
+  "> > > Type */\n",
+  "> > > +\tsdp->sdp_header.HB2 = vsc->revision; /* Revision Number */\n",
+  "> > > +\tsdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data\n",
+  "> > > Bytes */\n",
+  "> > > +\n",
+  "> > > +\t/* VSC SDP Payload for DB16 through DB18 */\n",
+  "> > > +\t/* Pixel Encoding and Colorimetry Formats  */\n",
+  "> > > +\tsdp->db[16] = (vsc->colorspace & 0xf) << 4; /* DB16[7:4] */\n",
+  "> > > +\tsdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */\n",
+  "> > > +\n",
+  "> > > +\tswitch (vsc->bpc) {\n",
+  "> > > +\tcase 8:\n",
+  "> > > +\t\tsdp->db[17] = 0x1; /* DB17[3:0] */\n",
+  "> > > +\t\tbreak;\n",
+  "> > > +\tcase 10:\n",
+  "> > > +\t\tsdp->db[17] = 0x2;\n",
+  "> > > +\t\tbreak;\n",
+  "> > > +\tcase 12:\n",
+  "> > > +\t\tsdp->db[17] = 0x3;\n",
+  "> > > +\t\tbreak;\n",
+  "> > > +\tcase 16:\n",
+  "> > > +\t\tsdp->db[17] = 0x4;\n",
+  "> > > +\t\tbreak;\n",
+  "> > > +\tdefault:\n",
+  "> > > +\t\tMISSING_CASE(vsc->bpc);\n",
+  "> >\n",
+  "> > 6bpc is not handled here, add that as well.\n",
+  "> >\n",
+  "> Yes, I missed 6bpc case, I'll update it.\n",
+  "> > > +\t\tbreak;\n",
+  "> > > +\t}\n",
+  "> > > +\t/* Dynamic Range and Component Bit Depth */\n",
+  "> > > +\tif (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA)\n",
+  "> > > +\t\tsdp->db[17] |= 0x80;  /* DB17[7] */\n",
+  "> > > +\n",
+  "> > > +\t/* Content Type */\n",
+  "> > > +\tsdp->db[18] = vsc->content_type & 0x7;\n",
+  "> > > +\n",
+  "> > > +\treturn length;\n",
+  "> > > +}\n",
+  "> > > +\n",
+  "> > > +static ssize_t\n",
+  "> > > +intel_dp_hdr_metadata_infoframe_sdp_pack(const struct\n",
+  "> > > hdmi_drm_infoframe\n",
+  "> > > *drm_infoframe,\n",
+  "> > > +\t\t\t\t\t struct dp_sdp *sdp,\n",
+  "> > > +\t\t\t\t\t size_t size)\n",
+  "> > > +{\n",
+  "> > > +\tsize_t length = sizeof(struct dp_sdp);\n",
+  "> > > +\tconst int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE +\n",
+  "> > > HDMI_DRM_INFOFRAME_SIZE;\n",
+  "> > > +\tunsigned char buf[HDMI_INFOFRAME_HEADER_SIZE +\n",
+  "> > > HDMI_DRM_INFOFRAME_SIZE];\n",
+  "> > > +\tssize_t len;\n",
+  "> > > +\n",
+  "> > > +\tif (size < length)\n",
+  "> > > +\t\treturn -ENOSPC;\n",
+  "> > > +\n",
+  "> > > +\tmemset(sdp, 0, size);\n",
+  "> > > +\n",
+  "> > > +\tlen = hdmi_drm_infoframe_pack_only(drm_infoframe, buf,\n",
+  "> > > sizeof(buf));\n",
+  "> > > +\tif (len < 0) {\n",
+  "> > > +\t\tDRM_DEBUG_KMS(\"buffer size is smaller than hdr metadata\n",
+  "> > > infoframe\\n\");\n",
+  "> > > +\t\treturn -ENOSPC;\n",
+  "> > > +\t}\n",
+  "> > > +\n",
+  "> > > +\tif (len != infoframe_size) {\n",
+  "> > > +\t\tDRM_DEBUG_KMS(\"wrong static hdr metadata size\\n\");\n",
+  "> > > +\t\treturn -ENOSPC;\n",
+  "> > > +\t}\n",
+  "> > > +\n",
+  "> > > +\t/*\n",
+  "> > > +\t * Set up the infoframe sdp packet for HDR static metadata.\n",
+  "> > > +\t * Prepare VSC Header for SU as per DP 1.4a spec,\n",
+  "> > > +\t * Table 2-100 and Table 2-101\n",
+  "> > > +\t */\n",
+  "> > > +\n",
+  "> > > +\t/* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */\n",
+  "> > > +\tsdp->sdp_header.HB0 = 0;\n",
+  "> > > +\t/*\n",
+  "> > > +\t * Packet Type 80h + Non-audio INFOFRAME Type value\n",
+  "> > > +\t * HDMI_INFOFRAME_TYPE_DRM: 0x87\n",
+  "> > > +\t * - 80h + Non-audio INFOFRAME Type value\n",
+  "> > > +\t * - InfoFrame Type: 0x07\n",
+  "> > > +\t *    [CTA-861-G Table-42 Dynamic Range and Mastering\n",
+  "> > > InfoFrame]\n",
+  "> > > +\t */\n",
+  "> > > +\tsdp->sdp_header.HB1 = drm_infoframe->type;\n",
+  "> > > +\t/*\n",
+  "> > > +\t * Least Significant Eight Bits of (Data Byte Count \342\200\223 1)\n",
+  "> > > +\t * infoframe_size - 1\n",
+  "> > > +\t */\n",
+  "> > > +\tsdp->sdp_header.HB2 = 0x1D;\n",
+  "> > > +\t/* INFOFRAME SDP Version Number */\n",
+  "> > > +\tsdp->sdp_header.HB3 = (0x13 << 2);\n",
+  "> > > +\t/* CTA Header Byte 2 (INFOFRAME Version Number) */\n",
+  "> > > +\tsdp->db[0] = drm_infoframe->version;\n",
+  "> > > +\t/* CTA Header Byte 3 (Length of INFOFRAME):\n",
+  "> > > HDMI_DRM_INFOFRAME_SIZE */\n",
+  "> > > +\tsdp->db[1] = drm_infoframe->length;\n",
+  "> > > +\t/*\n",
+  "> > > +\t * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after\n",
+  "> >\n",
+  "> > Comment Looks incomplete.\n",
+  "> >\n",
+  "> I missed some comments, I'll update it.\n",
+  "> > > +\t */\n",
+  "> > > +\tBUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2);\n",
+  "> > > +\tmemcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE],\n",
+  "> > > +\t       HDMI_DRM_INFOFRAME_SIZE);\n",
+  "> > > +\n",
+  "> > > +\t/*\n",
+  "> > > +\t * Size of DP infoframe sdp packet for HDR static metadata is\n",
+  "> > > consist of\n",
+  "> >\n",
+  "> > Drop \"is\"\n",
+  "> >\n",
+  "> Includes this, I'll polish polish commit message and comments.\n",
+  "> \n",
+  "> > > +\t * - DP SDP Header(struct dp_sdp_header): 4 bytes\n",
+  "> > > +\t * - Two Data Blocks: 2 bytes\n",
+  "> > > +\t *    CTA Header Byte2 (INFOFRAME Version Number)\n",
+  "> > > +\t *    CTA Header Byte3 (Length of INFOFRAME)\n",
+  "> > > +\t * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes\n",
+  "> > > +\t *\n",
+  "> > > +\t * Prior to GEN11's GMP register size is identical to DP HDR\n",
+  "> > > static metadata\n",
+  "> > > +\t * infoframe size. But GEN11+ has larger than that size,\n",
+  "> > > write_infoframe\n",
+  "> > > +\t * will pad rest of the size.\n",
+  "> > > +\t */\n",
+  "> > > +\treturn sizeof(struct dp_sdp_header) + 2 +\n",
+  "> > > HDMI_DRM_INFOFRAME_SIZE; }\n",
+  "> > > +\n",
+  "> > > +static void intel_write_dp_sdp(struct intel_encoder *encoder,\n",
+  "> > > +\t\t\t       const struct intel_crtc_state\n",
+  "> > > *crtc_state,\n",
+  "> > > +\t\t\t       unsigned int type)\n",
+  "> > > +{\n",
+  "> > > +\tstruct intel_digital_port *intel_dig_port =\n",
+  "> > > enc_to_dig_port(encoder);\n",
+  "> > > +\tstruct dp_sdp sdp = {};\n",
+  "> > > +\tssize_t len;\n",
+  "> > > +\n",
+  "> > > +\tif ((crtc_state->infoframes.enable &\n",
+  "> > > +\t     intel_hdmi_infoframe_enable(type)) == 0)\n",
+  "> > > +\t\treturn;\n",
+  "> > > +\n",
+  "> > > +\tswitch (type) {\n",
+  "> > > +\tcase DP_SDP_VSC:\n",
+  "> > > +\t\tlen = intel_dp_vsc_sdp_pack(&crtc_state-\n",
+  "> > > >infoframes.vsc, &sdp,\n",
+  "> > > +\t\t\t\t\t    sizeof(sdp));\n",
+  "> > > +\t\tbreak;\n",
+  "> > > +\tcase HDMI_PACKET_TYPE_GAMUT_METADATA:\n",
+  "> > > +\t\tlen =\n",
+  "> > > intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state-\n",
+  "> > > > infoframes.drm.drm,\n",
+  "> > > +\t\t\t\t\t\t\t       &sdp,\n",
+  "> > > sizeof(sdp));\n",
+  "> > > +\t\tbreak;\n",
+  "> > > +\tdefault:\n",
+  "> > > +\t\tMISSING_CASE(type);\n",
+  "> > > +\t\tbreak;\n",
+  "> > > +\t}\n",
+  "> > > +\n",
+  "> > > +\tif (WARN_ON(len < 0))\n",
+  "> > > +\t\treturn;\n",
+  "> > > +\n",
+  "> > > +\tintel_dig_port->write_infoframe(encoder, crtc_state, type,\n",
+  "> > > &sdp, len);\n",
+  "> > > +}\n",
+  "> > > +\n",
+  "> > > +void intel_dp_set_infoframes(struct intel_encoder *encoder,\n",
+  "> > > +\t\t\t     bool enable,\n",
+  "> > > +\t\t\t     const struct intel_crtc_state *crtc_state,\n",
+  "> > > +\t\t\t     const struct drm_connector_state\n",
+  "> > > *conn_state) {\n",
+  "> > > +\tstruct drm_i915_private *dev_priv = to_i915(encoder->base.dev);\n",
+  "> > > +\tstruct intel_dp *intel_dp = enc_to_intel_dp(encoder);\n",
+  "> > > +\ti915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state-\n",
+  "> > > >cpu_transcoder);\n",
+  "> > > +\tu32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW |\n",
+  "> > > VIDEO_DIP_ENABLE_GCP_HSW |\n",
+  "> > > +\t\t\t VIDEO_DIP_ENABLE_VS_HSW |\n",
+  "> > > VIDEO_DIP_ENABLE_GMP_HSW |\n",
+  "> > > +\t\t\t VIDEO_DIP_ENABLE_SPD_HSW |\n",
+  "> > > VIDEO_DIP_ENABLE_DRM_GLK;\n",
+  "> > > +\tu32 val = I915_READ(reg);\n",
+  "> > > +\n",
+  "> > > +\t/* TODO: Add DSC case (DIP_ENABLE_PPS) */\n",
+  "> > > +\t/* When PSR is enabled, this routine doesn't disable VSC DIP */\n",
+  "> > > +\tif (intel_psr_enabled(intel_dp))\n",
+  "> > > +\t\tval &= ~dip_enable;\n",
+  "> > > +\telse\n",
+  "> > > +\t\tval &= ~(dip_enable | VIDEO_DIP_ENABLE_VSC_HSW);\n",
+  "> >\n",
+  "> > dip_enable has VIDEO_DIP_ENABLE_VSC_HSW already in it. Please fix\n",
+  "> > this.\n",
+  "> >\n",
+  "> Declaring of dip_enable does not include VIDEO_DIP_ENABLE_VSC_HSW.\n",
+  "> therefore we need it here to disable VSC SDP DIP.\n",
+  "\n",
+  "Oh ok, Took VS for VSC. Scratch my earlier comment, change is correct.\n",
+  "\n",
+  "> > > +\n",
+  "> > > +\tif (!enable) {\n",
+  "> > > +\t\tI915_WRITE(reg, val);\n",
+  "> > > +\t\tPOSTING_READ(reg);\n",
+  "> > > +\t\treturn;\n",
+  "> > > +\t}\n",
+  "> > > +\n",
+  "> > > +\tI915_WRITE(reg, val);\n",
+  "> > > +\tPOSTING_READ(reg);\n",
+  "> > > +\n",
+  "> > > +\t/* When PSR is enabled, VSC SDP is handled by PSR routine */\n",
+  "> > > +\tif (!intel_psr_enabled(intel_dp))\n",
+  "> > > +\t\tintel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC);\n",
+  "> > > +\n",
+  "> > > +\tintel_write_dp_sdp(encoder, crtc_state,\n",
+  "> > > +HDMI_PACKET_TYPE_GAMUT_METADATA); }\n",
+  "> > > +\n",
+  "> > >  static void\n",
+  "> > >  intel_dp_setup_vsc_sdp(struct intel_dp *intel_dp,\n",
+  "> > >  \t\t       const struct intel_crtc_state *crtc_state, diff --git\n",
+  "> > > a/drivers/gpu/drm/i915/display/intel_dp.h\n",
+  "> > > b/drivers/gpu/drm/i915/display/intel_dp.h\n",
+  "> > > index 3da166054788..0dc09a463ee1 100644\n",
+  "> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h\n",
+  "> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h\n",
+  "> > > \@\@ -116,6 +116,9 \@\@ void intel_dp_vsc_enable(struct intel_dp\n",
+  "> > > *intel_dp,  void intel_dp_hdr_metadata_enable(struct intel_dp\n",
+  "> > > *intel_dp,\n",
+  "> > >  \t\t\t\t  const struct intel_crtc_state *crtc_state,\n",
+  "> > >  \t\t\t\t  const struct drm_connector_state *conn_state);\n",
+  "> > > +void intel_dp_set_infoframes(struct intel_encoder *encoder, bool\n",
+  "> > > enable,\n",
+  "> > > +\t\t\t     const struct intel_crtc_state *crtc_state,\n",
+  "> > > +\t\t\t     const struct drm_connector_state\n",
+  "> > > *conn_state);\n",
+  "> > >  bool intel_digital_port_connected(struct intel_encoder *encoder);\n",
+  "> > >\n",
+  "> > >  static inline unsigned int intel_dp_unused_lane_mask(int\n",
+  "> > > lane_count)\n",
+  "> > > --\n",
+  "> > > 2.24.1\n",
+  "> > >\n",
+  "> > > _______________________________________________\n",
+  "> > > dri-devel mailing list\n",
+  "> > > dri-devel\@lists.freedesktop.org\n",
+  "> > > https://lists.freedesktop.org/mailman/listinfo/dri-devel\n",
+  "_______________________________________________\n",
+  "dri-devel mailing list\n",
+  "dri-devel\@lists.freedesktop.org\n",
+  "https://lists.freedesktop.org/mailman/listinfo/dri-devel"
 ]
 
-98ce46eab589aa83b6e5fe7eb45dd8a61ef99e7bbaf3cafb636d195165aa0e48
+86ae07eda36b000059ee8d5523ab6e440324eb8a2bb15ed43be0d02d0cb22a73
