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spf=pass smtp.mailfrom=arm.com; dmarc=pass action=none header.from=arm.com; dkim=pass header.d=arm.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ZwwmA0HvTWsuz+QVtXEbHROxSwKkJ99daUm8VeuBw8E=; b=MsI4C+Ll4mGIP56C8cLBR03khHZkfYwmkoQ2L+abNOCKDlSF0AtrsGGMIrNDUQ7JTkxUKP/DljDrx0w/jwx/fYv9SUgk4o6obBN2AUjF6VbnclOkMjioO6SoC+6n2WcPQw7+wWPMZbWbt3ZdmNDXg0BzoMeQHzFDq3INUXpUBEY= From: Bertrand Marquis To: Julien Grall CC: Jan Beulich , Stefano Stabellini , "Volodymyr_Babchuk@epam.com" , Stefano Stabellini , "xen-devel@lists.xenproject.org" , Andre Przywara Subject: Re: [PATCH v2] xen/arm: do not read MVFR2 when is not defined Thread-Topic: [PATCH v2] xen/arm: do not read MVFR2 when is not defined Thread-Index: AQHW5fO/cBZB5l3jZkmpNH6hbDKrc6oiIY2AgAAasgCAAIUfgIAACBWAgAADOgCAAAFfAIAAAhyA Date: Mon, 11 Jan 2021 19:14:49 +0000 Message-ID: References: <20210108192243.25889-1-sstabellini@kernel.org> <7311f402-dd5d-7484-345a-ef62071adb58@xen.org> <9A54F469-6A90-46C8-8BC4-673F469240E7@arm.com> <5d38eb31-7fbb-50f8-e8b8-ea9704122b1f@xen.org> In-Reply-To: <5d38eb31-7fbb-50f8-e8b8-ea9704122b1f@xen.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: Apple Mail (2.3608.120.23.2.4) Authentication-Results-Original: xen.org; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Jan 2021 19:14:57.6230 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f4a0554f-a2cf-44ec-4404-08d8b6652f6a X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT047.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PA4PR08MB6317 Hi, > On 11 Jan 2021, at 19:07, Julien Grall wrote: >=20 >=20 >=20 > On 11/01/2021 19:02, Bertrand Marquis wrote: >> Hi Julien, >=20 > Hi Bertrand, >=20 >>> On 11 Jan 2021, at 18:50, Julien Grall wrote: >>>=20 >>> On 11/01/2021 18:21, Bertrand Marquis wrote: >>>> Hi Julien, >>>=20 >>> Hi Bertrand, >>>=20 >>>> Sorry for the delay but I was on holiday until today. >>>=20 >>> Welcome back! No worries. >>>=20 >>>>> On 11 Jan 2021, at 10:25, Julien Grall wrote: >>>>>=20 >>>>> Hi Jan, >>>>>=20 >>>>> On 11/01/2021 08:49, Jan Beulich wrote: >>>>>> On 08.01.2021 20:22, Stefano Stabellini wrote: >>>>>>> MVFR2 is not available on ARMv7. It is available on ARMv8 aarch32 a= nd >>>>>>> aarch64. If Xen reads MVFR2 on ARMv7 it could crash. >>>>>>>=20 >>>>>>> Avoid the issue by doing the following: >>>>>>>=20 >>>>>>> - define MVFR2_MAYBE_UNDEFINED on arm32 >>>>>>> - if MVFR2_MAYBE_UNDEFINED, do not attempt to read MVFR2 in Xen >>>>>>> - keep the 3rd register_t in struct cpuinfo_arm.mvfr on arm32 so th= at a >>>>>>> guest read to the register returns '0' instead of crashing the gu= est. >>>>>>>=20 >>>>>>> '0' is an appropriate value to return to the guest because it is de= fined >>>>>>> as "no support for miscellaneous features". >>>>>>>=20 >>>>>>> Aarch64 Xen is not affected by this patch. >>>>>> But it looks to also be affected by ... >>>>>=20 >>>>> AFAICT, the smoke test passed on Laxton0 (AMD Seattle) [1] over the w= eek-end. >>>>>=20 >>>>>>> Fixes: 9cfdb489af81 ("xen/arm: Add ID registers and complete cpuinf= o") >>>>>> ... this, faulting (according to osstest logs) early during boot on >>>>>=20 >>>>> The xen-unstable flight [2] ran on Rochester0 (Cavium Thunder-X). So = this has something to do with the platform. >>>>>=20 >>>>> The main difference is AMD Seattle supports AArch32 while Cavium Thun= der-X doesn't. >>>>>=20 >>>>>> 000000000025D314 mrs x1, id_pfr2_el1 >>>>> This register contains information for the AArch32 state. >>>>>=20 >>>>> AFAICT, the Arm Arm back to at least ARM DDI 0487A.j (published in 20= 16) described the encoding as Read-Only. So I am not sure why we receive an= UNDEF here, the more it looks like ID_PFR{0, 1}_EL1 were correctly accesse= d. >>>>>=20 >>>>> Andre, Bertrand, do you have any clue? >>>> I will double check this but my understanding when I checked this was = that it would be possible to read with an unknown value but should not gene= rate an UNDEF. >>>>>=20 >>>>> However, most of the AArch32 ID registers are UNKNOWN on platform not= implementing AArch32. So we may want to conditionally skip the access to A= Arch32 state. >>>> We could skip aarch32 registers on platforms not supporting aarch32 bu= t we will still have to provide values to a guest trying to access them so = might be better to return what is returned by the hardware. >>>=20 >>> Per the Arm Arm, the value of the registers may changed at any time. IO= W, two read of the sytem registers may return different values. >>>=20 >>> IIRC, the original intent of the series was to provide sanitized value = of the ID registers. So I think it would be unwise to let the guest using t= he values. >>>=20 >>> Instead, I would suggest to implement them as RAZ. >> Works for me. >>>=20 >>>> Now if some platforms are generating an UNDEF we need to understand in= what cases and behave the same way for the guest. >>>=20 >>> I am not entirely sure what you mean by platforms here. >>>=20 >>> If you mean any platform conforming with the Arm Arm, then I agree with= your statement. >>>=20 >>> However, if you refer to platform that may not follow the Arm Arm, then= I disagree. We should try to expose a sane interface to the guest whenever= it is possible. >>>=20 >>> In this case, I would bet the hardware would not even allow us to trap = the ID_PFR2. Although, I haven't tried it. >>>=20 >>>> Do i understand it right that on Cavium which has no aarch32 support t= he access is generating an UNDEF ? >>>=20 >>> Yes. The UNDEF will happen when trying to read ID_PFR2_EL1. Interesting= ly, it doesn't happen when reading ID_PFR{0, 1}_EL1. So this smells like a = silicon bug. >> Sounds like the ifdef ARM64 should be something like if (!cavium) >=20 > Hmmm.... Cavium may not the only platform where AArch32 is not supported. > So as the values are actually UNKOWN (or UNDEF or Cavium), then there is = no point to read them. >=20 > Therefore the following pseudo-code should be enough: >=20 > if ( aarch32 supported ) > read AArch32 ID registers >=20 > This will nicely solve the UNDEF on Cavium without adding more workaround= in the code :). Works for me. Cheers Bertrand >=20 > Cheers, >=20 > --=20 > Julien Grall