From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabriele Paoloni Subject: RE: [RFC PATCH v2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI Date: Mon, 8 Feb 2016 16:06:54 +0000 Message-ID: References: <1454935264-6076-1-git-send-email-gabriele.paoloni@huawei.com> <1454935264-6076-2-git-send-email-gabriele.paoloni@huawei.com> <2409806.1aGBrN4l0X@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <2409806.1aGBrN4l0X@wuerfel> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" Cc: "Guohanjun (Hanjun Guo)" , "Wangzhou (B)" , "liudongdong (C)" , Linuxarm , qiujiang , "bhelgaas@google.com" , "Lorenzo.Pieralisi@arm.com" , "tn@semihalf.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "xuwei (O)" , "linux-acpi@vger.kernel.org" , "jcm@redhat.com" , zhangjukuo , "Liguozhu (Kenneth)" List-Id: linux-acpi@vger.kernel.org Hi Arnd > -----Original Message----- > From: Arnd Bergmann [mailto:arnd@arndb.de] > Sent: 08 February 2016 13:50 > To: linux-arm-kernel@lists.infradead.org > Cc: Gabriele Paoloni; Guohanjun (Hanjun Guo); Wangzhou (B); liudongdong > (C); Linuxarm; qiujiang; bhelgaas@google.com; > Lorenzo.Pieralisi@arm.com; tn@semihalf.com; linux-pci@vger.kernel.org; > linux-kernel@vger.kernel.org; xuwei (O); linux-acpi@vger.kernel.org; > jcm@redhat.com; zhangjukuo; Liguozhu (Kenneth) > Subject: Re: [RFC PATCH v2 1/3] PCI: hisi: re-architect Hip05/Hip06 > controllers driver to preapare for ACPI > > On Monday 08 February 2016 12:41:02 Gabriele Paoloni wrote: > > + > > +/* HipXX PCIe host only supports 32-bit config access */ > > +int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int > size, > > + u32 *val) > > +{ > > + u32 reg; > > + u32 reg_val; > > + void *walker = ®_val; > > + > > + walker += (where & 0x3); > > + reg = where & ~0x3; > > + reg_val = readl(reg_base + reg); > > + > > + if (size == 1) > > + *val = *(u8 __force *) walker; > > + else if (size == 2) > > + *val = *(u16 __force *) walker; > > + else if (size == 4) > > + *val = reg_val; > > + else > > + return PCIBIOS_BAD_REGISTER_NUMBER; > > + > > + return PCIBIOS_SUCCESSFUL; > > +} > > Isn't this the same hack that Qualcomm are using? As far as I can see Qualcomm defines its own config access mechanism only for RC config read and also it seems they're having problems with reporting the device class... https://github.com/torvalds/linux/blob/master/drivers/pci/host/pcie-qcom.c#L474 Our problem is that our HW can only perform 32b rd/wr accesses So we can't use readw/readb/writew/writeb... Thanks Gab > > Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932167AbcBHQHN (ORCPT ); Mon, 8 Feb 2016 11:07:13 -0500 Received: from lhrrgout.huawei.com ([194.213.3.17]:61370 "EHLO lhrrgout.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S932116AbcBHQHK convert rfc822-to-8bit (ORCPT ); Mon, 8 Feb 2016 11:07:10 -0500 From: Gabriele Paoloni To: Arnd Bergmann , "linux-arm-kernel@lists.infradead.org" CC: "Guohanjun (Hanjun Guo)" , "Wangzhou (B)" , "liudongdong (C)" , Linuxarm , qiujiang , "bhelgaas@google.com" , "Lorenzo.Pieralisi@arm.com" , "tn@semihalf.com" , "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "xuwei (O)" , "linux-acpi@vger.kernel.org" , "jcm@redhat.com" , zhangjukuo , "Liguozhu (Kenneth)" Subject: RE: [RFC PATCH v2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI Thread-Topic: [RFC PATCH v2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI Thread-Index: AQHRYm4y5aNxJ7rYxEm4h6c72yZ2b58iKmqAgAAkSOA= Date: Mon, 8 Feb 2016 16:06:54 +0000 Message-ID: References: <1454935264-6076-1-git-send-email-gabriele.paoloni@huawei.com> <1454935264-6076-2-git-send-email-gabriele.paoloni@huawei.com> <2409806.1aGBrN4l0X@wuerfel> In-Reply-To: <2409806.1aGBrN4l0X@wuerfel> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.203.181.156] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020202.56B8BD2B.0235,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: baf2490e1c97930fc9fef2aca136c66f Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Arnd > -----Original Message----- > From: Arnd Bergmann [mailto:arnd@arndb.de] > Sent: 08 February 2016 13:50 > To: linux-arm-kernel@lists.infradead.org > Cc: Gabriele Paoloni; Guohanjun (Hanjun Guo); Wangzhou (B); liudongdong > (C); Linuxarm; qiujiang; bhelgaas@google.com; > Lorenzo.Pieralisi@arm.com; tn@semihalf.com; linux-pci@vger.kernel.org; > linux-kernel@vger.kernel.org; xuwei (O); linux-acpi@vger.kernel.org; > jcm@redhat.com; zhangjukuo; Liguozhu (Kenneth) > Subject: Re: [RFC PATCH v2 1/3] PCI: hisi: re-architect Hip05/Hip06 > controllers driver to preapare for ACPI > > On Monday 08 February 2016 12:41:02 Gabriele Paoloni wrote: > > + > > +/* HipXX PCIe host only supports 32-bit config access */ > > +int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int > size, > > + u32 *val) > > +{ > > + u32 reg; > > + u32 reg_val; > > + void *walker = ®_val; > > + > > + walker += (where & 0x3); > > + reg = where & ~0x3; > > + reg_val = readl(reg_base + reg); > > + > > + if (size == 1) > > + *val = *(u8 __force *) walker; > > + else if (size == 2) > > + *val = *(u16 __force *) walker; > > + else if (size == 4) > > + *val = reg_val; > > + else > > + return PCIBIOS_BAD_REGISTER_NUMBER; > > + > > + return PCIBIOS_SUCCESSFUL; > > +} > > Isn't this the same hack that Qualcomm are using? As far as I can see Qualcomm defines its own config access mechanism only for RC config read and also it seems they're having problems with reporting the device class... https://github.com/torvalds/linux/blob/master/drivers/pci/host/pcie-qcom.c#L474 Our problem is that our HW can only perform 32b rd/wr accesses So we can't use readw/readb/writew/writeb... Thanks Gab > > Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: gabriele.paoloni@huawei.com (Gabriele Paoloni) Date: Mon, 8 Feb 2016 16:06:54 +0000 Subject: [RFC PATCH v2 1/3] PCI: hisi: re-architect Hip05/Hip06 controllers driver to preapare for ACPI In-Reply-To: <2409806.1aGBrN4l0X@wuerfel> References: <1454935264-6076-1-git-send-email-gabriele.paoloni@huawei.com> <1454935264-6076-2-git-send-email-gabriele.paoloni@huawei.com> <2409806.1aGBrN4l0X@wuerfel> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Arnd > -----Original Message----- > From: Arnd Bergmann [mailto:arnd at arndb.de] > Sent: 08 February 2016 13:50 > To: linux-arm-kernel at lists.infradead.org > Cc: Gabriele Paoloni; Guohanjun (Hanjun Guo); Wangzhou (B); liudongdong > (C); Linuxarm; qiujiang; bhelgaas at google.com; > Lorenzo.Pieralisi at arm.com; tn at semihalf.com; linux-pci at vger.kernel.org; > linux-kernel at vger.kernel.org; xuwei (O); linux-acpi at vger.kernel.org; > jcm at redhat.com; zhangjukuo; Liguozhu (Kenneth) > Subject: Re: [RFC PATCH v2 1/3] PCI: hisi: re-architect Hip05/Hip06 > controllers driver to preapare for ACPI > > On Monday 08 February 2016 12:41:02 Gabriele Paoloni wrote: > > + > > +/* HipXX PCIe host only supports 32-bit config access */ > > +int hisi_pcie_common_cfg_read(void __iomem *reg_base, int where, int > size, > > + u32 *val) > > +{ > > + u32 reg; > > + u32 reg_val; > > + void *walker = ®_val; > > + > > + walker += (where & 0x3); > > + reg = where & ~0x3; > > + reg_val = readl(reg_base + reg); > > + > > + if (size == 1) > > + *val = *(u8 __force *) walker; > > + else if (size == 2) > > + *val = *(u16 __force *) walker; > > + else if (size == 4) > > + *val = reg_val; > > + else > > + return PCIBIOS_BAD_REGISTER_NUMBER; > > + > > + return PCIBIOS_SUCCESSFUL; > > +} > > Isn't this the same hack that Qualcomm are using? As far as I can see Qualcomm defines its own config access mechanism only for RC config read and also it seems they're having problems with reporting the device class... https://github.com/torvalds/linux/blob/master/drivers/pci/host/pcie-qcom.c#L474 Our problem is that our HW can only perform 32b rd/wr accesses So we can't use readw/readb/writew/writeb... Thanks Gab > > Arnd