From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753149AbcKIMLv convert rfc822-to-8bit (ORCPT ); Wed, 9 Nov 2016 07:11:51 -0500 Received: from lhrrgout.huawei.com ([194.213.3.17]:4127 "EHLO lhrrgout.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751021AbcKIMLq (ORCPT ); Wed, 9 Nov 2016 07:11:46 -0500 From: Gabriele Paoloni To: Arnd Bergmann , Yuanzhichang CC: "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , "bhelgaas@google.com" , "mark.rutland@arm.com" , "olof@lixom.net" , "linux-arm-kernel@lists.infradead.org" , "lorenzo.pieralisi@arm.com" , "linux-kernel@vger.kernel.org" , Linuxarm , "devicetree@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-serial@vger.kernel.org" , "minyard@acm.org" , "benh@kernel.crashing.org" , "liviu.dudau@arm.com" , "zourongrong@gmail.com" , John Garry , "zhichang.yuan02@gmail.com" , "kantyzc@163.com" , "xuwei (O)" Subject: RE: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on Hip06 Thread-Topic: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on Hip06 Thread-Index: AQHSOW8K5aTV4LQ1M0O6BqeWVWJhSaDPRlGAgAFKX+A= Date: Wed, 9 Nov 2016 12:10:43 +0000 Message-ID: References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-4-git-send-email-yuanzhichang@hisilicon.com> <1555494.4IFvGxvsfe@wuerfel> In-Reply-To: <1555494.4IFvGxvsfe@wuerfel> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.203.181.158] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A0B0206.5823124F.0180,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=0.0.0.0, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 1e9f88d50239c4133042febe4386a53e Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Arnd > -----Original Message----- > From: Arnd Bergmann [mailto:arnd@arndb.de] > Sent: 08 November 2016 16:25 > To: Yuanzhichang > Cc: catalin.marinas@arm.com; will.deacon@arm.com; robh+dt@kernel.org; > bhelgaas@google.com; mark.rutland@arm.com; olof@lixom.net; linux-arm- > kernel@lists.infradead.org; lorenzo.pieralisi@arm.com; linux- > kernel@vger.kernel.org; Linuxarm; devicetree@vger.kernel.org; linux- > pci@vger.kernel.org; linux-serial@vger.kernel.org; minyard@acm.org; > benh@kernel.crashing.org; liviu.dudau@arm.com; zourongrong@gmail.com; > John Garry; Gabriele Paoloni; zhichang.yuan02@gmail.com; > kantyzc@163.com; xuwei (O) > Subject: Re: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on > Hip06 > > On Tuesday, November 8, 2016 11:47:09 AM CET zhichang.yuan wrote: > > + /* > > + * The first PCIBIOS_MIN_IO is reserved specifically for > indirectIO. > > + * It will separate indirectIO range from pci host bridge to > > + * avoid the possible PIO conflict. > > + * Set the indirectIO range directly here. > > + */ > > + lpcdev->io_ops.start = 0; > > + lpcdev->io_ops.end = PCIBIOS_MIN_IO - 1; > > + lpcdev->io_ops.devpara = lpcdev; > > + lpcdev->io_ops.pfin = hisilpc_comm_in; > > + lpcdev->io_ops.pfout = hisilpc_comm_out; > > + lpcdev->io_ops.pfins = hisilpc_comm_ins; > > + lpcdev->io_ops.pfouts = hisilpc_comm_outs; > > I have to look at patch 2 in more detail again, after missing a few > review > rounds. I'm still a bit skeptical about hardcoding a logical I/O port > range here, and would hope that we can just go through the same > assignment of logical port ranges that we have for PCI buses, > decoupling > the bus addresses from the linux-internal ones. The point here is that we want to avoid any conflict/overlap between the LPC I/O space and the PCI I/O space. With the assignment above we make sure that LPC never interfere with PCI I/O space. Thanks Gab > > Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabriele Paoloni Subject: RE: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on Hip06 Date: Wed, 9 Nov 2016 12:10:43 +0000 Message-ID: References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-4-git-send-email-yuanzhichang@hisilicon.com> <1555494.4IFvGxvsfe@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <1555494.4IFvGxvsfe@wuerfel> Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Arnd Bergmann , Yuanzhichang Cc: "catalin.marinas-5wv7dgnIgG8@public.gmane.org" , "will.deacon-5wv7dgnIgG8@public.gmane.org" , "robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org" , "bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org" , "mark.rutland-5wv7dgnIgG8@public.gmane.org" , "olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org" , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Linuxarm , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "minyard-HInyCGIudOg@public.gmane.org" , "benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org" List-Id: devicetree@vger.kernel.org Hi Arnd > -----Original Message----- > From: Arnd Bergmann [mailto:arnd-r2nGTMty4D4@public.gmane.org] > Sent: 08 November 2016 16:25 > To: Yuanzhichang > Cc: catalin.marinas-5wv7dgnIgG8@public.gmane.org; will.deacon-5wv7dgnIgG8@public.gmane.org; robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org; > bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org; mark.rutland-5wv7dgnIgG8@public.gmane.org; olof-nZhT3qVonbNeoWH0uzbU5w@public.gmane.org; linux-arm- > kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org; lorenzo.pieralisi-5wv7dgnIgG8@public.gmane.org; linux- > kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; Linuxarm; devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux- > pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; linux-serial-u79uwXL29TY76Z2rM5mHXA@public.gmane.org; minyard-HInyCGIudOg@public.gmane.org; > benh-XVmvHMARGAS8U2dJNN8I7kB+6BGkLq7r@public.gmane.org; liviu.dudau-5wv7dgnIgG8@public.gmane.org; zourongrong-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; > John Garry; Gabriele Paoloni; zhichang.yuan02-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org; > kantyzc-9Onoh4P/yGk@public.gmane.org; xuwei (O) > Subject: Re: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on > Hip06 > > On Tuesday, November 8, 2016 11:47:09 AM CET zhichang.yuan wrote: > > + /* > > + * The first PCIBIOS_MIN_IO is reserved specifically for > indirectIO. > > + * It will separate indirectIO range from pci host bridge to > > + * avoid the possible PIO conflict. > > + * Set the indirectIO range directly here. > > + */ > > + lpcdev->io_ops.start = 0; > > + lpcdev->io_ops.end = PCIBIOS_MIN_IO - 1; > > + lpcdev->io_ops.devpara = lpcdev; > > + lpcdev->io_ops.pfin = hisilpc_comm_in; > > + lpcdev->io_ops.pfout = hisilpc_comm_out; > > + lpcdev->io_ops.pfins = hisilpc_comm_ins; > > + lpcdev->io_ops.pfouts = hisilpc_comm_outs; > > I have to look at patch 2 in more detail again, after missing a few > review > rounds. I'm still a bit skeptical about hardcoding a logical I/O port > range here, and would hope that we can just go through the same > assignment of logical port ranges that we have for PCI buses, > decoupling > the bus addresses from the linux-internal ones. The point here is that we want to avoid any conflict/overlap between the LPC I/O space and the PCI I/O space. With the assignment above we make sure that LPC never interfere with PCI I/O space. Thanks Gab > > Arnd -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lhrrgout.huawei.com ([194.213.3.17]:4127 "EHLO lhrrgout.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751021AbcKIMLq (ORCPT ); Wed, 9 Nov 2016 07:11:46 -0500 From: Gabriele Paoloni To: Arnd Bergmann , Yuanzhichang CC: "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , "bhelgaas@google.com" , "mark.rutland@arm.com" , "olof@lixom.net" , "linux-arm-kernel@lists.infradead.org" , "lorenzo.pieralisi@arm.com" , "linux-kernel@vger.kernel.org" , Linuxarm , "devicetree@vger.kernel.org" , "linux-pci@vger.kernel.org" , "linux-serial@vger.kernel.org" , "minyard@acm.org" , "benh@kernel.crashing.org" , "liviu.dudau@arm.com" , "zourongrong@gmail.com" , John Garry , "zhichang.yuan02@gmail.com" , "kantyzc@163.com" , "xuwei (O)" Subject: RE: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on Hip06 Date: Wed, 9 Nov 2016 12:10:43 +0000 Message-ID: References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-4-git-send-email-yuanzhichang@hisilicon.com> <1555494.4IFvGxvsfe@wuerfel> In-Reply-To: <1555494.4IFvGxvsfe@wuerfel> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org List-ID: Hi Arnd > -----Original Message----- > From: Arnd Bergmann [mailto:arnd@arndb.de] > Sent: 08 November 2016 16:25 > To: Yuanzhichang > Cc: catalin.marinas@arm.com; will.deacon@arm.com; robh+dt@kernel.org; > bhelgaas@google.com; mark.rutland@arm.com; olof@lixom.net; linux-arm- > kernel@lists.infradead.org; lorenzo.pieralisi@arm.com; linux- > kernel@vger.kernel.org; Linuxarm; devicetree@vger.kernel.org; linux- > pci@vger.kernel.org; linux-serial@vger.kernel.org; minyard@acm.org; > benh@kernel.crashing.org; liviu.dudau@arm.com; zourongrong@gmail.com; > John Garry; Gabriele Paoloni; zhichang.yuan02@gmail.com; > kantyzc@163.com; xuwei (O) > Subject: Re: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on > Hip06 > > On Tuesday, November 8, 2016 11:47:09 AM CET zhichang.yuan wrote: > > + /* > > + * The first PCIBIOS_MIN_IO is reserved specifically for > indirectIO. > > + * It will separate indirectIO range from pci host bridge to > > + * avoid the possible PIO conflict. > > + * Set the indirectIO range directly here. > > + */ > > + lpcdev->io_ops.start = 0; > > + lpcdev->io_ops.end = PCIBIOS_MIN_IO - 1; > > + lpcdev->io_ops.devpara = lpcdev; > > + lpcdev->io_ops.pfin = hisilpc_comm_in; > > + lpcdev->io_ops.pfout = hisilpc_comm_out; > > + lpcdev->io_ops.pfins = hisilpc_comm_ins; > > + lpcdev->io_ops.pfouts = hisilpc_comm_outs; > > I have to look at patch 2 in more detail again, after missing a few > review > rounds. I'm still a bit skeptical about hardcoding a logical I/O port > range here, and would hope that we can just go through the same > assignment of logical port ranges that we have for PCI buses, > decoupling > the bus addresses from the linux-internal ones. The point here is that we want to avoid any conflict/overlap between the LPC I/O space and the PCI I/O space. With the assignment above we make sure that LPC never interfere with PCI I/O space. Thanks Gab > > Arnd From mboxrd@z Thu Jan 1 00:00:00 1970 From: gabriele.paoloni@huawei.com (Gabriele Paoloni) Date: Wed, 9 Nov 2016 12:10:43 +0000 Subject: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on Hip06 In-Reply-To: <1555494.4IFvGxvsfe@wuerfel> References: <1478576829-112707-1-git-send-email-yuanzhichang@hisilicon.com> <1478576829-112707-4-git-send-email-yuanzhichang@hisilicon.com> <1555494.4IFvGxvsfe@wuerfel> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Arnd > -----Original Message----- > From: Arnd Bergmann [mailto:arnd at arndb.de] > Sent: 08 November 2016 16:25 > To: Yuanzhichang > Cc: catalin.marinas at arm.com; will.deacon at arm.com; robh+dt at kernel.org; > bhelgaas at google.com; mark.rutland at arm.com; olof at lixom.net; linux-arm- > kernel at lists.infradead.org; lorenzo.pieralisi at arm.com; linux- > kernel at vger.kernel.org; Linuxarm; devicetree at vger.kernel.org; linux- > pci at vger.kernel.org; linux-serial at vger.kernel.org; minyard at acm.org; > benh at kernel.crashing.org; liviu.dudau at arm.com; zourongrong at gmail.com; > John Garry; Gabriele Paoloni; zhichang.yuan02 at gmail.com; > kantyzc at 163.com; xuwei (O) > Subject: Re: [PATCH V5 3/3] ARM64 LPC: LPC driver implementation on > Hip06 > > On Tuesday, November 8, 2016 11:47:09 AM CET zhichang.yuan wrote: > > + /* > > + * The first PCIBIOS_MIN_IO is reserved specifically for > indirectIO. > > + * It will separate indirectIO range from pci host bridge to > > + * avoid the possible PIO conflict. > > + * Set the indirectIO range directly here. > > + */ > > + lpcdev->io_ops.start = 0; > > + lpcdev->io_ops.end = PCIBIOS_MIN_IO - 1; > > + lpcdev->io_ops.devpara = lpcdev; > > + lpcdev->io_ops.pfin = hisilpc_comm_in; > > + lpcdev->io_ops.pfout = hisilpc_comm_out; > > + lpcdev->io_ops.pfins = hisilpc_comm_ins; > > + lpcdev->io_ops.pfouts = hisilpc_comm_outs; > > I have to look at patch 2 in more detail again, after missing a few > review > rounds. I'm still a bit skeptical about hardcoding a logical I/O port > range here, and would hope that we can just go through the same > assignment of logical port ranges that we have for PCI buses, > decoupling > the bus addresses from the linux-internal ones. The point here is that we want to avoid any conflict/overlap between the LPC I/O space and the PCI I/O space. With the assignment above we make sure that LPC never interfere with PCI I/O space. Thanks Gab > > Arnd