From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabriele Paoloni Subject: RE: [PATCH v10 0/9] LPC: legacy ISA I/O support Date: Mon, 30 Oct 2017 11:32:14 +0000 Message-ID: References: <1509120687-7352-1-git-send-email-gabriele.paoloni@huawei.com> <063D6719AE5E284EB5DD2968C1650D6DD00A6F5C@AcuExch.aculab.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6DD00A6F5C@AcuExch.aculab.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane.org@lists.infradead.org To: David Laight , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , "frowand.list@gmail.com" , "bhelgaas@google.com" , "rafael@kernel.org" , "arnd@arndb.de" , "linux-arm-kernel@lists.infradead.org" , "lorenzo.pieralisi@arm.com" Cc: "mark.rutland@arm.com" , "minyard@acm.org" , "benh@kernel.crashing.org" , John Garry , "linux-kernel@vger.kernel.org" , "xuwei (O)" , Linuxarm , "linux-acpi@vger.kernel.org" , "linux-pci@vger.kernel.org" , "olof@lixom.net" , "brian.starkey@arm.com" List-Id: linux-acpi@vger.kernel.org Hi David [...] > FWIW my thoughts on this are WTF! > > Looks to me horribly over complicated and over generalised. > > Surely is it could be done the same way that x86 does IO cycles? No > So you encode the information into the 'address' the driver passes > to ioread16() (etc) to allow it to do either a normal bus cycle or > the indirect cycle onto the external bus. In order to do that you need to have a special PCI bridge that is able to detect the special IO addresses and initiate such special IO cycles on the external bus. This is not supported by our HW (and this why we need the LPC accessors) Gab > > So you have one kernel option that makes these real functions. > > David From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932281AbdJ3Ljf convert rfc822-to-8bit (ORCPT ); Mon, 30 Oct 2017 07:39:35 -0400 Received: from dfwrgout.huawei.com ([206.16.17.72]:2099 "EHLO dfwrgout.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752451AbdJ3Ljd (ORCPT ); Mon, 30 Oct 2017 07:39:33 -0400 X-Greylist: delayed 415 seconds by postgrey-1.27 at vger.kernel.org; Mon, 30 Oct 2017 07:39:33 EDT From: Gabriele Paoloni To: David Laight , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , "frowand.list@gmail.com" , "bhelgaas@google.com" , "rafael@kernel.org" , "arnd@arndb.de" , "linux-arm-kernel@lists.infradead.org" , "lorenzo.pieralisi@arm.com" CC: "mark.rutland@arm.com" , "brian.starkey@arm.com" , "olof@lixom.net" , "benh@kernel.crashing.org" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , Linuxarm , "linux-pci@vger.kernel.org" , "minyard@acm.org" , John Garry , "xuwei (O)" Subject: RE: [PATCH v10 0/9] LPC: legacy ISA I/O support Thread-Topic: [PATCH v10 0/9] LPC: legacy ISA I/O support Thread-Index: AQHTTz5lUsUvmUVHGEOpQaZ2riZ2DKL3xhwAgAR/j9A= Date: Mon, 30 Oct 2017 11:32:14 +0000 Message-ID: References: <1509120687-7352-1-git-send-email-gabriele.paoloni@huawei.com> <063D6719AE5E284EB5DD2968C1650D6DD00A6F5C@AcuExch.aculab.com> In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6DD00A6F5C@AcuExch.aculab.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.226.113] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi David [...] > FWIW my thoughts on this are WTF! > > Looks to me horribly over complicated and over generalised. > > Surely is it could be done the same way that x86 does IO cycles? No > So you encode the information into the 'address' the driver passes > to ioread16() (etc) to allow it to do either a normal bus cycle or > the indirect cycle onto the external bus. In order to do that you need to have a special PCI bridge that is able to detect the special IO addresses and initiate such special IO cycles on the external bus. This is not supported by our HW (and this why we need the LPC accessors) Gab > > So you have one kernel option that makes these real functions. > > David From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: Gabriele Paoloni To: David Laight , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , "frowand.list@gmail.com" , "bhelgaas@google.com" , "rafael@kernel.org" , "arnd@arndb.de" , "linux-arm-kernel@lists.infradead.org" , "lorenzo.pieralisi@arm.com" Subject: RE: [PATCH v10 0/9] LPC: legacy ISA I/O support Date: Mon, 30 Oct 2017 11:32:14 +0000 Message-ID: References: <1509120687-7352-1-git-send-email-gabriele.paoloni@huawei.com> <063D6719AE5E284EB5DD2968C1650D6DD00A6F5C@AcuExch.aculab.com> In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6DD00A6F5C@AcuExch.aculab.com> MIME-Version: 1.0 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "minyard@acm.org" , "benh@kernel.crashing.org" , John Garry , "linux-kernel@vger.kernel.org" , "xuwei \(O\)" , Linuxarm , "linux-acpi@vger.kernel.org" , "linux-pci@vger.kernel.org" , "olof@lixom.net" , "brian.starkey@arm.com" Content-Type: text/plain; charset="us-ascii" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: Hi David [...] > FWIW my thoughts on this are WTF! > > Looks to me horribly over complicated and over generalised. > > Surely is it could be done the same way that x86 does IO cycles? No > So you encode the information into the 'address' the driver passes > to ioread16() (etc) to allow it to do either a normal bus cycle or > the indirect cycle onto the external bus. In order to do that you need to have a special PCI bridge that is able to detect the special IO addresses and initiate such special IO cycles on the external bus. This is not supported by our HW (and this why we need the LPC accessors) Gab > > So you have one kernel option that makes these real functions. > > David _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel From mboxrd@z Thu Jan 1 00:00:00 1970 From: gabriele.paoloni@huawei.com (Gabriele Paoloni) Date: Mon, 30 Oct 2017 11:32:14 +0000 Subject: [PATCH v10 0/9] LPC: legacy ISA I/O support In-Reply-To: <063D6719AE5E284EB5DD2968C1650D6DD00A6F5C@AcuExch.aculab.com> References: <1509120687-7352-1-git-send-email-gabriele.paoloni@huawei.com> <063D6719AE5E284EB5DD2968C1650D6DD00A6F5C@AcuExch.aculab.com> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi David [...] > FWIW my thoughts on this are WTF! > > Looks to me horribly over complicated and over generalised. > > Surely is it could be done the same way that x86 does IO cycles? No > So you encode the information into the 'address' the driver passes > to ioread16() (etc) to allow it to do either a normal bus cycle or > the indirect cycle onto the external bus. In order to do that you need to have a special PCI bridge that is able to detect the special IO addresses and initiate such special IO cycles on the external bus. This is not supported by our HW (and this why we need the LPC accessors) Gab > > So you have one kernel option that makes these real functions. > > David