From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabriele Paoloni Subject: RE: [PATCH v10 1/9] LIB: Introduce a generic PIO mapping method Date: Mon, 30 Oct 2017 15:31:21 +0000 Message-ID: References: <1509120687-7352-1-git-send-email-gabriele.paoloni@huawei.com> <1509120687-7352-2-git-send-email-gabriele.paoloni@huawei.com> <49ac8217-1e89-bb4a-8592-9d57039f792c@acm.org> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from lhrrgout.huawei.com ([194.213.3.17]:39401 "EHLO lhrrgout.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752166AbdJ3Pbv (ORCPT ); Mon, 30 Oct 2017 11:31:51 -0400 In-Reply-To: <49ac8217-1e89-bb4a-8592-9d57039f792c@acm.org> Content-Language: en-US Sender: linux-acpi-owner@vger.kernel.org List-Id: linux-acpi@vger.kernel.org To: "minyard@acm.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , "frowand.list@gmail.com" , "bhelgaas@google.com" , "rafael@kernel.org" , "arnd@arndb.de" , "linux-arm-kernel@lists.infradead.org" , "lorenzo.pieralisi@arm.com" Cc: "mark.rutland@arm.com" , "brian.starkey@arm.com" , "olof@lixom.net" , "benh@kernel.crashing.org" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , Linuxarm , "linux-pci@vger.kernel.org" , John Garry , "xuwei (O)" , "zhichang.yuan" SGkgQ29yZXkNCg0KTWFueSBUaGFua3MgZm9yIHlvdXIgY29tbWVudHMNCg0KWy4uLl0NCg0KPiA+ ICAgI2RlZmluZSBJT19TUEFDRV9MSU1JVCAweGZmZmYNCj4gPiAgICNlbmRpZg0KPiA+DQo+ID4g KyNpbmNsdWRlIDxsaW51eC9sb2dpY19waW8uaD4NCj4gDQo+IFRoaXMgd2hvbGUgdGhpbmcgd291 bGQgYmUgYSBsb3Qgc2ltcGxlciBpZiB5b3UgaGFkOg0KPiANCj4gI2lmZGVmIENPTkZJR19JTkRJ UkVDVF9QSU8NCj4gI2RlZmluZSBpbmIgbG9naWNfaW5iDQo+ICNkZWZpbmUgb3V0YiBsb2dpYyBv dXRiDQo+IC4NCj4gLg0KPiAjZW5kaWYgLyogQ09ORklHX0lORElSRUNUX1BJTyAqLw0KPiANCj4g YW5kIGxldCB0aGUgImlmbmRlZiBYWFgiIGJlbG93IGhhbmRsZSBub3QgZW5hYmxpbmcgdGhlIHN0 YW5kYXJkIGNvZGUuDQo+IFlvdSBjb3VsZCBldmVuIHB1dCB0aGF0IGluIGxvZ2ljX3Bpby5oIHRv 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S1752166AbdJ3Pbv (ORCPT ); Mon, 30 Oct 2017 11:31:51 -0400 From: Gabriele Paoloni To: "minyard@acm.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , "frowand.list@gmail.com" , "bhelgaas@google.com" , "rafael@kernel.org" , "arnd@arndb.de" , "linux-arm-kernel@lists.infradead.org" , "lorenzo.pieralisi@arm.com" CC: "mark.rutland@arm.com" , "brian.starkey@arm.com" , "olof@lixom.net" , "benh@kernel.crashing.org" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , Linuxarm , "linux-pci@vger.kernel.org" , John Garry , "xuwei (O)" , "zhichang.yuan" Subject: RE: [PATCH v10 1/9] LIB: Introduce a generic PIO mapping method Thread-Topic: [PATCH v10 1/9] LIB: Introduce a generic PIO mapping method Thread-Index: AQHTTz5n3lbQP+NHY0mGaq68pFkhiqL3494AgAR9HeA= Date: Mon, 30 Oct 2017 15:31:21 +0000 Message-ID: References: <1509120687-7352-1-git-send-email-gabriele.paoloni@huawei.com> <1509120687-7352-2-git-send-email-gabriele.paoloni@huawei.com> <49ac8217-1e89-bb4a-8592-9d57039f792c@acm.org> In-Reply-To: <49ac8217-1e89-bb4a-8592-9d57039f792c@acm.org> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.226.113] Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 X-CFilter-Loop: Reflected X-Mirapoint-Virus-RAPID-Raw: score=unknown(0), refid=str=0001.0A020203.59F745DD.01E1,ss=1,re=0.000,recu=0.000,reip=0.000,cl=1,cld=1,fgs=0, ip=169.254.1.209, so=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32 X-Mirapoint-Loop-Id: 9f57fadf250f9e44a99f265e5593c69d Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from base64 to 8bit by nfs id v9UFVwYA007106 Hi Corey Many Thanks for your comments [...] > > #define IO_SPACE_LIMIT 0xffff > > #endif > > > > +#include > > This whole thing would be a lot simpler if you had: > > #ifdef CONFIG_INDIRECT_PIO > #define inb logic_inb > #define outb logic outb > . > . > #endif /* CONFIG_INDIRECT_PIO */ > > and let the "ifndef XXX" below handle not enabling the standard code. > You could even put that in logic_pio.h to avoid polluting io.h. Agreed. I'll move it into "logic_pio.h" > > You might have to add "#ifndef inb", etc. above, but I still think it > would > be better. Yes agreed also on adding the "#ifndef ***" around each function re-definition in logic_pio.h This will be fixed in v11 > > I'm not sure if this wouldn't be better done in arm64/include/asm/io.h, > though. > A specific machine may want to only do this in ranges, for instance. No I don’t think so...this io functions re-0definition has nothing to do with ARM architecture and I think it is better to keep everything in logic_pio.h including the file from "include/asm-generic/io.h" Cheers Gab > > -corey [...] > > --- a/lib/Kconfig > > +++ b/lib/Kconfig > > @@ -59,6 +59,32 @@ config ARCH_USE_CMPXCHG_LOCKREF > > config ARCH_HAS_FAST_MULTIPLIER > > bool > > > > +config LOGIC_PIO > > + bool "Generic logical I/O management" > > + def_bool y if PCI && !X86 && !IA64 && !POWERPC > > + help > > + For some architectures, there are no IO space. To support the > > + accesses to legacy I/O devices on those architectures, kernel > > + implemented the memory mapped I/O mechanism based on bridge bus > > + supports. But for some buses which do not support MMIO, the > > + peripherals there should be accessed with device-specific way. > > + To abstract those different I/O accesses into unified I/O > accessors, > > + this option provide a generic I/O space management way after > mapping > > + the device I/O to system logical/fake I/O and help to hide all > the > > + hardware detail. > > + > > +config INDIRECT_PIO > > + bool "Access I/O in non-MMIO mode" if LOGIC_PIO > > + help > > + On some platforms where no separate I/O space exist, there are > I/O > > + hosts which can not be accessed in MMIO mode. Based on > LOGIC_PIO > > + mechanism, the host-local I/O resource can be mapped into > system > > + logic PIO space shared with MMIO hosts, such as PCI/PCIE, then > system > > + can access the I/O devices with the mapped logic PIO through > I/O > > + accessors. > > + This way has a little I/O performance cost. Please make sure > your > > + devices really need this configure item enabled. > > + > > If this is always available on the hisilicon chips, I think you would > want to just always > enable this on those chips. In patch 6/9 we have +config HISILICON_LPC + bool "Support for ISA I/O space on Hisilicon Hip0X" + depends on (ARM64 && (ARCH_HISI || COMPILE_TEST)) + select LOGIC_PIO + select INDIRECT_PIO So the LPC host controller driver is selecting INDIRECT_PIO... > > -corey > Cheers Gab From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Gabriele Paoloni To: "minyard@acm.org" , "catalin.marinas@arm.com" , "will.deacon@arm.com" , "robh+dt@kernel.org" , "frowand.list@gmail.com" , "bhelgaas@google.com" , "rafael@kernel.org" , "arnd@arndb.de" , "linux-arm-kernel@lists.infradead.org" , "lorenzo.pieralisi@arm.com" CC: "mark.rutland@arm.com" , "brian.starkey@arm.com" , "olof@lixom.net" , "benh@kernel.crashing.org" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , Linuxarm , "linux-pci@vger.kernel.org" , John Garry , "xuwei (O)" , "zhichang.yuan" Subject: RE: [PATCH v10 1/9] LIB: Introduce a generic PIO mapping method Date: Mon, 30 Oct 2017 15:31:21 +0000 Message-ID: References: <1509120687-7352-1-git-send-email-gabriele.paoloni@huawei.com> <1509120687-7352-2-git-send-email-gabriele.paoloni@huawei.com> <49ac8217-1e89-bb4a-8592-9d57039f792c@acm.org> In-Reply-To: <49ac8217-1e89-bb4a-8592-9d57039f792c@acm.org> Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Sender: linux-acpi-owner@vger.kernel.org List-ID: SGkgQ29yZXkNCg0KTWFueSBUaGFua3MgZm9yIHlvdXIgY29tbWVudHMNCg0KWy4uLl0NCg0KPiA+ ICAgI2RlZmluZSBJT19TUEFDRV9MSU1JVCAweGZmZmYNCj4gPiAgICNlbmRpZg0KPiA+DQo+ID4g KyNpbmNsdWRlIDxsaW51eC9sb2dpY19waW8uaD4NCj4gDQo+IFRoaXMgd2hvbGUgdGhpbmcgd291 bGQgYmUgYSBsb3Qgc2ltcGxlciBpZiB5b3UgaGFkOg0KPiANCj4gI2lmZGVmIENPTkZJR19JTkRJ UkVDVF9QSU8NCj4gI2RlZmluZSBpbmIgbG9naWNfaW5iDQo+ICNkZWZpbmUgb3V0YiBsb2dpYyBv dXRiDQo+IC4NCj4gLg0KPiAjZW5kaWYgLyogQ09ORklHX0lORElSRUNUX1BJTyAqLw0KPiANCj4g YW5kIGxldCB0aGUgImlmbmRlZiBYWFgiIGJlbG93IGhhbmRsZSBub3QgZW5hYmxpbmcgdGhlIHN0 YW5kYXJkIGNvZGUuDQo+IFlvdSBjb3VsZCBldmVuIHB1dCB0aGF0IGluIGxvZ2ljX3Bpby5oIHRv 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<1509120687-7352-1-git-send-email-gabriele.paoloni@huawei.com> <1509120687-7352-2-git-send-email-gabriele.paoloni@huawei.com> <49ac8217-1e89-bb4a-8592-9d57039f792c@acm.org> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Corey Many Thanks for your comments [...] > > #define IO_SPACE_LIMIT 0xffff > > #endif > > > > +#include > > This whole thing would be a lot simpler if you had: > > #ifdef CONFIG_INDIRECT_PIO > #define inb logic_inb > #define outb logic outb > . > . > #endif /* CONFIG_INDIRECT_PIO */ > > and let the "ifndef XXX" below handle not enabling the standard code. > You could even put that in logic_pio.h to avoid polluting io.h. Agreed. I'll move it into "logic_pio.h" > > You might have to add "#ifndef inb", etc. above, but I still think it > would > be better. Yes agreed also on adding the "#ifndef ***" around each function re-definition in logic_pio.h This will be fixed in v11 > > I'm not sure if this wouldn't be better done in arm64/include/asm/io.h, > though. > A specific machine may want to only do this in ranges, for instance. No I don?t think so...this io functions re-0definition has nothing to do with ARM architecture and I think it is better to keep everything in logic_pio.h including the file from "include/asm-generic/io.h" Cheers Gab > > -corey [...] > > --- a/lib/Kconfig > > +++ b/lib/Kconfig > > @@ -59,6 +59,32 @@ config ARCH_USE_CMPXCHG_LOCKREF > > config ARCH_HAS_FAST_MULTIPLIER > > bool > > > > +config LOGIC_PIO > > + bool "Generic logical I/O management" > > + def_bool y if PCI && !X86 && !IA64 && !POWERPC > > + help > > + For some architectures, there are no IO space. To support the > > + accesses to legacy I/O devices on those architectures, kernel > > + implemented the memory mapped I/O mechanism based on bridge bus > > + supports. But for some buses which do not support MMIO, the > > + peripherals there should be accessed with device-specific way. > > + To abstract those different I/O accesses into unified I/O > accessors, > > + this option provide a generic I/O space management way after > mapping > > + the device I/O to system logical/fake I/O and help to hide all > the > > + hardware detail. > > + > > +config INDIRECT_PIO > > + bool "Access I/O in non-MMIO mode" if LOGIC_PIO > > + help > > + On some platforms where no separate I/O space exist, there are > I/O > > + hosts which can not be accessed in MMIO mode. Based on > LOGIC_PIO > > + mechanism, the host-local I/O resource can be mapped into > system > > + logic PIO space shared with MMIO hosts, such as PCI/PCIE, then > system > > + can access the I/O devices with the mapped logic PIO through > I/O > > + accessors. > > + This way has a little I/O performance cost. Please make sure > your > > + devices really need this configure item enabled. > > + > > If this is always available on the hisilicon chips, I think you would > want to just always > enable this on those chips. In patch 6/9 we have +config HISILICON_LPC + bool "Support for ISA I/O space on Hisilicon Hip0X" + depends on (ARM64 && (ARCH_HISI || COMPILE_TEST)) + select LOGIC_PIO + select INDIRECT_PIO So the LPC host controller driver is selecting INDIRECT_PIO... > > -corey > Cheers Gab