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Date: Tue, 14 Nov 2023 10:13:58 -0500
From: David Woodhouse <dwmw2@infradead.org>
To: =?ISO-8859-1?Q?Philippe_Mathieu-Daud=E9?= <philmd@linaro.org>,
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On 14 November 2023 09:38:02 GMT-05:00, "Philippe Mathieu-Daud=C3=A9" <phil=
md@linaro=2Eorg> wrote:
>Similarly to the restriction in hw/pci/msix=2Ec (see commit
>e1e4bf2252 "msix: fix msix_vector_masked"), restrict the
>xen_is_pirq_msi() call in msi_is_masked() to Xen=2E
>
>Signed-off-by: Philippe Mathieu-Daud=C3=A9 <philmd@linaro=2Eorg>

Hm, we do also support the Xen abomination of snooping on MSI table writes=
 to see if they're targeted at a Xen PIRQ, then actually unmasking the MSI =
from QEMU when the guest binds the corresponding event channel to that PIRQ=
=2E

I think this is going to break in CI as kvm_xen_guest=2Epy does deliberate=
ly exercise that use case, doesn't it?

I deliberately *didn't* switch to testing the Xen PV net device, with a co=
mment that testing MSI and irqchip permutations was far more entertaining=
=2E So I hope it should catch this?