From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57567) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1amiyb-0006Q6-C8 for qemu-devel@nongnu.org; Sun, 03 Apr 2016 10:26:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1amiya-0002H4-Cy for qemu-devel@nongnu.org; Sun, 03 Apr 2016 10:26:05 -0400 From: Aleksandar Markovic Date: Sun, 3 Apr 2016 14:25:50 +0000 Message-ID: References: <1458910214-12239-1-git-send-email-aleksandar.markovic@rt-rk.com> <1458910214-12239-2-git-send-email-aleksandar.markovic@rt-rk.com>, <56FEC5D1.8020908@imgtec.com> In-Reply-To: <56FEC5D1.8020908@imgtec.com> Content-Language: en-US Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurable meaning of signaling NaN bit List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae , Aleksandar Markovic , "qemu-devel@nongnu.org" Cc: "peter.maydell@linaro.org" , "ehabkost@redhat.com" , "kbastian@mail.uni-paderborn.de" , "rth@twiddle.net" , "mark.cave-ayland@ilande.co.uk" , "agraf@suse.de" , Petar Jovanovic , "blauwirbel@gmail.com" , "jcmvbkbc@gmail.com" , Miodrag Dinic , "qemu-arm@nongnu.org" , "qemu-ppc@nongnu.org" , "pbonzini@redhat.com" , "edgar.iglesias@gmail.com" , "gxt@mprc.pku.edu.cn" , "afaerber@suse.de" , "aurelien@aurel32.net" , "proljc@gmail.com" I truly appreciate your guidance and bringing this matter to my attention.= =0A= =0A= It just seems to me that, in similar case, 16-bit default NaN value should = be 0x7E00. This value is needed for MSA operations. ("MIPS Architecture for= Programmers Volume IV-j: The MIPS32=AE SIMD Architecture Module", Revision= 1.12, (february 3, 2016), page 52, table 3.7 "Default NaN Encodings")=0A= =0A= I plan to include all three corrections in the next version of this patch s= et. Please, let me know if you think that I should not.=0A= =0A= Yours,=0A= Aleksandar=0A= =0A= =0A= =0A= ________________________________________=0A= From: qemu-devel-bounces+aleksandar.markovic=3Dimgtec.com@nongnu.org [qemu-= devel-bounces+aleksandar.markovic=3Dimgtec.com@nongnu.org] on behalf of Leo= n Alrae=0A= Sent: Friday, April 01, 2016 12:02 PM=0A= To: Aleksandar Markovic; qemu-devel@nongnu.org=0A= Cc: peter.maydell@linaro.org; ehabkost@redhat.com; proljc@gmail.com; mark.c= ave-ayland@ilande.co.uk; agraf@suse.de; kbastian@mail.uni-paderborn.de; Pet= ar Jovanovic; blauwirbel@gmail.com; jcmvbkbc@gmail.com; Miodrag Dinic; qemu= -arm@nongnu.org; qemu-ppc@nongnu.org; edgar.iglesias@gmail.com; pbonzini@re= dhat.com; gxt@mprc.pku.edu.cn; afaerber@suse.de; aurelien@aurel32.net; rth@= twiddle.net=0A= Subject: Re: [Qemu-devel] [PATCH 1/2] softfloat: Enable run-time-configurab= le meaning of signaling NaN bit=0A= =0A= On 25/03/16 12:50, Aleksandar Markovic wrote:=0A= > /*----------------------------------------------------------------------= ------=0A= > | The pattern for a default generated single-precision NaN.=0A= > *-----------------------------------------------------------------------= -----*/=0A= > +float32 float32_default_nan(float_status *status) {=0A= > #if defined(TARGET_SPARC)=0A= > -const float32 float32_default_nan =3D const_float32(0x7FFFFFFF);=0A= > + return const_float32(0x7FFFFFFF);=0A= > #elif defined(TARGET_PPC) || defined(TARGET_ARM) || defined(TARGET_ALPHA= ) || \=0A= > defined(TARGET_XTENSA) || defined(TARGET_S390X) || defined(TARGET_= TRICORE)=0A= > -const float32 float32_default_nan =3D const_float32(0x7FC00000);=0A= > -#elif SNAN_BIT_IS_ONE=0A= > -const float32 float32_default_nan =3D const_float32(0x7FBFFFFF);=0A= > + return const_float32(0x7FC00000);=0A= > #else=0A= > -const float32 float32_default_nan =3D const_float32(0xFFC00000);=0A= > + if (status->snan_bit_is_one)=0A= > + return const_float32(0x7FBFFFFF);=0A= > + else=0A= > + return const_float32(0xFFC00000);=0A= =0A= Here for MIPS (when FCR31.NAN2008 is set) we should generate 0x7FC00000=0A= for single-precision. Reference:=0A= "MIPS Architecture For Programmers, Volume I-A: Introduction to the=0A= MIPS64 Architecture", Imagination Technologies LTD., Document Number:=0A= MD00083, Revision 6.01, August 20, 2014, Table 6.3 "Value Supplied When=0A= a New Quiet NaN Is Created", p. 84=0A= =0A= Also, for double-precision we should generate 0x7FF8000000000000.=0A= =0A= Thanks,=0A= Leon=0A= =0A=