From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Srinivas, Vidya" Subject: Re: [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc Date: Fri, 9 Feb 2018 03:50:09 +0000 Message-ID: References: <1517921899-25926-1-git-send-email-vidya.srinivas@intel.com> <1517921899-25926-4-git-send-email-vidya.srinivas@intel.com> <82dbc81e-5fa7-bed9-fc45-b93983789035@intel.com> <004b81a0-c856-dc5b-1dfc-8e7707f21a86@intel.com> <2dcd8a50-7e0d-2c5e-83cf-144ea4e8971f@intel.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0354580878==" Return-path: Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C02F6E708 for ; Fri, 9 Feb 2018 03:50:14 +0000 (UTC) In-Reply-To: <2dcd8a50-7e0d-2c5e-83cf-144ea4e8971f@intel.com> Content-Language: en-US List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Sharma, Shashank" , "intel-gfx@lists.freedesktop.org" List-Id: intel-gfx@lists.freedesktop.org --===============0354580878== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_F653A0A18852B74D88578FA2EB7094EAB6822890BGSMSX108garcor_" --_000_F653A0A18852B74D88578FA2EB7094EAB6822890BGSMSX108garcor_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable From: Sharma, Shashank Sent: Thursday, February 8, 2018 12:17 PM To: Srinivas, Vidya ; intel-gfx@lists.freedesktop= .org Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil ; Shankar, Uma ; Kumar, Mahesh1 Subject: Re: [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc Regards Shashank On 2/8/2018 10:02 AM, Sharma, Shashank wrote: On 2/8/2018 8:50 AM, Srinivas, Vidya wrote: -----Original Message----- From: Sharma, Shashank Sent: Wednesday, February 7, 2018 9:22 PM To: Srinivas, Vidya ; intel- gfx@lists.freedesktop.org Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil ; Shankar, Uma ; Kumar, Mahesh1 Subject: Re: [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format_to_fourcc Regards Shashank On 2/6/2018 6:28 PM, Vidya Srinivas wrote: From: Mahesh Kumar Add support of recognizing DRM_FORMAT_NV12 from plane_format register value. Signed-off-by: Mahesh Kumar --- drivers/gpu/drm/i915/intel_display.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 60ba5bb..e3a6a7f 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha) switch (format) { case PLANE_CTL_FORMAT_RGB_565: return DRM_FORMAT_RGB565; + case PLANE_CTL_FORMAT_NV12: + return DRM_FORMAT_NV12; I dont think this is correct, the case PLANE_CTL_FORMAT_NV12 is defined as (1 << 24) but when I check bspec definition, 24th bit is set for P010/12/16 formats. AFAIK NV12 is 8 bit format whereas P0xx formats are 10/12/16 bit formats (they both are YCBCR 4:2:0 of course). This means we have mixed NV12 format with P0xx formats. When I checked the definition of DRM_FORMAT_NV12, I am not sure if that's intended for this. Ville, I saw that the DRM_FORMAT_NV12 definition was added by you, can you please comment if this is the right usage ? Upto Gen10 24-27 bits of PLANE_CTL will be used for format. ICL onwards 23r= d bit is also used. PLANE_CTL_FORMAT_MASK has been defined in i915_reg.h and mapping will be same if 23rd bit is 0. For NV12, 1<< 24 thus holds good for all Gen. That's not my point. What I want to say is, as per bspec (1 << 24) is for P= 010/P012/P016 formats, not NV12. NV12 is 8 bit YCBCR 4:2:0 format whereas P= 010/012/016 are 10,12 and 16 bit YCBCR 4:2:0 formats. So I was not sure if = that should be called NV12 and hence I was not sure if we should return DRM= _FORMAT_NV12 for the same. - Shashank What I mean to say here is, the check (1 << 24) is not good enough for all = NV12, as you have to use it as if (mask =3D=3D YCBCR_420_FORMAT_NV12) not (= mask & YCBCR_420_FORMAT_NV12). But if that's how its intended to be used for future addition of P010/012/0= 16, then I guess you can bypass this comment, but please make sure you dif= ferentiate NV12 with those formats. - Shashank Sure thank u, will take care when P0xx gets added. default: case PLANE_CTL_FORMAT_XRGB_8888: if (rgb_order) { --_000_F653A0A18852B74D88578FA2EB7094EAB6822890BGSMSX108garcor_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

 

 

From: Sha= rma, Shashank
Sent: Thursday, February 8, 2018 12:17 PM
To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-gfx@list= s.freedesktop.org
Cc: maarten.lankhorst@linux.intel.com; Kamath, Sunil <sunil.kamat= h@intel.com>; Shankar, Uma <uma.shankar@intel.com>; Kumar, Mahesh1= <mahesh1.kumar@intel.com>
Subject: Re: [PATCH 03/16] drm/i915/skl+: add NV12 in skl_format= _to_fourcc

 

Regards

Shashank

 

On 2/8/2018 10:02 AM, Sharma, Shashank wrote:



On 2/8/2018 8:50 AM, Srinivas, Vidya wrote:



-----Original Message-----
From: Sharma, Shashank
Sent: Wednesday, February 7, 2018 9:22 PM
To: Srinivas, Vidya <vidya.s= rinivas@intel.com>; intel-
gfx@lists.freedesktop.org =
Cc: maarten.lankhorst@= linux.intel.com; Kamath, Sunil
<sunil.kamath@intel.com>; Shankar, Uma <uma.shankar@intel.com>;=
Kumar, Mahesh1 <mahesh1.kumar= @intel.com>
Subject: Re: [PATCH 03/16] drm/i915/skl+: add NV12 in
skl_format_to_fourcc

Regards

Shashank


On 2/6/2018 6:28 PM, Vidya Srinivas wrote:

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Add support of recognizing DRM_FORMAT_NV12 from plane_format

register

value.

Signed-off-by: Mahesh Kumar <= mahesh1.kumar@intel.com>
---
   drivers/gpu/drm/i915/intel_display.c | 2 ++
   1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c
b/drivers/gpu/drm/i915/intel_display.c
index 60ba5bb..e3a6a7f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2626,6 +2626,8 @@ static int skl_format_to_fourcc(int format, bool =

rgb_order, bool alpha)

       switch (format)= {
       case PLANE_CTL_FORMAT_RGB_565:
           return DRM_FOR= MAT_RGB565;
+    case PLANE_CTL_FORMAT_NV12:
+        return DRM_FORMAT_NV12;

I dont think this is = correct, the case PLANE_CTL_FORMAT_NV12 is defined as
(1 << 24) but when I check bspec definition, 24th bit is set for
P010/12/16 formats. AFAIK NV12 is 8 bit format whereas P0xx formats are 10/12/16 bit formats (they both are YCBCR 4:2:0 of course). This means we <= br> have mixed NV12 format with P0xx formats. When I checked the definition of DRM_FORMAT_NV12, I am not sure if that's intended for this. Ville, I saw=
that the DRM_FORMAT_NV12 definition was added by you, can you please
comment if this is the right usage ?

Upto Gen10 24-27 bits of PLANE_CTL will be used for = format. ICL onwards 23rd bit
is also used. PLANE_CTL_FORMAT_MASK has been defined in i915_reg.h
and mapping will be same if 23rd bit is 0. For NV12, 1<< 24 thus hold= s good
for all Gen.

That's not my point. What I want to say is, as per b= spec (1 << 24) is for P010/P012/P016 formats, not NV12. NV12 is 8 bit= YCBCR 4:2:0 format whereas P010/012/016 are 10,12 and 16 bit YCBCR 4:2:0 f= ormats. So I was not sure if that should be called NV12 and hence I was not sure if we should return DRM_FORMAT_NV1= 2 for the same.
- Shashank

What I mean to say here is, the check (1 << 24= ) is not good enough for all NV12, as you have to use it as if (mask =3D=3D= YCBCR_420_FORMAT_NV12) not (mask & YCBCR_420_FORMAT_NV12).
But if that's how its intended to be used for future addition of P010/012/0= 16,  then I guess you can bypass this comment, but please make sure yo= u differentiate NV12 with those formats.
- Shashank

 

Sure thank u, will tak= e care when P0xx gets added.

       default:
       case PLANE_CTL_FORMAT_XRGB_8888:
           if (rgb_order)= {

 

 

--_000_F653A0A18852B74D88578FA2EB7094EAB6822890BGSMSX108garcor_-- --===============0354580878== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KSW50ZWwtZ2Z4 IG1haWxpbmcgbGlzdApJbnRlbC1nZnhAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBzOi8vbGlz dHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vaW50ZWwtZ2Z4Cg== --===============0354580878==--