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[77.188.68.61]) by smtp.gmail.com with ESMTPSA id og42-20020a1709071dea00b008e8e9859905sm6149308ejc.184.2023.03.01.12.58.41 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 01 Mar 2023 12:58:41 -0800 (PST) Date: Wed, 01 Mar 2023 20:58:38 +0000 From: Bernhard Beschow To: David Woodhouse , BALATON Zoltan CC: qemu-devel@nongnu.org, qemu-ppc@nongnu.org, Gerd Hoffmann , Daniel Henrique Barboza , Peter Maydell , philmd@linaro.org, ReneEngel80@emailn.de Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v5_5/7=5D_hw/isa/vt82c686=3A_Work_arou?= =?US-ASCII?Q?nd_missing_level_sensitive_irq_in_i8259_model?= In-Reply-To: <859e28fd61203c35e30fce505f0101886a54e654.camel@infradead.org> References: <6502f6bd-029c-25a8-49ec-e61784c64db5@eik.bme.hu> <943866390436e3c8828fea3e8cec117ae8553887.camel@infradead.org> <1c9daa28-b4b0-5227-ea94-90035a8bed7a@eik.bme.hu> <859e28fd61203c35e30fce505f0101886a54e654.camel@infradead.org> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::52d; envelope-from=shentey@gmail.com; helo=mail-ed1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Am 1=2E M=C3=A4rz 2023 14:05:31 UTC schrieb David Woodhouse : >On Wed, 2023-03-01 at 14:18 +0100, BALATON Zoltan wrote: >> > Are you sure the PIC ELCR is actually set for the lines you're having >> > trouble with? Is that something the Pegasos SmartFirmware would have >> > done, and MorphOS is expecting to inherit but isn't actually setting = up >> > for itself? >>=20 >> No, it works with other guests like Linux and AmigaOS that use PIC as s= et=20 >> up by the firmware but MorphOS tries to use it in level sensitive mode = and=20 >> likely has an IRQ handler which expects this to work=2E This is where I= 've=20 >> debugged it and came to this workaround: >>=20 >> https://lists=2Enongnu=2Eorg/archive/html/qemu-ppc/2023-02/msg00403=2Eh= tml >>=20 >> When booting MorphOS with -d unimp I see these logs: >>=20 >> i8259: level sensitive irq not supported >> i8259: level sensitive irq not supported >>=20 >> which is I guess when it tries to set it for both PICs=2E (If you want = to=20 >> try this MorphOS iso is downloadable and instructions how to boot it is= =20 >> here: http://zero=2Eeik=2Ebme=2Ehu/~balaton/qemu/amiga/#morphos > > >Wow=2E Even looking at the PIIX3 datasheet from 1996, That 'Edge/Level >Bank Select (LTIM)' bit was documented as 'This bit is disabled=2E Its >function is replaced by the Edge/Level Triggerede Control (ELCR) >Registers=2E > >We've been able to set the edge/level on a per-pin basis ever since the >ELCR was introduced with the IBM PS/2, I think=2E > >It isn't a *correct* fix without a little bit more typing, but does >this make it work? > >diff --git a/hw/intc/i8259=2Ec b/hw/intc/i8259=2Ec >index 17910f3bcb=2E=2E36ebcff025 100644 >--- a/hw/intc/i8259=2Ec >+++ b/hw/intc/i8259=2Ec >@@ -246,6 +246,7 @@ static void pic_ioport_write(void *opaque, hwaddr add= r64, > if (val & 0x08) { > qemu_log_mask(LOG_UNIMP, > "i8259: level sensitive irq not supported\= n"); >+ s->elcr =3D 0xff; Thanks so much, David! You're a genious=2E=2E=2E Best regards, Bernhard > } > } else if (val & 0x08) { > if (val & 0x04) { > > >