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From: Lamar Hansford <Lamar.Hansford@maxpoint.com>
To: ath9k-devel@lists.ath9k.org
Subject: [ath9k-devel] Interrupt issue on ARM with SMP
Date: Thu, 25 Aug 2016 18:15:42 +0000	[thread overview]
Message-ID: <F9D95AC275991E48901933FBF3337AB0A3315924@ex-02> (raw)
In-Reply-To: <CAJ-VmokwKLJ3s86_UK8nvJ5OziojGzH6vdX+Nvvp3nn6ZyiLQw@mail.gmail.com>

I am using legacy interrupts in this case.  I found the issue where the interrupts were not firing (stupid issue on my part).  Working on getting the data through the pipe.

I still have a question on the meaning for the ASYNC cause.

After receiving and clearing interrupts (writing the ISR back to itself).   I am masking the bits until they are serviced.  When the interrupts are masked I get an async cause of 0x0 and the interrupts are ignored.

Is the AR_INTR_ASYNC_CAUSE indicating that the interrupt has not changed since the last IMR update?

If so this would be odd behavior (normally an IMR will prevent spurious ISR to relieve loading).

Thanks in advance,
-Lamar






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  reply	other threads:[~2016-08-25 18:15 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-08-25  3:50 [ath9k-devel] Interrupt issue on ARM with SMP Lamar Hansford
2016-08-25 15:48 ` Adrian Chadd
2016-08-25 18:15   ` Lamar Hansford [this message]
2016-08-26  1:33     ` Adrian Chadd
2016-08-26 14:35       ` Lamar Hansford
2016-08-28  4:44         ` Adrian Chadd
2016-08-29 15:27           ` Lamar Hansford

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