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From: <Wenyou.Yang@microchip.com>
To: <linux@armlinux.org.uk>, <jjhiblot@gmail.com>
CC: <alexandre.belloni@free-electrons.com>, <mark.rutland@arm.com>,
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Subject: RE: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu
 idle
Thread-Topic: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu
 idle
Thread-Index: AQHSZ+rsMKNieJVdMU6/XbtU2qIHPaEyX9SAgAAJHQCAAIwTYIAApZ+AgAADrYCAAHYTIA==
Date: Thu, 12 Jan 2017 01:25:22 +0000
Message-ID: <F9F4555C4E01D7469D37975B62D0EFBB497F2B@CHN-SV-EXMX07.mchp-main.com>
References: <20170106065947.30631-1-wenyou.yang@atmel.com>
 <20170106065947.30631-2-wenyou.yang@atmel.com>
 <20170110161821.vp673jyfqx6s76pg@piout.net>
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 <CACh+v5M3tU4WHMqAX0zm2H=zzwc0+XChyG1tnH2aHxaacm6C=A@mail.gmail.com>
 <20170111111814.GJ14217@n2100.armlinux.org.uk>
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> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux@armlinux.org.uk]
> Sent: 2017年1月11日 19:18
> To: Jean-Jacques Hiblot <jjhiblot@gmail.com>
> Cc: Wenyou Yang - A41535 <Wenyou.Yang@microchip.com>; Alexandre Belloni
> <alexandre.belloni@free-electrons.com>; Mark Rutland <mark.rutland@arm.com>;
> devicetree <devicetree@vger.kernel.org>; Nicolas Ferre
> <nicolas.ferre@atmel.com>; Linux Kernel Mailing List <linux-
> kernel@vger.kernel.org>; robh+dt <robh+dt@kernel.org>; linux-arm-
> kernel@lists.infradead.org
> Subject: Re: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle
> 
> On Wed, Jan 11, 2017 at 12:05:05PM +0100, Jean-Jacques Hiblot wrote:
> > 2017-01-11 9:15 GMT+01:00  <Wenyou.Yang@microchip.com>:
> > > Hi Jean-Jacques,
> > >
> > >> -----Original Message-----
> > >> From: Jean-Jacques Hiblot [mailto:jjhiblot@gmail.com]
> > >> Sent: 2017年1月11日 0:51
> > >> To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> > >> Cc: Wenyou Yang - A41535 <Wenyou.Yang@microchip.com>; Mark Rutland
> > >> <mark.rutland@arm.com>; devicetree <devicetree@vger.kernel.org>;
> > >> Russell King <linux@arm.linux.org.uk>; Wenyou Yang - A41535
> > >> <Wenyou.Yang@microchip.com>; Nicolas Ferre
> > >> <nicolas.ferre@atmel.com>; Linux Kernel Mailing List
> > >> <linux-kernel@vger.kernel.org>; Rob Herring <robh+dt@kernel.org>;
> > >> linux-arm-kernel@lists.infradead.org
> > >> Subject: Re: [PATCH 1/3] ARM: at91: flush the L2 cache before
> > >> entering cpu idle
> > >>
> > >> 2017-01-10 17:18 GMT+01:00 Alexandre Belloni
> > >> <alexandre.belloni@free-electrons.com>:
> > >> > I though a bit more about it, and I don't really like the new
> > >> > compatible string. I don't feel this should be necessary.
> > >> >
> > >> > What about the following:
> > >> >
> > >> > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> > >> > index
> > >> > b4332b727e9c..0333aca63e44 100644
> > >> > --- a/arch/arm/mach-at91/pm.c
> > >> > +++ b/arch/arm/mach-at91/pm.c
> > >> > @@ -53,6 +53,7 @@ extern void at91_pinctrl_gpio_resume(void);
> > >> > static struct {
> > >> >         unsigned long uhp_udp_mask;
> > >> >         int memctrl;
> > >> > +       bool has_l2_cache;
> > >> >  } at91_pm_data;
> > >> >
> > >> >  void __iomem *at91_ramc_base[2]; @@ -267,6 +268,11 @@ static
> > >> > void at91_ddr_standby(void)
> > >> >         u32 lpr0, lpr1 = 0;
> > >> >         u32 saved_lpr0, saved_lpr1 = 0;
> > >> >
> > >>
> > >> > +       if (at91_pm_data.has_l2_cache) {
> > >> > +               flush_cache_all();
> > >> what is the point of calling flush_cache_all() here ? Do we really
> > >> care that dirty data in L1 is written to DDR ? I may be missing
> > >> something but to me it's just extra latency.
> > >
> > > Are you mean use outer_flush_all() to flush all cache lines in the outer cache
> only?
> >
> > Yes that's what I meant. You see, you don't flush the cache for
> > sama5d3 so it shouldn't be required either for sam5d4. You should be
> > able to test it quickly and see if L1 flush is indeed required by
> > replacing  flush_cache_all() with outer_flush_all(). BTW is highly
> > probable that L2 cache flush is done in outer_disable() so calling
> > outer_flush_all() is probably no required.
> 
> Please don't.  Read the comments in the code, and understand the APIs that
> you're suggesting people use _before_ making the suggestion:
> 
> /**
>  * outer_flush_all - clean and invalidate all cache lines in the outer cache
>  *
>  * Note: depending on implementation, this may not be atomic - it must
>  * only be called with interrupts disabled and no other active outer
>  * cache masters.
>  *
>  * It is intended that this function is only used by implementations
>  * needing to override the outer_cache.disable() method due to security.
>  * (Some implementations perform this as a clean followed by an invalidate.)  */
> 
> So, outer_flush_all() should not be called except from L2 cache code
> implementing the outer_disable() function - it's not intended for platforms to use.
> 
> There are, however, sadly three users of outer_flush_all() which have crept in
> through arm-soc, that should be outer_disable() instead.

Here, outer_flush_all() should not be called, calling outer_disable() is enough. Is it right?

In the implementation of l2c_disable(void) of in mm/cache-l2x0.c, the outer_cache.flush_all() is called.

> 
> --
> RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
> FTTC broadband for 0.8mile line: currently at 9.6Mbps down 400kbps up
> according to speedtest.net.


Best Regards,
Wenyou Yang

From mboxrd@z Thu Jan  1 00:00:00 1970
From: <Wenyou.Yang-UWL1GkI3JZL3oGB3hsPCZA@public.gmane.org>
Subject: RE: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu
 idle
Date: Thu, 12 Jan 2017 01:25:22 +0000
Message-ID: <F9F4555C4E01D7469D37975B62D0EFBB497F2B@CHN-SV-EXMX07.mchp-main.com>
References: <20170106065947.30631-1-wenyou.yang@atmel.com>
 <20170106065947.30631-2-wenyou.yang@atmel.com>
 <20170110161821.vp673jyfqx6s76pg@piout.net>
 <CACh+v5NX9Da__zXtnVGgbO9wYAzEJy-8rjVPHdQx_F6QDk+xZg@mail.gmail.com>
 <F9F4555C4E01D7469D37975B62D0EFBB496BE4@CHN-SV-EXMX07.mchp-main.com>
 <CACh+v5M3tU4WHMqAX0zm2H=zzwc0+XChyG1tnH2aHxaacm6C=A@mail.gmail.com>
 <20170111111814.GJ14217@n2100.armlinux.org.uk>
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DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogUnVzc2VsbCBLaW5nIC0g
QVJNIExpbnV4IFttYWlsdG86bGludXhAYXJtbGludXgub3JnLnVrXQ0KPiBTZW50OiAyMDE35bm0
MeaciDEx5pelIDE5OjE4DQo+IFRvOiBKZWFuLUphY3F1ZXMgSGlibG90IDxqamhpYmxvdEBnbWFp
bC5jb20+DQo+IENjOiBXZW55b3UgWWFuZyAtIEE0MTUzNSA8V2VueW91LllhbmdAbWljcm9jaGlw
LmNvbT47IEFsZXhhbmRyZSBCZWxsb25pDQo+IDxhbGV4YW5kcmUuYmVsbG9uaUBmcmVlLWVsZWN0
cm9ucy5jb20+OyBNYXJrIFJ1dGxhbmQgPG1hcmsucnV0bGFuZEBhcm0uY29tPjsNCj4gZGV2aWNl
dHJlZSA8ZGV2aWNldHJlZUB2Z2VyLmtlcm5lbC5vcmc+OyBOaWNvbGFzIEZlcnJlDQo+IDxuaWNv
bGFzLmZlcnJlQGF0bWVsLmNvbT47IExpbnV4IEtlcm5lbCBNYWlsaW5nIExpc3QgPGxpbnV4LQ0K
PiBrZXJuZWxAdmdlci5rZXJuZWwub3JnPjsgcm9iaCtkdCA8cm9iaCtkdEBrZXJuZWwub3JnPjsg
bGludXgtYXJtLQ0KPiBrZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZw0KPiBTdWJqZWN0OiBSZTog
W1BBVENIIDEvM10gQVJNOiBhdDkxOiBmbHVzaCB0aGUgTDIgY2FjaGUgYmVmb3JlIGVudGVyaW5n
IGNwdSBpZGxlDQo+IA0KPiBPbiBXZWQsIEphbiAxMSwgMjAxNyBhdCAxMjowNTowNVBNICswMTAw
LCBKZWFuLUphY3F1ZXMgSGlibG90IHdyb3RlOg0KPiA+IDIwMTctMDEtMTEgOToxNSBHTVQrMDE6
MDAgIDxXZW55b3UuWWFuZ0BtaWNyb2NoaXAuY29tPjoNCj4gPiA+IEhpIEplYW4tSmFjcXVlcywN
Cj4gPiA+DQo+ID4gPj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gPiA+PiBGcm9tOiBK
ZWFuLUphY3F1ZXMgSGlibG90IFttYWlsdG86ampoaWJsb3RAZ21haWwuY29tXQ0KPiA+ID4+IFNl
bnQ6IDIwMTflubQx5pyIMTHml6UgMDo1MQ0KPiA+ID4+IFRvOiBBbGV4YW5kcmUgQmVsbG9uaSA8
YWxleGFuZHJlLmJlbGxvbmlAZnJlZS1lbGVjdHJvbnMuY29tPg0KPiA+ID4+IENjOiBXZW55b3Ug
WWFuZyAtIEE0MTUzNSA8V2VueW91LllhbmdAbWljcm9jaGlwLmNvbT47IE1hcmsgUnV0bGFuZA0K
PiA+ID4+IDxtYXJrLnJ1dGxhbmRAYXJtLmNvbT47IGRldmljZXRyZWUgPGRldmljZXRyZWVAdmdl
ci5rZXJuZWwub3JnPjsNCj4gPiA+PiBSdXNzZWxsIEtpbmcgPGxpbnV4QGFybS5saW51eC5vcmcu
dWs+OyBXZW55b3UgWWFuZyAtIEE0MTUzNQ0KPiA+ID4+IDxXZW55b3UuWWFuZ0BtaWNyb2NoaXAu
Y29tPjsgTmljb2xhcyBGZXJyZQ0KPiA+ID4+IDxuaWNvbGFzLmZlcnJlQGF0bWVsLmNvbT47IExp
bnV4IEtlcm5lbCBNYWlsaW5nIExpc3QNCj4gPiA+PiA8bGludXgta2VybmVsQHZnZXIua2VybmVs
Lm9yZz47IFJvYiBIZXJyaW5nIDxyb2JoK2R0QGtlcm5lbC5vcmc+Ow0KPiA+ID4+IGxpbnV4LWFy
bS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZw0KPiA+ID4+IFN1YmplY3Q6IFJlOiBbUEFUQ0gg
MS8zXSBBUk06IGF0OTE6IGZsdXNoIHRoZSBMMiBjYWNoZSBiZWZvcmUNCj4gPiA+PiBlbnRlcmlu
ZyBjcHUgaWRsZQ0KPiA+ID4+DQo+ID4gPj4gMjAxNy0wMS0xMCAxNzoxOCBHTVQrMDE6MDAgQWxl
eGFuZHJlIEJlbGxvbmkNCj4gPiA+PiA8YWxleGFuZHJlLmJlbGxvbmlAZnJlZS1lbGVjdHJvbnMu
Y29tPjoNCj4gPiA+PiA+IEkgdGhvdWdoIGEgYml0IG1vcmUgYWJvdXQgaXQsIGFuZCBJIGRvbid0
IHJlYWxseSBsaWtlIHRoZSBuZXcNCj4gPiA+PiA+IGNvbXBhdGlibGUgc3RyaW5nLiBJIGRvbid0
IGZlZWwgdGhpcyBzaG91bGQgYmUgbmVjZXNzYXJ5Lg0KPiA+ID4+ID4NCj4gPiA+PiA+IFdoYXQg
YWJvdXQgdGhlIGZvbGxvd2luZzoNCj4gPiA+PiA+DQo+ID4gPj4gPiBkaWZmIC0tZ2l0IGEvYXJj
aC9hcm0vbWFjaC1hdDkxL3BtLmMgYi9hcmNoL2FybS9tYWNoLWF0OTEvcG0uYw0KPiA+ID4+ID4g
aW5kZXgNCj4gPiA+PiA+IGI0MzMyYjcyN2U5Yy4uMDMzM2FjYTYzZTQ0IDEwMDY0NA0KPiA+ID4+
ID4gLS0tIGEvYXJjaC9hcm0vbWFjaC1hdDkxL3BtLmMNCj4gPiA+PiA+ICsrKyBiL2FyY2gvYXJt
L21hY2gtYXQ5MS9wbS5jDQo+ID4gPj4gPiBAQCAtNTMsNiArNTMsNyBAQCBleHRlcm4gdm9pZCBh
dDkxX3BpbmN0cmxfZ3Bpb19yZXN1bWUodm9pZCk7DQo+ID4gPj4gPiBzdGF0aWMgc3RydWN0IHsN
Cj4gPiA+PiA+ICAgICAgICAgdW5zaWduZWQgbG9uZyB1aHBfdWRwX21hc2s7DQo+ID4gPj4gPiAg
ICAgICAgIGludCBtZW1jdHJsOw0KPiA+ID4+ID4gKyAgICAgICBib29sIGhhc19sMl9jYWNoZTsN
Cj4gPiA+PiA+ICB9IGF0OTFfcG1fZGF0YTsNCj4gPiA+PiA+DQo+ID4gPj4gPiAgdm9pZCBfX2lv
bWVtICphdDkxX3JhbWNfYmFzZVsyXTsgQEAgLTI2Nyw2ICsyNjgsMTEgQEAgc3RhdGljDQo+ID4g
Pj4gPiB2b2lkIGF0OTFfZGRyX3N0YW5kYnkodm9pZCkNCj4gPiA+PiA+ICAgICAgICAgdTMyIGxw
cjAsIGxwcjEgPSAwOw0KPiA+ID4+ID4gICAgICAgICB1MzIgc2F2ZWRfbHByMCwgc2F2ZWRfbHBy
MSA9IDA7DQo+ID4gPj4gPg0KPiA+ID4+DQo+ID4gPj4gPiArICAgICAgIGlmIChhdDkxX3BtX2Rh
dGEuaGFzX2wyX2NhY2hlKSB7DQo+ID4gPj4gPiArICAgICAgICAgICAgICAgZmx1c2hfY2FjaGVf
YWxsKCk7DQo+ID4gPj4gd2hhdCBpcyB0aGUgcG9pbnQgb2YgY2FsbGluZyBmbHVzaF9jYWNoZV9h
bGwoKSBoZXJlID8gRG8gd2UgcmVhbGx5DQo+ID4gPj4gY2FyZSB0aGF0IGRpcnR5IGRhdGEgaW4g
TDEgaXMgd3JpdHRlbiB0byBERFIgPyBJIG1heSBiZSBtaXNzaW5nDQo+ID4gPj4gc29tZXRoaW5n
IGJ1dCB0byBtZSBpdCdzIGp1c3QgZXh0cmEgbGF0ZW5jeS4NCj4gPiA+DQo+ID4gPiBBcmUgeW91
IG1lYW4gdXNlIG91dGVyX2ZsdXNoX2FsbCgpIHRvIGZsdXNoIGFsbCBjYWNoZSBsaW5lcyBpbiB0
aGUgb3V0ZXIgY2FjaGUNCj4gb25seT8NCj4gPg0KPiA+IFllcyB0aGF0J3Mgd2hhdCBJIG1lYW50
LiBZb3Ugc2VlLCB5b3UgZG9uJ3QgZmx1c2ggdGhlIGNhY2hlIGZvcg0KPiA+IHNhbWE1ZDMgc28g
aXQgc2hvdWxkbid0IGJlIHJlcXVpcmVkIGVpdGhlciBmb3Igc2FtNWQ0LiBZb3Ugc2hvdWxkIGJl
DQo+ID4gYWJsZSB0byB0ZXN0IGl0IHF1aWNrbHkgYW5kIHNlZSBpZiBMMSBmbHVzaCBpcyBpbmRl
ZWQgcmVxdWlyZWQgYnkNCj4gPiByZXBsYWNpbmcgIGZsdXNoX2NhY2hlX2FsbCgpIHdpdGggb3V0
ZXJfZmx1c2hfYWxsKCkuIEJUVyBpcyBoaWdobHkNCj4gPiBwcm9iYWJsZSB0aGF0IEwyIGNhY2hl
IGZsdXNoIGlzIGRvbmUgaW4gb3V0ZXJfZGlzYWJsZSgpIHNvIGNhbGxpbmcNCj4gPiBvdXRlcl9m
bHVzaF9hbGwoKSBpcyBwcm9iYWJseSBubyByZXF1aXJlZC4NCj4gDQo+IFBsZWFzZSBkb24ndC4g
IFJlYWQgdGhlIGNvbW1lbnRzIGluIHRoZSBjb2RlLCBhbmQgdW5kZXJzdGFuZCB0aGUgQVBJcyB0
aGF0DQo+IHlvdSdyZSBzdWdnZXN0aW5nIHBlb3BsZSB1c2UgX2JlZm9yZV8gbWFraW5nIHRoZSBz
dWdnZXN0aW9uOg0KPiANCj4gLyoqDQo+ICAqIG91dGVyX2ZsdXNoX2FsbCAtIGNsZWFuIGFuZCBp
bnZhbGlkYXRlIGFsbCBjYWNoZSBsaW5lcyBpbiB0aGUgb3V0ZXIgY2FjaGUNCj4gICoNCj4gICog
Tm90ZTogZGVwZW5kaW5nIG9uIGltcGxlbWVudGF0aW9uLCB0aGlzIG1heSBub3QgYmUgYXRvbWlj
IC0gaXQgbXVzdA0KPiAgKiBvbmx5IGJlIGNhbGxlZCB3aXRoIGludGVycnVwdHMgZGlzYWJsZWQg
YW5kIG5vIG90aGVyIGFjdGl2ZSBvdXRlcg0KPiAgKiBjYWNoZSBtYXN0ZXJzLg0KPiAgKg0KPiAg
KiBJdCBpcyBpbnRlbmRlZCB0aGF0IHRoaXMgZnVuY3Rpb24gaXMgb25seSB1c2VkIGJ5IGltcGxl
bWVudGF0aW9ucw0KPiAgKiBuZWVkaW5nIHRvIG92ZXJyaWRlIHRoZSBvdXRlcl9jYWNoZS5kaXNh
YmxlKCkgbWV0aG9kIGR1ZSB0byBzZWN1cml0eS4NCj4gICogKFNvbWUgaW1wbGVtZW50YXRpb25z
IHBlcmZvcm0gdGhpcyBhcyBhIGNsZWFuIGZvbGxvd2VkIGJ5IGFuIGludmFsaWRhdGUuKSAgKi8N
Cj4gDQo+IFNvLCBvdXRlcl9mbHVzaF9hbGwoKSBzaG91bGQgbm90IGJlIGNhbGxlZCBleGNlcHQg
ZnJvbSBMMiBjYWNoZSBjb2RlDQo+IGltcGxlbWVudGluZyB0aGUgb3V0ZXJfZGlzYWJsZSgpIGZ1
bmN0aW9uIC0gaXQncyBub3QgaW50ZW5kZWQgZm9yIHBsYXRmb3JtcyB0byB1c2UuDQo+IA0KPiBU
aGVyZSBhcmUsIGhvd2V2ZXIsIHNhZGx5IHRocmVlIHVzZXJzIG9mIG91dGVyX2ZsdXNoX2FsbCgp
IHdoaWNoIGhhdmUgY3JlcHQgaW4NCj4gdGhyb3VnaCBhcm0tc29jLCB0aGF0IHNob3VsZCBiZSBv
dXRlcl9kaXNhYmxlKCkgaW5zdGVhZC4NCg0KSGVyZSwgb3V0ZXJfZmx1c2hfYWxsKCkgc2hvdWxk
IG5vdCBiZSBjYWxsZWQsIGNhbGxpbmcgb3V0ZXJfZGlzYWJsZSgpIGlzIGVub3VnaC4gSXMgaXQg
cmlnaHQ/DQoNCkluIHRoZSBpbXBsZW1lbnRhdGlvbiBvZiBsMmNfZGlzYWJsZSh2b2lkKSBvZiBp
biBtbS9jYWNoZS1sMngwLmMsIHRoZSBvdXRlcl9jYWNoZS5mbHVzaF9hbGwoKSBpcyBjYWxsZWQu
DQoNCj4gDQo+IC0tDQo+IFJNSydzIFBhdGNoIHN5c3RlbTogaHR0cDovL3d3dy5hcm1saW51eC5v
cmcudWsvZGV2ZWxvcGVyL3BhdGNoZXMvDQo+IEZUVEMgYnJvYWRiYW5kIGZvciAwLjhtaWxlIGxp
bmU6IGN1cnJlbnRseSBhdCA5LjZNYnBzIGRvd24gNDAwa2JwcyB1cA0KPiBhY2NvcmRpbmcgdG8g
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From mboxrd@z Thu Jan  1 00:00:00 1970
From: Wenyou.Yang@microchip.com (Wenyou.Yang at microchip.com)
Date: Thu, 12 Jan 2017 01:25:22 +0000
Subject: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle
In-Reply-To: <20170111111814.GJ14217@n2100.armlinux.org.uk>
References: <20170106065947.30631-1-wenyou.yang@atmel.com>
 <20170106065947.30631-2-wenyou.yang@atmel.com>
 <20170110161821.vp673jyfqx6s76pg@piout.net>
 <CACh+v5NX9Da__zXtnVGgbO9wYAzEJy-8rjVPHdQx_F6QDk+xZg@mail.gmail.com>
 <F9F4555C4E01D7469D37975B62D0EFBB496BE4@CHN-SV-EXMX07.mchp-main.com>
 <CACh+v5M3tU4WHMqAX0zm2H=zzwc0+XChyG1tnH2aHxaacm6C=A@mail.gmail.com>
 <20170111111814.GJ14217@n2100.armlinux.org.uk>
Message-ID: <F9F4555C4E01D7469D37975B62D0EFBB497F2B@CHN-SV-EXMX07.mchp-main.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org



> -----Original Message-----
> From: Russell King - ARM Linux [mailto:linux at armlinux.org.uk]
> Sent: 2017?1?11? 19:18
> To: Jean-Jacques Hiblot <jjhiblot@gmail.com>
> Cc: Wenyou Yang - A41535 <Wenyou.Yang@microchip.com>; Alexandre Belloni
> <alexandre.belloni@free-electrons.com>; Mark Rutland <mark.rutland@arm.com>;
> devicetree <devicetree@vger.kernel.org>; Nicolas Ferre
> <nicolas.ferre@atmel.com>; Linux Kernel Mailing List <linux-
> kernel at vger.kernel.org>; robh+dt <robh+dt@kernel.org>; linux-arm-
> kernel at lists.infradead.org
> Subject: Re: [PATCH 1/3] ARM: at91: flush the L2 cache before entering cpu idle
> 
> On Wed, Jan 11, 2017 at 12:05:05PM +0100, Jean-Jacques Hiblot wrote:
> > 2017-01-11 9:15 GMT+01:00  <Wenyou.Yang@microchip.com>:
> > > Hi Jean-Jacques,
> > >
> > >> -----Original Message-----
> > >> From: Jean-Jacques Hiblot [mailto:jjhiblot at gmail.com]
> > >> Sent: 2017?1?11? 0:51
> > >> To: Alexandre Belloni <alexandre.belloni@free-electrons.com>
> > >> Cc: Wenyou Yang - A41535 <Wenyou.Yang@microchip.com>; Mark Rutland
> > >> <mark.rutland@arm.com>; devicetree <devicetree@vger.kernel.org>;
> > >> Russell King <linux@arm.linux.org.uk>; Wenyou Yang - A41535
> > >> <Wenyou.Yang@microchip.com>; Nicolas Ferre
> > >> <nicolas.ferre@atmel.com>; Linux Kernel Mailing List
> > >> <linux-kernel@vger.kernel.org>; Rob Herring <robh+dt@kernel.org>;
> > >> linux-arm-kernel at lists.infradead.org
> > >> Subject: Re: [PATCH 1/3] ARM: at91: flush the L2 cache before
> > >> entering cpu idle
> > >>
> > >> 2017-01-10 17:18 GMT+01:00 Alexandre Belloni
> > >> <alexandre.belloni@free-electrons.com>:
> > >> > I though a bit more about it, and I don't really like the new
> > >> > compatible string. I don't feel this should be necessary.
> > >> >
> > >> > What about the following:
> > >> >
> > >> > diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
> > >> > index
> > >> > b4332b727e9c..0333aca63e44 100644
> > >> > --- a/arch/arm/mach-at91/pm.c
> > >> > +++ b/arch/arm/mach-at91/pm.c
> > >> > @@ -53,6 +53,7 @@ extern void at91_pinctrl_gpio_resume(void);
> > >> > static struct {
> > >> >         unsigned long uhp_udp_mask;
> > >> >         int memctrl;
> > >> > +       bool has_l2_cache;
> > >> >  } at91_pm_data;
> > >> >
> > >> >  void __iomem *at91_ramc_base[2]; @@ -267,6 +268,11 @@ static
> > >> > void at91_ddr_standby(void)
> > >> >         u32 lpr0, lpr1 = 0;
> > >> >         u32 saved_lpr0, saved_lpr1 = 0;
> > >> >
> > >>
> > >> > +       if (at91_pm_data.has_l2_cache) {
> > >> > +               flush_cache_all();
> > >> what is the point of calling flush_cache_all() here ? Do we really
> > >> care that dirty data in L1 is written to DDR ? I may be missing
> > >> something but to me it's just extra latency.
> > >
> > > Are you mean use outer_flush_all() to flush all cache lines in the outer cache
> only?
> >
> > Yes that's what I meant. You see, you don't flush the cache for
> > sama5d3 so it shouldn't be required either for sam5d4. You should be
> > able to test it quickly and see if L1 flush is indeed required by
> > replacing  flush_cache_all() with outer_flush_all(). BTW is highly
> > probable that L2 cache flush is done in outer_disable() so calling
> > outer_flush_all() is probably no required.
> 
> Please don't.  Read the comments in the code, and understand the APIs that
> you're suggesting people use _before_ making the suggestion:
> 
> /**
>  * outer_flush_all - clean and invalidate all cache lines in the outer cache
>  *
>  * Note: depending on implementation, this may not be atomic - it must
>  * only be called with interrupts disabled and no other active outer
>  * cache masters.
>  *
>  * It is intended that this function is only used by implementations
>  * needing to override the outer_cache.disable() method due to security.
>  * (Some implementations perform this as a clean followed by an invalidate.)  */
> 
> So, outer_flush_all() should not be called except from L2 cache code
> implementing the outer_disable() function - it's not intended for platforms to use.
> 
> There are, however, sadly three users of outer_flush_all() which have crept in
> through arm-soc, that should be outer_disable() instead.

Here, outer_flush_all() should not be called, calling outer_disable() is enough. Is it right?

In the implementation of l2c_disable(void) of in mm/cache-l2x0.c, the outer_cache.flush_all() is called.

> 
> --
> RMK's Patch system: http://www.armlinux.org.uk/developer/patches/
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Best Regards,
Wenyou Yang