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[77.11.174.6]) by smtp.gmail.com with ESMTPSA id o24-20020a170906769800b00726abf9a32bsm930212ejm.138.2022.07.09.13.51.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sat, 09 Jul 2022 13:51:25 -0700 (PDT) Date: Sat, 09 Jul 2022 20:51:22 +0000 From: B To: qemu-devel@nongnu.org, Joao Martins CC: Igor Mammedov , Eduardo Habkost , "Michael S. Tsirkin" , Richard Henderson , Alex Williamson , Paolo Bonzini , Ani Sinha , Marcel Apfelbaum , "Dr. David Alan Gilbert" , Suravee Suthikulpanit Subject: =?US-ASCII?Q?Re=3A_=5BPATCH_v6_03/10=5D_i386/pc=3A_pass_?= =?US-ASCII?Q?pci=5Fhole64=5Fsize_to_pc=5Fmemory=5Finit=28=29?= In-Reply-To: <20220701161014.3850-4-joao.m.martins@oracle.com> References: <20220701161014.3850-1-joao.m.martins@oracle.com> <20220701161014.3850-4-joao.m.martins@oracle.com> Message-ID: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=shentey@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Am 1=2E Juli 2022 16:10:07 UTC schrieb Joao Martins : >Use the pre-initialized pci-host qdev and fetch the >pci-hole64-size into pc_memory_init() newly added argument=2E >piix needs a bit of care given all the !pci_enabled() >and that the pci_hole64_size is private to i440fx=2E It exposes this value as the property PCI_HOST_PROP_PCI_HOLE64_SIZE=2E Reu= sing it allows for not touching i440fx in this patch at all=2E For code symmetry reasons the analogue property could be used for Q35 as w= ell=2E Best regards, Bernhard > >This is in preparation to determine that host-phys-bits are >enough and for pci-hole64-size to be considered to relocate >ram-above-4g to be at 1T (on AMD platforms)=2E > >Signed-off-by: Joao Martins >Reviewed-by: Igor Mammedov >--- > hw/i386/pc=2Ec | 3 ++- > hw/i386/pc_piix=2Ec | 5 ++++- > hw/i386/pc_q35=2Ec | 8 +++++++- > hw/pci-host/i440fx=2Ec | 7 +++++++ > include/hw/i386/pc=2Eh | 3 ++- > include/hw/pci-host/i440fx=2Eh | 1 + > 6 files changed, 23 insertions(+), 4 deletions(-) > >diff --git a/hw/i386/pc=2Ec b/hw/i386/pc=2Ec >index a9d1bf95649a=2E=2E1bb89a9c17ec 100644 >--- a/hw/i386/pc=2Ec >+++ b/hw/i386/pc=2Ec >@@ -817,7 +817,8 @@ void xen_load_linux(PCMachineState *pcms) > void pc_memory_init(PCMachineState *pcms, > MemoryRegion *system_memory, > MemoryRegion *rom_memory, >- MemoryRegion **ram_memory) >+ MemoryRegion **ram_memory, >+ uint64_t pci_hole64_size) > { > int linux_boot, i; > MemoryRegion *option_rom_mr; >diff --git a/hw/i386/pc_piix=2Ec b/hw/i386/pc_piix=2Ec >index 6186a1473755=2E=2Ef3c726e42400 100644 >--- a/hw/i386/pc_piix=2Ec >+++ b/hw/i386/pc_piix=2Ec >@@ -91,6 +91,7 @@ static void pc_init1(MachineState *machine, > MemoryRegion *pci_memory; > MemoryRegion *rom_memory; > ram_addr_t lowmem; >+ uint64_t hole64_size; > DeviceState *i440fx_host; >=20 > /* >@@ -166,10 +167,12 @@ static void pc_init1(MachineState *machine, > memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); > rom_memory =3D pci_memory; > i440fx_host =3D qdev_new(host_type); >+ hole64_size =3D i440fx_pci_hole64_size(i440fx_host); > } else { > pci_memory =3D NULL; > rom_memory =3D system_memory; > i440fx_host =3D NULL; >+ hole64_size =3D 0; > } >=20 > pc_guest_info_init(pcms); >@@ -186,7 +189,7 @@ static void pc_init1(MachineState *machine, > /* allocate ram and load rom/bios */ > if (!xen_enabled()) { > pc_memory_init(pcms, system_memory, >- rom_memory, &ram_memory); >+ rom_memory, &ram_memory, hole64_size); > } else { > pc_system_flash_cleanup_unused(pcms); > if (machine->kernel_filename !=3D NULL) { >diff --git a/hw/i386/pc_q35=2Ec b/hw/i386/pc_q35=2Ec >index 46ea89e564de=2E=2E5a4a737fe203 100644 >--- a/hw/i386/pc_q35=2Ec >+++ b/hw/i386/pc_q35=2Ec >@@ -138,6 +138,7 @@ static void pc_q35_init(MachineState *machine) > MachineClass *mc =3D MACHINE_GET_CLASS(machine); > bool acpi_pcihp; > bool keep_pci_slot_hpc; >+ uint64_t pci_hole64_size =3D 0; >=20 > /* Check whether RAM fits below 4G (leaving 1/2 GByte for IO memory > * and 256 Mbytes for PCI Express Enhanced Configuration Access Mapp= ing >@@ -206,8 +207,13 @@ static void pc_q35_init(MachineState *machine) > /* create pci host bus */ > q35_host =3D Q35_HOST_DEVICE(qdev_new(TYPE_Q35_HOST_DEVICE)); >=20 >+ if (pcmc->pci_enabled) { >+ pci_hole64_size =3D q35_host->mch=2Epci_hole64_size; >+ } >+ > /* allocate ram and load rom/bios */ >- pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory); >+ pc_memory_init(pcms, get_system_memory(), rom_memory, &ram_memory, >+ pci_hole64_size); >=20 > object_property_add_child(qdev_get_machine(), "q35", OBJECT(q35_host= )); > object_property_set_link(OBJECT(q35_host), MCH_HOST_PROP_RAM_MEM, >diff --git a/hw/pci-host/i440fx=2Ec b/hw/pci-host/i440fx=2Ec >index d5426ef4a53c=2E=2E15680da7d709 100644 >--- a/hw/pci-host/i440fx=2Ec >+++ b/hw/pci-host/i440fx=2Ec >@@ -237,6 +237,13 @@ static void i440fx_realize(PCIDevice *dev, Error **e= rrp) > } > } >=20 >+uint64_t i440fx_pci_hole64_size(DeviceState *i440fx_dev) >+{ >+ I440FXState *i440fx =3D I440FX_PCI_HOST_BRIDGE(i440fx_dev); >+ >+ return i440fx->pci_hole64_size; >+} >+ > PCIBus *i440fx_init(const char *pci_type, > DeviceState *dev, > MemoryRegion *address_space_mem, >diff --git a/include/hw/i386/pc=2Eh b/include/hw/i386/pc=2Eh >index b7735dccfc81=2E=2E568c226d3034 100644 >--- a/include/hw/i386/pc=2Eh >+++ b/include/hw/i386/pc=2Eh >@@ -159,7 +159,8 @@ void xen_load_linux(PCMachineState *pcms); > void pc_memory_init(PCMachineState *pcms, > MemoryRegion *system_memory, > MemoryRegion *rom_memory, >- MemoryRegion **ram_memory); >+ MemoryRegion **ram_memory, >+ uint64_t pci_hole64_size); > uint64_t pc_pci_hole64_start(void); > DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); > void pc_basic_device_init(struct PCMachineState *pcms, >diff --git a/include/hw/pci-host/i440fx=2Eh b/include/hw/pci-host/i440fx= =2Eh >index d02bf1ed6b93=2E=2E2234dd5a2a6a 100644 >--- a/include/hw/pci-host/i440fx=2Eh >+++ b/include/hw/pci-host/i440fx=2Eh >@@ -45,5 +45,6 @@ PCIBus *i440fx_init(const char *pci_type, > MemoryRegion *pci_memory, > MemoryRegion *ram_memory); >=20 >+uint64_t i440fx_pci_hole64_size(DeviceState *i440fx_dev); >=20 > #endif