[PATCH 00/92] IIO: Fix alignment of buffers for DMA

[PATCH 00/92] IIO: Fix alignment of buffers for DMA

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Many years ago, IIO started using ____cacheline_aligned to ensure
that buffers that might be used for DMA were not sharing a cacheline
with other data that might lead to DMA safety issues.

As it turns out, that was fine at the time, but not based on the
correct alignment requirement (though I believe it was a conservative
choice at the time).  Note that on many architectures this was introducing
unecessary padding.  We should have been using ARCH_KMALLOC_MINALIGN
as other subsystems such as crypto have done for a long time.

Patch 1 discription contains more information but in short, there are
ARM64 SoCs out their that have a larger cachline size for caches beyond
L1. In many cases they maintain coherency for all DMA devices attached
and so this isn't a problem, but there are exceptions that do not.

So, this is a rather large patch set and just covers those drivers
that are in the last kernel release and in drivers/iio.

Many of these drivers are somewhat old so I haven't specifically
cc'd anyone so will be relying on those kind enough to sanity check
patches on drivers that are beyond their own.

Given there is ongoing discussion around reducing the alignment
requirements where possible, I've adopted the existing IIO_ALIGN
define througout.  That way we have a single point to update if
that becomes relevant in future.

Cc: catalin.marinas@arm.com

Jonathan Cameron (92):
  iio: core: Fix IIO_ALIGN as it was not sufficiently large on some
    platforms.
  iio: accel: adxl313: Fix alignment for DMA safety
  iio: accel: adxl355: Fix alignment for DMA safety
  iio: accel: adxl367: Fix alignment for DMA safety
  iio: accel: bma220: Fix alignment for DMA safety
  iio: accel: bmi088: Fix alignment for DMA safety
  iio: accel: sca3000: Fix alignment for DMA safety
  iio: accel: sca3000: Fix alignment for DMA safety
  iio: adc: ad7266: Fix alignment for DMA safety
  iio: adc: ad7280a: Fix alignment for DMA safety
  iio: adc: ad7292: Fix alignment for DMA safety
  iio: adc: ad7298: Fix alignment for DMA safety
  iio: adc: ad7476: Fix alignment for DMA safety
  iio: adc: ad7606: Fix alignment for DMA safety
  iio: adc: ad7766: Fix alignment for DMA safety
  iio: adc: ad7768-1: Fix alignment for DMA safety
  iio: adc: ad7887: Fix alignment for DMA safety
  iio: adc: ad7923: Fix alignment for DMA safety
  iio: adc: ad7949: Fix alignment for DMA safety
  iio: adc: hi8435: Fix alignment for DMA safety
  iio: adc: ltc2496: Fix alignment for DMA safety
  iio: adc: ltc2497: Fix alignment for DMA safety
  iio: adc: max1027: Fix alignment for DMA safety
  iio: adc: max11100: Fix alignment for DMA safety
  iio: adc: max1118: Fix alignment for DMA safety
  iio: adc: max1241: Fix alignment for DMA safety
  iio: adc: mcp320x: Fix alignment for DMA safety
  iio: adc: ti-adc0832: Fix alignment for DMA safety
  iio: adc: ti-adc084s021: Fix alignment for DMA safety
  iio: adc: ti-adc108s102: Fix alignment for DMA safety
  iio: adc: ti-adc12138: Fix alignment for DMA safety
  iio: adc: ti-adc128s052: Fix alignment for DMA safety
  iio: adc: ti-adc161s626: Fix alignment for DMA safety
  iio: adc: ti-ads124s08: Fix alignment for DMA safety
  iio: adc: ti-ads131e08: Fix alignment for DMA safety
  iio: adc: ti-ads7950: Fix alignment for DMA safety
  iio: adc: ti-ads8344: Fix alignment for DMA safety
  iio: adc: ti-ads8688: Fix alignment for DMA safety
  iio: adc: ti-tlc4541: Fix alignment for DMA safety
  iio: addac: ad74413r: Fix alignment for DMA safety
  iio: amplifiers: ad8366: Fix alignment for DMA safety
  iio: common: ssp: Fix alignment for DMA safety
  iio: dac: ad5064: Fix alignment for DMA safety
  iio: dac: ad5360: Fix alignment for DMA safety
  iio: dac: ad5421: Fix alignment for DMA safety
  iio: dac: ad5449: Fix alignment for DMA safety
  iio: dac: ad5504: Fix alignment for DMA safety
  iio: dac: ad5592r: Fix alignment for DMA safety
  iio: dac: ad5686: Fix alignment for DMA safety
  iio: dac: ad5755: Fix alignment for DMA safety
  iio: dac: ad5761: Fix alignment for DMA safety
  iio: dac: ad5764: Fix alignment for DMA safety
  iio: dac: ad5766: Fix alignment for DMA safety
  iio: dac: ad5770r: Fix alignment for DMA safety
  iio: dac: ad5791: Fix alignment for DMA saftey
  iio: dac: ad7293: Fix alignment for DMA safety
  iio: dac: ad7303: Fix alignment for DMA safety
  iio: dac: ad8801: Fix alignment for DMA safety
  iio: dac: ltc2688: Fix alignment for DMA safety
  iio: dac: mcp3922: Fix alignment for DMA safety
  iio: dac: ti-dac082s085: Fix alignment for DMA safety
  iio: dac: ti-dac5571: Fix alignment for DMA safety
  iio: dac: ti-dac7311: Fix alignment for DMA safety
  iio: dac: ti-dac7612: Fix alignment for DMA safety
  iio: frequency: ad9523: Fix alignment for DMA safety
  iio: frequency: adf4350: Fix alignment for DMA safety
  iio: frequency: adf4371: Fix alignment for DMA safety
  iio: frequency: admv1013: Fix alignment for DMA safety
  iio: frequency: admv1014: Fix alignment for DMA safety
  iio: frequency: admv4420: Fix alignment for DMA safety
  iio: frequency: adrf6780: Fix alignment for DMA safety
  iio: gyro: adis16080: Fix alignment for DMA safety
  iio: gyro: adis16130: Fix alignment for DMA safety
  iio: gyro: adxrs450: Fix alignment for DMA safety
  iio: gyro: fxas210002c: Fix alignment for DMA safety
  iio: imu: fxos8700: Fix alignment for DMA safety
  iio: imu_icm42600: Fix alignment for DMA safety
  iio: imu: icm42600: Fix alignment for DMA safety in buffer code.
  iio: imu: mpu6050: Fix alignment for DMA safety
  iio: potentiometer: ad5110: Fix alignment for DMA safety
  iio: potentiometer: ad5272: Fix alignment for DMA safety
  iio: potentiometer: max5481: Fix alignment for DMA safety
  iio: potentiometer: mcp41010: Fix alignment for DMA safety
  iio: potentiometer: mcp4131: Fix alignment for DMA safety
  iio: pressure: dlhl60d: Drop unnecessary alignment forcing.
  iio: proximity: as3935: Fix alignment for DMA safety
  iio: proximity: vcnl3020: Drop unnecessary alignment requirement for
    i2c device
  iio: resolver: ad2s1200: Fix alignment for DMA safety
  iio: resolver: ad2s90: Fix alignment for DMA safety
  iio: temp: ltc2983: Fix alignment for DMA safety
  iio: temp: max31865: Fix alignment for DMA safety
  iio: temp: maxim_thermocouple: Fix alignment for DMA safety

 drivers/iio/accel/adxl313_core.c                   |  2 +-
 drivers/iio/accel/adxl355_core.c                   |  2 +-
 drivers/iio/accel/adxl367.c                        |  2 +-
 drivers/iio/accel/adxl367_spi.c                    |  8 +++++---
 drivers/iio/accel/bma220_spi.c                     |  2 +-
 drivers/iio/accel/bmi088-accel-core.c              |  2 +-
 drivers/iio/accel/sca3000.c                        |  4 ++--
 drivers/iio/accel/sca3300.c                        |  2 +-
 drivers/iio/adc/ad7266.c                           |  6 +++---
 drivers/iio/adc/ad7280a.c                          |  2 +-
 drivers/iio/adc/ad7292.c                           |  2 +-
 drivers/iio/adc/ad7298.c                           |  2 +-
 drivers/iio/adc/ad7476.c                           |  5 ++---
 drivers/iio/adc/ad7606.h                           |  6 +++---
 drivers/iio/adc/ad7766.c                           |  5 ++---
 drivers/iio/adc/ad7768-1.c                         |  4 ++--
 drivers/iio/adc/ad7887.c                           |  5 ++---
 drivers/iio/adc/ad7923.c                           |  4 ++--
 drivers/iio/adc/ad7949.c                           |  2 +-
 drivers/iio/adc/hi8435.c                           |  2 +-
 drivers/iio/adc/ltc2496.c                          |  4 ++--
 drivers/iio/adc/ltc2497.c                          |  4 ++--
 drivers/iio/adc/max1027.c                          |  2 +-
 drivers/iio/adc/max11100.c                         |  4 ++--
 drivers/iio/adc/max1118.c                          |  2 +-
 drivers/iio/adc/max1241.c                          |  2 +-
 drivers/iio/adc/mcp320x.c                          |  2 +-
 drivers/iio/adc/ti-adc0832.c                       |  2 +-
 drivers/iio/adc/ti-adc084s021.c                    |  4 ++--
 drivers/iio/adc/ti-adc108s102.c                    |  4 ++--
 drivers/iio/adc/ti-adc12138.c                      |  2 +-
 drivers/iio/adc/ti-adc128s052.c                    |  2 +-
 drivers/iio/adc/ti-adc161s626.c                    |  2 +-
 drivers/iio/adc/ti-ads124s08.c                     |  2 +-
 drivers/iio/adc/ti-ads131e08.c                     |  2 +-
 drivers/iio/adc/ti-ads7950.c                       |  4 ++--
 drivers/iio/adc/ti-ads8344.c                       |  2 +-
 drivers/iio/adc/ti-ads8688.c                       |  2 +-
 drivers/iio/adc/ti-tlc4541.c                       |  4 ++--
 drivers/iio/addac/ad74413r.c                       |  4 ++--
 drivers/iio/amplifiers/ad8366.c                    |  4 ++--
 drivers/iio/common/ssp_sensors/ssp.h               |  3 +--
 drivers/iio/dac/ad5064.c                           |  4 ++--
 drivers/iio/dac/ad5360.c                           |  4 ++--
 drivers/iio/dac/ad5421.c                           |  4 ++--
 drivers/iio/dac/ad5449.c                           |  4 ++--
 drivers/iio/dac/ad5504.c                           |  2 +-
 drivers/iio/dac/ad5592r-base.h                     |  4 +++-
 drivers/iio/dac/ad5686.h                           |  6 ++++--
 drivers/iio/dac/ad5755.c                           |  4 ++--
 drivers/iio/dac/ad5761.c                           |  4 ++--
 drivers/iio/dac/ad5764.c                           |  4 ++--
 drivers/iio/dac/ad5766.c                           |  2 +-
 drivers/iio/dac/ad5770r.c                          |  2 +-
 drivers/iio/dac/ad5791.c                           |  2 +-
 drivers/iio/dac/ad7293.c                           |  2 +-
 drivers/iio/dac/ad7303.c                           |  4 ++--
 drivers/iio/dac/ad8801.c                           |  2 +-
 drivers/iio/dac/ltc2688.c                          |  4 ++--
 drivers/iio/dac/mcp4922.c                          |  2 +-
 drivers/iio/dac/ti-dac082s085.c                    |  2 +-
 drivers/iio/dac/ti-dac5571.c                       |  2 +-
 drivers/iio/dac/ti-dac7311.c                       |  2 +-
 drivers/iio/dac/ti-dac7612.c                       |  4 ++--
 drivers/iio/frequency/ad9523.c                     |  6 +++---
 drivers/iio/frequency/adf4350.c                    |  6 +++---
 drivers/iio/frequency/adf4371.c                    |  2 +-
 drivers/iio/frequency/admv1013.c                   |  2 +-
 drivers/iio/frequency/admv1014.c                   |  2 +-
 drivers/iio/frequency/admv4420.c                   |  2 +-
 drivers/iio/frequency/adrf6780.c                   |  2 +-
 drivers/iio/gyro/adis16080.c                       |  2 +-
 drivers/iio/gyro/adis16130.c                       |  2 +-
 drivers/iio/gyro/adxrs450.c                        |  2 +-
 drivers/iio/gyro/fxas21002c_core.c                 |  6 +++---
 drivers/iio/imu/fxos8700_core.c                    |  2 +-
 drivers/iio/imu/inv_icm42600/inv_icm42600.h        |  2 +-
 drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h |  2 +-
 drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h          |  2 +-
 drivers/iio/potentiometer/ad5110.c                 |  6 +++---
 drivers/iio/potentiometer/ad5272.c                 |  2 +-
 drivers/iio/potentiometer/max5481.c                |  2 +-
 drivers/iio/potentiometer/mcp41010.c               |  2 +-
 drivers/iio/potentiometer/mcp4131.c                |  2 +-
 drivers/iio/pressure/dlhl60d.c                     |  2 +-
 drivers/iio/proximity/as3935.c                     |  2 +-
 drivers/iio/proximity/vcnl3020.c                   |  4 ++--
 drivers/iio/resolver/ad2s1200.c                    |  2 +-
 drivers/iio/resolver/ad2s90.c                      |  2 +-
 drivers/iio/temperature/ltc2983.c                  |  6 +++---
 drivers/iio/temperature/max31865.c                 |  2 +-
 drivers/iio/temperature/maxim_thermocouple.c       |  2 +-
 include/linux/iio/iio.h                            | 10 ++++++++--
 93 files changed, 149 insertions(+), 141 deletions(-)

-- 
2.36.0

[PATCH 01/92] iio: core: Fix IIO_ALIGN as it was not sufficiently large on some platforms.

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Discussion of the series:
https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/
mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that
our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm
platforms out their with non coherent DMA and larger cache lines at
at higher levels of their cache hierarchy.

Note this patch will greatly reduce the padding on some architectures
that have smaller requirements for DMA safe buffers.

The history of changing values of ARCH_KMALLOC_MINALIGN via
ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this
as fixing a particular patch from that route as it's not clear what to tag.

Most recently a change to bring them back inline was reverted because
of some Qualcomm Kryo cores with an L2 cache with 128-byte lines
sitting above the point of coherency.

c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)"
That reverts:
65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which
refers to the change originally being motivated by Thunder x1 performance
rather than correctness.

Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data space to iio_allocate_device")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 include/linux/iio/iio.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h
index faf00f2c0be6..30937f8f9424 100644
--- a/include/linux/iio/iio.h
+++ b/include/linux/iio/iio.h
@@ -9,6 +9,7 @@
 
 #include <linux/device.h>
 #include <linux/cdev.h>
+#include <linux/slab.h>
 #include <linux/iio/types.h>
 #include <linux/of.h>
 /* IIO TODO LIST */
@@ -657,8 +658,13 @@ static inline void *iio_device_get_drvdata(const struct iio_dev *indio_dev)
 	return dev_get_drvdata(&indio_dev->dev);
 }
 
-/* Can we make this smaller? */
-#define IIO_ALIGN L1_CACHE_BYTES
+/*
+ * Used to ensure the iio_priv() structure is aligned to allow that structure
+ * to in turn include IIO_ALIGN'd elements such as buffers which must not share
+ * cachelines with the rest of the structure, thus making them safe for use with
+ * non-coherent DMA.
+ */
+#define IIO_ALIGN ARCH_KMALLOC_MINALIGN
 struct iio_dev *iio_device_alloc(struct device *parent, int sizeof_priv);
 
 /* The information at the returned address is guaranteed to be cacheline aligned */
-- 
2.36.0

[PATCH 02/92] iio: accel: adxl313: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the update IIO_ALIGN definition.

Fixes: 636d44633039 ("iio: accel: Add driver support for ADXL313")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/adxl313_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/accel/adxl313_core.c b/drivers/iio/accel/adxl313_core.c
index 9e4193e64765..508fccbd4347 100644
--- a/drivers/iio/accel/adxl313_core.c
+++ b/drivers/iio/accel/adxl313_core.c
@@ -46,7 +46,7 @@ EXPORT_SYMBOL_NS_GPL(adxl313_writable_regs_table, IIO_ADXL313);
 struct adxl313_data {
 	struct regmap	*regmap;
 	struct mutex	lock; /* lock to protect transf_buf */
-	__le16		transf_buf ____cacheline_aligned;
+	__le16		transf_buf __aligned(IIO_ALIGN);
 };
 
 static const int adxl313_odr_freqs[][2] = {
-- 
2.36.0

[PATCH 03/92] iio: accel: adxl355: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

 ____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_ALIGN definition.

Fixes: 327a0eaf19d53 ("iio: accel: adxl355: Add triggered buffer support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Puranjay Mohan <puranjay12@gmail.com>
---
 drivers/iio/accel/adxl355_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/accel/adxl355_core.c b/drivers/iio/accel/adxl355_core.c
index e9c10c8c32f0..50513db39ee8 100644
--- a/drivers/iio/accel/adxl355_core.c
+++ b/drivers/iio/accel/adxl355_core.c
@@ -177,7 +177,7 @@ struct adxl355_data {
 			u8 buf[14];
 			s64 ts;
 		} buffer;
-	} ____cacheline_aligned;
+	} __aligned(IIO_ALIGN);
 };
 
 static int adxl355_set_op_mode(struct adxl355_data *data,
-- 
2.36.0

[PATCH 04/92] iio: accel: adxl367: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_ALIGN definition.

Update comment to reflect that DMA safety may require separate
cachelines.

Fixes: cbab791c5e2a5 ("iio: accel: add ADXL367 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <demonsingur@gmail.com>
---
 drivers/iio/accel/adxl367.c     | 2 +-
 drivers/iio/accel/adxl367_spi.c | 8 +++++---
 2 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/drivers/iio/accel/adxl367.c b/drivers/iio/accel/adxl367.c
index 62960134ea19..9b933c5715c3 100644
--- a/drivers/iio/accel/adxl367.c
+++ b/drivers/iio/accel/adxl367.c
@@ -179,7 +179,7 @@ struct adxl367_state {
 	unsigned int	fifo_set_size;
 	unsigned int	fifo_watermark;
 
-	__be16		fifo_buf[ADXL367_FIFO_SIZE] ____cacheline_aligned;
+	__be16		fifo_buf[ADXL367_FIFO_SIZE] __aligned(IIO_ALIGN);
 	__be16		sample_buf;
 	u8		act_threshold_buf[2];
 	u8		inact_time_buf[2];
diff --git a/drivers/iio/accel/adxl367_spi.c b/drivers/iio/accel/adxl367_spi.c
index 26dfc821ebbe..872b1c5a2cc5 100644
--- a/drivers/iio/accel/adxl367_spi.c
+++ b/drivers/iio/accel/adxl367_spi.c
@@ -9,6 +9,8 @@
 #include <linux/regmap.h>
 #include <linux/spi/spi.h>
 
+#include <linux/iio/iio.h>
+
 #include "adxl367.h"
 
 #define ADXL367_SPI_WRITE_COMMAND	0x0A
@@ -28,10 +30,10 @@ struct adxl367_spi_state {
 	struct spi_transfer	fifo_xfer[2];
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
-	 * transfer buffers to live in their own cache lines.
+	 * DMA (thus cache coherency maintenance) may require the
+	 * transfer buffers live in their own cache lines.
 	 */
-	u8			reg_write_tx_buf[1] ____cacheline_aligned;
+	u8			reg_write_tx_buf[1] __aligned(IIO_ALIGN);
 	u8			reg_read_tx_buf[2];
 	u8			fifo_tx_buf[1];
 };
-- 
2.36.0

[PATCH 05/92] iio: accel: bma220: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_ALIGN definition.

Fixes: bf2a5600a3ebc ("iio: accel: Add support for Bosch BMA220")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/bma220_spi.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/accel/bma220_spi.c b/drivers/iio/accel/bma220_spi.c
index 74024d7ce5ac..219731393be4 100644
--- a/drivers/iio/accel/bma220_spi.c
+++ b/drivers/iio/accel/bma220_spi.c
@@ -67,7 +67,7 @@ struct bma220_data {
 		/* Ensure timestamp is naturally aligned. */
 		s64 timestamp __aligned(8);
 	} scan;
-	u8 tx_buf[2] ____cacheline_aligned;
+	u8 tx_buf[2] __aligned(IIO_ALIGN);
 };
 
 static const struct iio_chan_spec bma220_channels[] = {
-- 
2.36.0

[PATCH 06/92] iio: accel: bmi088: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_ALIGN definition.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/bmi088-accel-core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/accel/bmi088-accel-core.c b/drivers/iio/accel/bmi088-accel-core.c
index 8b2728bbcade..bde5bfd08118 100644
--- a/drivers/iio/accel/bmi088-accel-core.c
+++ b/drivers/iio/accel/bmi088-accel-core.c
@@ -124,7 +124,7 @@ struct bmi088_accel_chip_info {
 struct bmi088_accel_data {
 	struct regmap *regmap;
 	const struct bmi088_accel_chip_info *chip_info;
-	u8 buffer[2] ____cacheline_aligned; /* shared DMA safe buffer */
+	u8 buffer[2] __aligned(IIO_ALIGN); /* shared DMA safe buffer */
 };
 
 static const struct regmap_range bmi088_volatile_ranges[] = {
-- 
2.36.0

[PATCH 07/92] iio: accel: sca3000: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_ALIGN definition.

Fixes: ced5c03d360ae ("staging:iio:accel:sca3000 merge files into one.")
Fixes: 152a6a884ae13 ("staging:iio:accel:sca3000 move to hybrid hard / soft buffer design.")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/accel/sca3000.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/accel/sca3000.c b/drivers/iio/accel/sca3000.c
index 83c81072511e..a8897b684210 100644
--- a/drivers/iio/accel/sca3000.c
+++ b/drivers/iio/accel/sca3000.c
@@ -167,8 +167,8 @@ struct sca3000_state {
 	int				mo_det_use_count;
 	struct mutex			lock;
 	/* Can these share a cacheline ? */
-	u8				rx[384] ____cacheline_aligned;
-	u8				tx[6] ____cacheline_aligned;
+	u8				rx[384] __aligned(IIO_ALIGN);
+	u8				tx[6] __aligned(IIO_ALIGN);
 };
 
 /**
-- 
2.36.0

[PATCH 08/92] iio: accel: sca3000: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is insufficient guarantee for non-coherent DMA.
Switch to the updated IIO_ALIGN definition.

Fixes: 9cc9806e22178 ("iio: accel: Add driver for Murata SCA3300 accelerometer")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Tomas Melin <tomas.melin@vaisala.com>
---
 drivers/iio/accel/sca3300.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/accel/sca3300.c b/drivers/iio/accel/sca3300.c
index f7ef8ecfd34a..0e87746829a4 100644
--- a/drivers/iio/accel/sca3300.c
+++ b/drivers/iio/accel/sca3300.c
@@ -115,7 +115,7 @@ struct sca3300_data {
 		s16 channels[4];
 		s64 ts __aligned(sizeof(s64));
 	} scan;
-	u8 txbuf[4] ____cacheline_aligned;
+	u8 txbuf[4] __aligned(IIO_ALIGN);
 	u8 rxbuf[4];
 };
 
-- 
2.36.0

[PATCH 09/92] iio: adc: ad7266: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to reflect that DMA safety 'may' require separate
cachelines.

Fixes: 54e018da3141 ("iio:ad7266: Mark transfer buffer as __be16")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ad7266.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/adc/ad7266.c b/drivers/iio/adc/ad7266.c
index c17d9b5fbaf6..54fdb8fbb6a2 100644
--- a/drivers/iio/adc/ad7266.c
+++ b/drivers/iio/adc/ad7266.c
@@ -37,15 +37,15 @@ struct ad7266_state {
 	struct gpio_desc	*gpios[3];
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
-	 * transfer buffers to live in their own cache lines.
+	 * DMA (thus cache coherency maintenance) may require the
+	 * transfer buffers live in their own cache lines.
 	 * The buffer needs to be large enough to hold two samples (4 bytes) and
 	 * the naturally aligned timestamp (8 bytes).
 	 */
 	struct {
 		__be16 sample[2];
 		s64 timestamp;
-	} data ____cacheline_aligned;
+	} data __aligned(IIO_ALIGN);
 };
 
 static int ad7266_wakeup(struct ad7266_state *st)
-- 
2.36.0

[PATCH 10/92] iio: adc: ad7280a: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 003f1d48de52 ("staging:iio:adc:ad7280a: Split buff[2] into tx and rx parts")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ad7280a.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ad7280a.c b/drivers/iio/adc/ad7280a.c
index ec9acbf12b9a..74173e54b254 100644
--- a/drivers/iio/adc/ad7280a.c
+++ b/drivers/iio/adc/ad7280a.c
@@ -183,7 +183,7 @@ struct ad7280_state {
 	unsigned char			cb_mask[AD7280A_MAX_CHAIN];
 	struct mutex			lock; /* protect sensor state */
 
-	__be32				tx ____cacheline_aligned;
+	__be32				tx __aligned(IIO_ALIGN);
 	__be32				rx;
 };
 
-- 
2.36.0

[PATCH 11/92] iio: adc: ad7292: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 506d2e317a0a ("iio: adc: Add driver support for AD7292")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Marcelo Schmitt <marcelo.schmitt1@gmail.com>
---
 drivers/iio/adc/ad7292.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ad7292.c b/drivers/iio/adc/ad7292.c
index 3271a31afde1..08985fc5c200 100644
--- a/drivers/iio/adc/ad7292.c
+++ b/drivers/iio/adc/ad7292.c
@@ -80,7 +80,7 @@ struct ad7292_state {
 	struct regulator *reg;
 	unsigned short vref_mv;
 
-	__be16 d16 ____cacheline_aligned;
+	__be16 d16 __aligned(IIO_ALIGN);
 	u8 d8[2];
 };
 
-- 
2.36.0

[PATCH 12/92] iio: adc: ad7298: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: be7fd3b86ad2 ("iio:adc:ad7298 make the tx and rx buffers __be16")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ad7298.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ad7298.c b/drivers/iio/adc/ad7298.c
index 3f4e73f7d35a..3461321effae 100644
--- a/drivers/iio/adc/ad7298.c
+++ b/drivers/iio/adc/ad7298.c
@@ -49,7 +49,7 @@ struct ad7298_state {
 	 * DMA (thus cache coherency maintenance) requires the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	__be16				rx_buf[12] ____cacheline_aligned;
+	__be16				rx_buf[12] __aligned(IIO_ALIGN);
 	__be16				tx_buf[2];
 };
 
-- 
2.36.0

[PATCH 13/92] iio: adc: ad7476: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

 ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to reflect that DMA safety 'may' require separate
cachelines.

Fixes tag is unlikely to be the actual introdution of the problem but is
far enough back to cover any likely backporting.

Fixes: 7a28fe3c93d6 ("staging:iio:ad7476: Squash driver into a single file.")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ad7476.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/adc/ad7476.c b/drivers/iio/adc/ad7476.c
index a1e8b32671cf..d02b1c801957 100644
--- a/drivers/iio/adc/ad7476.c
+++ b/drivers/iio/adc/ad7476.c
@@ -44,13 +44,12 @@ struct ad7476_state {
 	struct spi_transfer		xfer;
 	struct spi_message		msg;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 * Make the buffer large enough for one 16 bit sample and one 64 bit
 	 * aligned 64 bit timestamp.
 	 */
-	unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)]
-			____cacheline_aligned;
+	unsigned char data[ALIGN(2, sizeof(s64)) + sizeof(s64)] __aligned(IIO_ALIGN);
 };
 
 enum ad7476_supported_device_ids {
-- 
2.36.0

[PATCH 14/92] iio: adc: ad7606: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to reflect the fact DMA safety 'may' require
separate cachelines.

Fixes: 7989b4bb23fe ("iio: adc: ad7616: Add support for AD7616 ADC")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ad7606.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h
index 4f82d7c9acfd..f52aedb1ecf3 100644
--- a/drivers/iio/adc/ad7606.h
+++ b/drivers/iio/adc/ad7606.h
@@ -116,11 +116,11 @@ struct ad7606_state {
 	struct completion		completion;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
-	 * transfer buffers to live in their own cache lines.
+	 * DMA (thus cache coherency maintenance) may require the
+	 * transfer buffers live in their own cache lines.
 	 * 16 * 16-bit samples + 64-bit timestamp
 	 */
-	unsigned short			data[20] ____cacheline_aligned;
+	unsigned short			data[20] __aligned(IIO_ALIGN);
 	__be16				d16[2];
 };
 
-- 
2.36.0

[PATCH 15/92] iio: adc: ad7766: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to reflect the fact DMA safety 'may' require
separate cachelines.

Fixes: aa16c6bd0e09 ("iio:adc: Add support for AD7766/AD7767")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/iio/adc/ad7766.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/adc/ad7766.c b/drivers/iio/adc/ad7766.c
index 51ee9482e0df..f26115967bed 100644
--- a/drivers/iio/adc/ad7766.c
+++ b/drivers/iio/adc/ad7766.c
@@ -45,13 +45,12 @@ struct ad7766 {
 	struct spi_message msg;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 * Make the buffer large enough for one 24 bit sample and one 64 bit
 	 * aligned 64 bit timestamp.
 	 */
-	unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)]
-			____cacheline_aligned;
+	unsigned char data[ALIGN(3, sizeof(s64)) + sizeof(s64)]	__aligned(IIO_ALIGN);
 };
 
 /*
-- 
2.36.0

[PATCH 16/92] iio: adc: ad7768-1: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to reflect that separate cachelines 'may' be
required.

Fixes: a5f8c7da3dbe ("iio: adc: Add AD7768-1 ADC basic support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ad7768-1.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ad7768-1.c b/drivers/iio/adc/ad7768-1.c
index aa42ba759fa1..325d3aba5abb 100644
--- a/drivers/iio/adc/ad7768-1.c
+++ b/drivers/iio/adc/ad7768-1.c
@@ -163,7 +163,7 @@ struct ad7768_state {
 	struct gpio_desc *gpio_sync_in;
 	const char *labels[ARRAY_SIZE(ad7768_channels)];
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 	union {
@@ -173,7 +173,7 @@ struct ad7768_state {
 		} scan;
 		__be32 d32;
 		u8 d8[2];
-	} data ____cacheline_aligned;
+	} data __aligned(IIO_ALIGN);
 };
 
 static int ad7768_spi_reg_read(struct ad7768_state *st, unsigned int addr,
-- 
2.36.0

[PATCH 17/92] iio: adc: ad7887: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes tag is clearly not where this was introduced but it is very unlikely
anyone will back port it past that point.

Fixes: 65dd3d3d7a9b ("staging:iio:ad7887: Squash everything into one file")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/iio/adc/ad7887.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/adc/ad7887.c b/drivers/iio/adc/ad7887.c
index f64999714a4d..17b20d2085f9 100644
--- a/drivers/iio/adc/ad7887.c
+++ b/drivers/iio/adc/ad7887.c
@@ -66,13 +66,12 @@ struct ad7887_state {
 	unsigned char			tx_cmd_buf[4];
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 * Buffer needs to be large enough to hold two 16 bit samples and a
 	 * 64 bit aligned 64 bit timestamp.
 	 */
-	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)]
-		____cacheline_aligned;
+	unsigned char data[ALIGN(4, sizeof(s64)) + sizeof(s64)] __aligned(IIO_ALIGN);
 };
 
 enum ad7887_supported_device_ids {
-- 
2.36.0

[PATCH 18/92] iio: adc: ad7923: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Note that some other fixes have applied to this line of code
that may complicate automated backporting.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Fixes: 0eac259db28f ("IIO ADC support for AD7923")
---
 drivers/iio/adc/ad7923.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ad7923.c b/drivers/iio/adc/ad7923.c
index 069b561ee768..596244bccd20 100644
--- a/drivers/iio/adc/ad7923.c
+++ b/drivers/iio/adc/ad7923.c
@@ -57,12 +57,12 @@ struct ad7923_state {
 	unsigned int			settings;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 * Ensure rx_buf can be directly used in iio_push_to_buffers_with_timetamp
 	 * Length = 8 channels + 4 extra for 8 byte timestamp
 	 */
-	__be16				rx_buf[12] ____cacheline_aligned;
+	__be16				rx_buf[12] __aligned(IIO_ALIGN);
 	__be16				tx_buf[4];
 };
 
-- 
2.36.0

[PATCH 19/92] iio: adc: ad7949: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Note the fixes tag predates some changes to this line of code so
automated application of this fix may fail.

Fixes: 7f40e0614317 ("iio:adc:ad7949: Add AD7949 ADC driver family")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Charles-Antoine Couret <charles-antoine.couret@essensium.com>
---
 drivers/iio/adc/ad7949.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ad7949.c b/drivers/iio/adc/ad7949.c
index 44bb5fde83de..7906f6c6409e 100644
--- a/drivers/iio/adc/ad7949.c
+++ b/drivers/iio/adc/ad7949.c
@@ -86,7 +86,7 @@ struct ad7949_adc_chip {
 	u8 resolution;
 	u16 cfg;
 	unsigned int current_channel;
-	u16 buffer ____cacheline_aligned;
+	u16 buffer __aligned(IIO_ALIGN);
 	__be16 buf8b;
 };
 
-- 
2.36.0

[PATCH 20/92] iio: adc: hi8435: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 72aa29ce0a59 ("iio: adc: hi8435: Holt HI-8435 threshold detector")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/hi8435.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/hi8435.c b/drivers/iio/adc/hi8435.c
index 8eb0140df133..2a96a185b1db 100644
--- a/drivers/iio/adc/hi8435.c
+++ b/drivers/iio/adc/hi8435.c
@@ -49,7 +49,7 @@ struct hi8435_priv {
 
 	unsigned threshold_lo[2]; /* GND-Open and Supply-Open thresholds */
 	unsigned threshold_hi[2]; /* GND-Open and Supply-Open thresholds */
-	u8 reg_buffer[3] ____cacheline_aligned;
+	u8 reg_buffer[3] __aligned(IIO_ALIGN);
 };
 
 static int hi8435_readb(struct hi8435_priv *priv, u8 reg, u8 *val)
-- 
2.36.0

[PATCH 21/92] iio: adc: ltc2496: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: e4c5c4dfaa88 ("iio: adc: new driver to support Linear technology's ltc2496")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
---
 drivers/iio/adc/ltc2496.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ltc2496.c b/drivers/iio/adc/ltc2496.c
index 5a55f79f2574..db1e14224ff9 100644
--- a/drivers/iio/adc/ltc2496.c
+++ b/drivers/iio/adc/ltc2496.c
@@ -24,10 +24,10 @@ struct ltc2496_driverdata {
 	struct spi_device *spi;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	unsigned char rxbuf[3] ____cacheline_aligned;
+	unsigned char rxbuf[3] __aligned(IIO_ALIGN);
 	unsigned char txbuf[3];
 };
 
-- 
2.36.0

[PATCH 22/92] iio: adc: ltc2497: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: bc82222fcca1 ("iio:adc: Driver for Linear Technology LTC2497 ADC")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Michael Hennerich <michael.hennerich@analog.com>
---
 drivers/iio/adc/ltc2497.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ltc2497.c b/drivers/iio/adc/ltc2497.c
index 1adddf5a88a9..8c78bee16369 100644
--- a/drivers/iio/adc/ltc2497.c
+++ b/drivers/iio/adc/ltc2497.c
@@ -20,10 +20,10 @@ struct ltc2497_driverdata {
 	struct ltc2497core_driverdata common_ddata;
 	struct i2c_client *client;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	__be32 buf ____cacheline_aligned;
+	__be32 buf __aligned(IIO_ALIGN);
 };
 
 static int ltc2497_result_and_measure(struct ltc2497core_driverdata *ddata,
-- 
2.36.0

[PATCH 23/92] iio: adc: max1027: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: fc167f624833 ("iio: add support of the max1027")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/max1027.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/max1027.c b/drivers/iio/adc/max1027.c
index 4daf1d576c4e..f79fe49d69b7 100644
--- a/drivers/iio/adc/max1027.c
+++ b/drivers/iio/adc/max1027.c
@@ -272,7 +272,7 @@ struct max1027_state {
 	struct mutex			lock;
 	struct completion		complete;
 
-	u8				reg ____cacheline_aligned;
+	u8				reg __aligned(IIO_ALIGN);
 };
 
 static int max1027_wait_eoc(struct iio_dev *indio_dev)
-- 
2.36.0

[PATCH 24/92] iio: adc: max11100: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: a8e7e88df9ec ("iio: adc: Add Maxim MAX11100 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Jacopo Mondi <jacopo+renesas@jmondi.org>
---
 drivers/iio/adc/max11100.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/max11100.c b/drivers/iio/adc/max11100.c
index eb1ce6a0315c..4766d45344f7 100644
--- a/drivers/iio/adc/max11100.c
+++ b/drivers/iio/adc/max11100.c
@@ -33,10 +33,10 @@ struct max11100_state {
 	struct spi_device *spi;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	u8 buffer[3] ____cacheline_aligned;
+	u8 buffer[3] __aligned(IIO_ALIGN);
 };
 
 static const struct iio_chan_spec max11100_channels[] = {
-- 
2.36.0

[PATCH 25/92] iio: adc: max1118: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: a9e9c7153e96 ("iio: adc: add max1117/max1118/max1119 ADC driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Akinobu Mita <akinobu.mita@gmail.com>
---
 drivers/iio/adc/max1118.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/max1118.c b/drivers/iio/adc/max1118.c
index a41bc570be21..6520acaa6938 100644
--- a/drivers/iio/adc/max1118.c
+++ b/drivers/iio/adc/max1118.c
@@ -42,7 +42,7 @@ struct max1118 {
 		s64 ts __aligned(8);
 	} scan;
 
-	u8 data ____cacheline_aligned;
+	u8 data __aligned(IIO_ALIGN);
 };
 
 #define MAX1118_CHANNEL(ch)						\
-- 
2.36.0

[PATCH 26/92] iio: adc: max1241: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 8a80a71d9020 ("iio: adc: Add MAX1241 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Alexandru Lazar <alazar@startmail.com>
---
 drivers/iio/adc/max1241.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/max1241.c b/drivers/iio/adc/max1241.c
index a5afd84af58b..e3dbcc2e4e77 100644
--- a/drivers/iio/adc/max1241.c
+++ b/drivers/iio/adc/max1241.c
@@ -26,7 +26,7 @@ struct max1241 {
 	struct regulator *vref;
 	struct gpio_desc *shutdown;
 
-	__be16 data ____cacheline_aligned;
+	__be16 data __aligned(IIO_ALIGN);
 };
 
 static const struct iio_chan_spec max1241_channels[] = {
-- 
2.36.0

[PATCH 27/92] iio: adc: mcp320x: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Worth noting the fixes tag refers to the same issue being observed
on a platform that probably had only 64 byte cachelines.

Fixes: 0e81bc99a082 ("iio: mcp320x: Fix occasional incorrect readings")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Michael Welling <mwelling@ieee.org>
---
 drivers/iio/adc/mcp320x.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/mcp320x.c b/drivers/iio/adc/mcp320x.c
index b4c69acb33e3..bd3ef543cc5d 100644
--- a/drivers/iio/adc/mcp320x.c
+++ b/drivers/iio/adc/mcp320x.c
@@ -92,7 +92,7 @@ struct mcp320x {
 	struct mutex lock;
 	const struct mcp320x_chip_info *chip_info;
 
-	u8 tx_buf ____cacheline_aligned;
+	u8 tx_buf __aligned(IIO_ALIGN);
 	u8 rx_buf[4];
 };
 
-- 
2.36.0

[PATCH 28/92] iio: adc: ti-adc0832: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: efc945fb729c ("iio: adc: add support for ADC0831/ADC0832/ADC0834/ADC0838 chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Akinobu Mita <akinobu.mita@gmail.com>
---
 drivers/iio/adc/ti-adc0832.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-adc0832.c b/drivers/iio/adc/ti-adc0832.c
index fb5e72600b96..0a18e63e70cd 100644
--- a/drivers/iio/adc/ti-adc0832.c
+++ b/drivers/iio/adc/ti-adc0832.c
@@ -36,7 +36,7 @@ struct adc0832 {
 	 */
 	u8 data[24] __aligned(8);
 
-	u8 tx_buf[2] ____cacheline_aligned;
+	u8 tx_buf[2] __aligned(IIO_ALIGN);
 	u8 rx_buf[2];
 };
 
-- 
2.36.0

[PATCH 29/92] iio: adc: ti-adc084s021: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 3691e5a69449 ("iio: adc: add driver for the ti-adc084s021 chip")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Mårten Lindahl <martenli@axis.com>
---
 drivers/iio/adc/ti-adc084s021.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ti-adc084s021.c b/drivers/iio/adc/ti-adc084s021.c
index c9b5d9aec3dc..6464541319af 100644
--- a/drivers/iio/adc/ti-adc084s021.c
+++ b/drivers/iio/adc/ti-adc084s021.c
@@ -32,10 +32,10 @@ struct adc084s021 {
 		s64 ts __aligned(8);
 	} scan;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache line.
 	 */
-	u16 tx_buf[4] ____cacheline_aligned;
+	u16 tx_buf[4] __aligned(IIO_ALIGN);
 	__be16 rx_buf[5]; /* First 16-bits are trash */
 };
 
-- 
2.36.0

[PATCH 30/92] iio: adc: ti-adc108s102: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Dual fixes tags as two cases that were introduced in different patches.
One of those patches is a fix however and likely to have been backported
to stable kernels.

Fixes: 3691e5a69449 ("iio: adc: add driver for the ti-adc084s021 chip")
Fixes: cbe5c6977604 ("iio: adc: ti-adc108s102: Fix alignment of buffer pushed to iio buffers.")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ti-adc108s102.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ti-adc108s102.c b/drivers/iio/adc/ti-adc108s102.c
index c8e48881c37f..4307d87d5400 100644
--- a/drivers/iio/adc/ti-adc108s102.c
+++ b/drivers/iio/adc/ti-adc108s102.c
@@ -77,8 +77,8 @@ struct adc108s102_state {
 	 *  tx_buf: 8 channel read commands, plus 1 dummy command
 	 *  rx_buf: 1 dummy response, 8 channel responses
 	 */
-	__be16				rx_buf[9] ____cacheline_aligned;
-	__be16				tx_buf[9] ____cacheline_aligned;
+	__be16				rx_buf[9] __aligned(IIO_ALIGN);
+	__be16				tx_buf[9] __aligned(IIO_ALIGN);
 };
 
 #define ADC108S102_V_CHAN(index)					\
-- 
2.36.0

[PATCH 31/92] iio: adc: ti-adc12138: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 50a6edb1b6e0 ("iio: adc: add ADC12130/ADC12132/ADC12138 ADC driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Akinobu Mita <akinobu.mita@gmail.com>
---
 drivers/iio/adc/ti-adc12138.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-adc12138.c b/drivers/iio/adc/ti-adc12138.c
index 59d75d09604f..f93eaa7e6143 100644
--- a/drivers/iio/adc/ti-adc12138.c
+++ b/drivers/iio/adc/ti-adc12138.c
@@ -55,7 +55,7 @@ struct adc12138 {
 	 */
 	__be16 data[20] __aligned(8);
 
-	u8 tx_buf[2] ____cacheline_aligned;
+	u8 tx_buf[2] __aligned(IIO_ALIGN);
 	u8 rx_buf[2];
 };
 
-- 
2.36.0

[PATCH 32/92] iio: adc: ti-adc128s052: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 913b86468674 ("iio: adc: Add TI ADC128S052")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ti-adc128s052.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-adc128s052.c b/drivers/iio/adc/ti-adc128s052.c
index 8e7adec87755..db4fd0ea7692 100644
--- a/drivers/iio/adc/ti-adc128s052.c
+++ b/drivers/iio/adc/ti-adc128s052.c
@@ -29,7 +29,7 @@ struct adc128 {
 	struct regulator *reg;
 	struct mutex lock;
 
-	u8 buffer[2] ____cacheline_aligned;
+	u8 buffer[2] __aligned(IIO_ALIGN);
 };
 
 static int adc128_adc_conversion(struct adc128 *adc, u8 channel)
-- 
2.36.0

[PATCH 33/92] iio: adc: ti-adc161s626: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 4d671b71beef ("iio: adc: ti-adc161s626: add support for TI 1-channel differential ADCs")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Matt Ranostay <mranostay@gmail.com>
---
 drivers/iio/adc/ti-adc161s626.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-adc161s626.c b/drivers/iio/adc/ti-adc161s626.c
index 75ca7f1c8726..c422da519004 100644
--- a/drivers/iio/adc/ti-adc161s626.c
+++ b/drivers/iio/adc/ti-adc161s626.c
@@ -71,7 +71,7 @@ struct ti_adc_data {
 	u8 read_size;
 	u8 shift;
 
-	u8 buffer[16] ____cacheline_aligned;
+	u8 buffer[16] __aligned(IIO_ALIGN);
 };
 
 static int ti_adc_read_measurement(struct ti_adc_data *data,
-- 
2.36.0

[PATCH 34/92] iio: adc: ti-ads124s08: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: e717f8c6dfec ("iio: adc: Add the TI ads124s08 ADC code")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ti-ads124s08.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-ads124s08.c b/drivers/iio/adc/ti-ads124s08.c
index 767b3b634809..b05d98c50c1e 100644
--- a/drivers/iio/adc/ti-ads124s08.c
+++ b/drivers/iio/adc/ti-ads124s08.c
@@ -106,7 +106,7 @@ struct ads124s_private {
 	 * timestamp is maintained.
 	 */
 	u32 buffer[ADS124S08_MAX_CHANNELS + sizeof(s64)/sizeof(u32)] __aligned(8);
-	u8 data[5] ____cacheline_aligned;
+	u8 data[5] __aligned(IIO_ALIGN);
 };
 
 #define ADS124S08_CHAN(index)					\
-- 
2.36.0

[PATCH 35/92] iio: adc: ti-ads131e08: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: d935eddd2799 ("iio: adc: Add driver for Texas Instruments ADS131E0x ADC family")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Tomislav Denis <tomislav.denis@avl.com>
---
 drivers/iio/adc/ti-ads131e08.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-ads131e08.c b/drivers/iio/adc/ti-ads131e08.c
index 0c2025a22575..fb490471ffb9 100644
--- a/drivers/iio/adc/ti-ads131e08.c
+++ b/drivers/iio/adc/ti-ads131e08.c
@@ -105,7 +105,7 @@ struct ads131e08_state {
 		s64 ts __aligned(8);
 	} tmp_buf;
 
-	u8 tx_buf[3] ____cacheline_aligned;
+	u8 tx_buf[3] __aligned(IIO_ALIGN);
 	/*
 	 * Add extra one padding byte to be able to access the last channel
 	 * value using u32 pointer
-- 
2.36.0

[PATCH 36/92] iio: adc: ti-ads7950: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 902c4b2446d4 ("iio: adc: New driver for TI ADS7950 chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: David Lechner <david@lechnology.com>
---
 drivers/iio/adc/ti-ads7950.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ti-ads7950.c b/drivers/iio/adc/ti-ads7950.c
index e3658b969c5b..a1337469d0f2 100644
--- a/drivers/iio/adc/ti-ads7950.c
+++ b/drivers/iio/adc/ti-ads7950.c
@@ -102,11 +102,11 @@ struct ti_ads7950_state {
 	unsigned int		gpio_cmd_settings_bitmask;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 	u16 rx_buf[TI_ADS7950_MAX_CHAN + 2 + TI_ADS7950_TIMESTAMP_SIZE]
-							____cacheline_aligned;
+		__aligned(IIO_ALIGN);
 	u16 tx_buf[TI_ADS7950_MAX_CHAN + 2];
 	u16 single_tx;
 	u16 single_rx;
-- 
2.36.0

[PATCH 37/92] iio: adc: ti-ads8344: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 8dd2d7c0fed7 ("iio: adc: Add driver for the TI ADS8344 A/DC chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ti-ads8344.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-ads8344.c b/drivers/iio/adc/ti-ads8344.c
index c96d2a9ba924..6d182d5f7805 100644
--- a/drivers/iio/adc/ti-ads8344.c
+++ b/drivers/iio/adc/ti-ads8344.c
@@ -28,7 +28,7 @@ struct ads8344 {
 	 */
 	struct mutex lock;
 
-	u8 tx_buf ____cacheline_aligned;
+	u8 tx_buf __aligned(IIO_ALIGN);
 	u8 rx_buf[3];
 };
 
-- 
2.36.0

[PATCH 38/92] iio: adc: ti-ads8688: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 3e87e7838328 ("iio: adc: Add TI ADS8688")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ti-ads8688.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/adc/ti-ads8688.c b/drivers/iio/adc/ti-ads8688.c
index 22c2583eedd0..3ed422331dc3 100644
--- a/drivers/iio/adc/ti-ads8688.c
+++ b/drivers/iio/adc/ti-ads8688.c
@@ -71,7 +71,7 @@ struct ads8688_state {
 	union {
 		__be32 d32;
 		u8 d8[4];
-	} data[2] ____cacheline_aligned;
+	} data[2] __aligned(IIO_ALIGN);
 };
 
 enum ads8688_id {
-- 
2.36.0

[PATCH 39/92] iio: adc: ti-tlc4541: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: ac2bec9d587c ("iio: adc: tlc4541: add support for TI tlc4541 adc")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/adc/ti-tlc4541.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/adc/ti-tlc4541.c b/drivers/iio/adc/ti-tlc4541.c
index 2406eda9dfc6..b418fc47dc8f 100644
--- a/drivers/iio/adc/ti-tlc4541.c
+++ b/drivers/iio/adc/ti-tlc4541.c
@@ -37,12 +37,12 @@ struct tlc4541_state {
 	struct spi_message              scan_single_msg;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 * 2 bytes data + 6 bytes padding + 8 bytes timestamp when
 	 * call iio_push_to_buffers_with_timestamp.
 	 */
-	__be16                          rx_buf[8] ____cacheline_aligned;
+	__be16                          rx_buf[8] __aligned(IIO_ALIGN);
 };
 
 struct tlc4541_chip_info {
-- 
2.36.0

[PATCH 40/92] iio: addac: ad74413r: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: fea251b6a5db ("iio: addac: add AD74413R driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cosmin Tanislav <cosmin.tanislav@analog.com>
---
 drivers/iio/addac/ad74413r.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/addac/ad74413r.c b/drivers/iio/addac/ad74413r.c
index acd230a6af35..99ddf3f4c544 100644
--- a/drivers/iio/addac/ad74413r.c
+++ b/drivers/iio/addac/ad74413r.c
@@ -77,13 +77,13 @@ struct ad74413r_state {
 	struct spi_transfer	adc_samples_xfer[AD74413R_CHANNEL_MAX + 1];
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 	struct {
 		u8 rx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
 		s64 timestamp;
-	} adc_samples_buf ____cacheline_aligned;
+	} adc_samples_buf __aligned(IIO_ALIGN);
 
 	u8	adc_samples_tx_buf[AD74413R_FRAME_SIZE * AD74413R_CHANNEL_MAX];
 	u8	reg_tx_buf[AD74413R_FRAME_SIZE];
-- 
2.36.0

[PATCH 41/92] iio: amplifiers: ad8366: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: e71d42e03c60 ("iio: amplifiers: New driver for AD8366 Dual-Digital Variable Gain Amplifier")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/amplifiers/ad8366.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/amplifiers/ad8366.c b/drivers/iio/amplifiers/ad8366.c
index 1134ae12e531..8527d8bfc5db 100644
--- a/drivers/iio/amplifiers/ad8366.c
+++ b/drivers/iio/amplifiers/ad8366.c
@@ -45,10 +45,10 @@ struct ad8366_state {
 	enum ad8366_type	type;
 	struct ad8366_info	*info;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	unsigned char		data[2] ____cacheline_aligned;
+	unsigned char		data[2] __aligned(IIO_ALIGN);
 };
 
 static struct ad8366_info ad8366_infos[] = {
-- 
2.36.0

[PATCH 42/92] iio: common: ssp: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 50dd64d57eee ("iio: common: ssp_sensors: Add sensorhub driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/common/ssp_sensors/ssp.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/iio/common/ssp_sensors/ssp.h b/drivers/iio/common/ssp_sensors/ssp.h
index abb832795619..33927e837022 100644
--- a/drivers/iio/common/ssp_sensors/ssp.h
+++ b/drivers/iio/common/ssp_sensors/ssp.h
@@ -221,8 +221,7 @@ struct ssp_data {
 	struct iio_dev *sensor_devs[SSP_SENSOR_MAX];
 	atomic_t enable_refcount;
 
-	__le16 header_buffer[SSP_HEADER_BUFFER_SIZE / sizeof(__le16)]
-		____cacheline_aligned;
+	__le16 header_buffer[SSP_HEADER_BUFFER_SIZE / sizeof(__le16)] __aligned(IIO_ALIGN);
 };
 
 void ssp_clean_pending_list(struct ssp_data *data);
-- 
2.36.0

[PATCH 43/92] iio: dac: ad5064: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 6a17a0768f77 ("iio:dac:ad5064: Add support for the ad5629r and ad5669r")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/iio/dac/ad5064.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad5064.c b/drivers/iio/dac/ad5064.c
index 27ee2c63c5d4..daeea263dc6a 100644
--- a/drivers/iio/dac/ad5064.c
+++ b/drivers/iio/dac/ad5064.c
@@ -115,13 +115,13 @@ struct ad5064_state {
 	struct mutex lock;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 	union {
 		u8 i2c[3];
 		__be32 spi;
-	} data ____cacheline_aligned;
+	} data __aligned(IIO_ALIGN);
 };
 
 enum ad5064_type {
-- 
2.36.0

[PATCH 44/92] iio: dac: ad5360: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: a3e2940c24d3 ("staging:iio:dac: Add AD5360 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/iio/dac/ad5360.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad5360.c b/drivers/iio/dac/ad5360.c
index ecbc6a51d60f..b1f0e29e7526 100644
--- a/drivers/iio/dac/ad5360.c
+++ b/drivers/iio/dac/ad5360.c
@@ -79,13 +79,13 @@ struct ad5360_state {
 	struct mutex			lock;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 	union {
 		__be32 d32;
 		u8 d8[4];
-	} data[2] ____cacheline_aligned;
+	} data[2] __aligned(IIO_ALIGN);
 };
 
 enum ad5360_type {
-- 
2.36.0

[PATCH 45/92] iio: dac: ad5421: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 5691b23489db ("staging:iio:dac: Add AD5421 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/iio/dac/ad5421.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad5421.c b/drivers/iio/dac/ad5421.c
index eedf661d32b2..48d36d4a6ff7 100644
--- a/drivers/iio/dac/ad5421.c
+++ b/drivers/iio/dac/ad5421.c
@@ -72,13 +72,13 @@ struct ad5421_state {
 	struct mutex			lock;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 	union {
 		__be32 d32;
 		u8 d8[4];
-	} data[2] ____cacheline_aligned;
+	} data[2] __aligned(IIO_ALIGN);
 };
 
 static const struct iio_event_spec ad5421_current_event[] = {
-- 
2.36.0

[PATCH 46/92] iio: dac: ad5449: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 8341dc04dfb3 ("iio:dac: Add support for the ad5449")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/iio/dac/ad5449.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad5449.c b/drivers/iio/dac/ad5449.c
index bad9bdaafa94..87307484bd7a 100644
--- a/drivers/iio/dac/ad5449.c
+++ b/drivers/iio/dac/ad5449.c
@@ -68,10 +68,10 @@ struct ad5449 {
 	uint16_t dac_cache[AD5449_MAX_CHANNELS];
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	__be16 data[2] ____cacheline_aligned;
+	__be16 data[2] __aligned(IIO_ALIGN);
 };
 
 enum ad5449_type {
-- 
2.36.0

[PATCH 47/92] iio: dac: ad5504: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 0dbe59c7a788 ("iio:ad5504: Do not store transfer buffers on the stack")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Lars-Peter Clausen <lars@metafoo.de>
---
 drivers/iio/dac/ad5504.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ad5504.c b/drivers/iio/dac/ad5504.c
index 8507573aa13e..cfbb8335228c 100644
--- a/drivers/iio/dac/ad5504.c
+++ b/drivers/iio/dac/ad5504.c
@@ -54,7 +54,7 @@ struct ad5504_state {
 	unsigned			pwr_down_mask;
 	unsigned			pwr_down_mode;
 
-	__be16				data[2] ____cacheline_aligned;
+	__be16				data[2] __aligned(IIO_ALIGN);
 };
 
 /*
-- 
2.36.0

[PATCH 48/92] iio: dac: ad5592r: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 56ca9db862bf ("iio: dac: Add support for the AD5592R/AD5593R ADCs/DACs")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Paul Cercueil <paul@crapouillou.net>
---
 drivers/iio/dac/ad5592r-base.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ad5592r-base.h b/drivers/iio/dac/ad5592r-base.h
index 2a22ef691996..072563c4529b 100644
--- a/drivers/iio/dac/ad5592r-base.h
+++ b/drivers/iio/dac/ad5592r-base.h
@@ -14,6 +14,8 @@
 #include <linux/mutex.h>
 #include <linux/gpio/driver.h>
 
+#include <linux/iio/iio.h>
+
 struct device;
 struct ad5592r_state;
 
@@ -65,7 +67,7 @@ struct ad5592r_state {
 	u8 gpio_in;
 	u8 gpio_val;
 
-	__be16 spi_msg ____cacheline_aligned;
+	__be16 spi_msg __aligned(IIO_ALIGN);
 	__be16 spi_msg_nop;
 };
 
-- 
2.36.0

[PATCH 49/92] iio: dac: ad5686: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 0357e488b825 ("iio:dac:ad5686: Refactor the driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/dac/ad5686.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad5686.h b/drivers/iio/dac/ad5686.h
index cd5fff9e9d53..e7c0db87791f 100644
--- a/drivers/iio/dac/ad5686.h
+++ b/drivers/iio/dac/ad5686.h
@@ -13,6 +13,8 @@
 #include <linux/mutex.h>
 #include <linux/kernel.h>
 
+#include <linux/iio/iio.h>
+
 #define AD5310_CMD(x)				((x) << 12)
 
 #define AD5683_DATA(x)				((x) << 4)
@@ -137,7 +139,7 @@ struct ad5686_state {
 	struct mutex			lock;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 
@@ -145,7 +147,7 @@ struct ad5686_state {
 		__be32 d32;
 		__be16 d16;
 		u8 d8[4];
-	} data[3] ____cacheline_aligned;
+	} data[3] __aligned(IIO_ALIGN);
 };
 
 
-- 
2.36.0

[PATCH 50/92] iio: dac: ad5755: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: c499d029d805 ("iio:dac: Add ad5755 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/dac/ad5755.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad5755.c b/drivers/iio/dac/ad5755.c
index 7a62e6e1d5f1..90bc293528fb 100644
--- a/drivers/iio/dac/ad5755.c
+++ b/drivers/iio/dac/ad5755.c
@@ -189,14 +189,14 @@ struct ad5755_state {
 	struct mutex			lock;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 
 	union {
 		__be32 d32;
 		u8 d8[4];
-	} data[2] ____cacheline_aligned;
+	} data[2] __aligned(IIO_ALIGN);
 };
 
 enum ad5755_type {
-- 
2.36.0

[PATCH 51/92] iio: dac: ad5761: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 131497acd88a ("iio: add ad5761 DAC driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/dac/ad5761.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad5761.c b/drivers/iio/dac/ad5761.c
index 4cb8471db81e..2f493f9ae2d2 100644
--- a/drivers/iio/dac/ad5761.c
+++ b/drivers/iio/dac/ad5761.c
@@ -70,13 +70,13 @@ struct ad5761_state {
 	enum ad5761_voltage_range range;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 	union {
 		__be32 d32;
 		u8 d8[4];
-	} data[3] ____cacheline_aligned;
+	} data[3] __aligned(IIO_ALIGN);
 };
 
 static const struct ad5761_range_params ad5761_range_params[] = {
-- 
2.36.0

[PATCH 52/92] iio: dac: ad5764: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 68b14d7ea956 ("staging:iio:dac: Add AD5764 driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/dac/ad5764.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad5764.c b/drivers/iio/dac/ad5764.c
index d235a8047ba0..ad14f277add8 100644
--- a/drivers/iio/dac/ad5764.c
+++ b/drivers/iio/dac/ad5764.c
@@ -56,13 +56,13 @@ struct ad5764_state {
 	struct mutex			lock;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
 	union {
 		__be32 d32;
 		u8 d8[4];
-	} data[2] ____cacheline_aligned;
+	} data[2] __aligned(IIO_ALIGN);
 };
 
 enum ad5764_type {
-- 
2.36.0

[PATCH 53/92] iio: dac: ad5766: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: fd9373e41b9b ("iio: dac: ad5766: add driver support for AD5766")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cristian Pop <cristian.pop@analog.com>
---
 drivers/iio/dac/ad5766.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ad5766.c b/drivers/iio/dac/ad5766.c
index 43189af2fb1f..71953bc45f8e 100644
--- a/drivers/iio/dac/ad5766.c
+++ b/drivers/iio/dac/ad5766.c
@@ -123,7 +123,7 @@ struct ad5766_state {
 		u32	d32;
 		u16	w16[2];
 		u8	b8[4];
-	} data[3] ____cacheline_aligned;
+	} data[3] __aligned(IIO_ALIGN);
 };
 
 struct ad5766_span_tbl {
-- 
2.36.0

[PATCH 54/92] iio: dac: ad5770r: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: cbbb819837f6 ("iio: dac: ad5770r: Add AD5770R support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Alexandru Tachici <alexandru.tachici@analog.com>
---
 drivers/iio/dac/ad5770r.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ad5770r.c b/drivers/iio/dac/ad5770r.c
index 7e2fd32e993a..be5b6331e6d9 100644
--- a/drivers/iio/dac/ad5770r.c
+++ b/drivers/iio/dac/ad5770r.c
@@ -140,7 +140,7 @@ struct ad5770r_state {
 	bool				ch_pwr_down[AD5770R_MAX_CHANNELS];
 	bool				internal_ref;
 	bool				external_res;
-	u8				transf_buf[2] ____cacheline_aligned;
+	u8				transf_buf[2] __aligned(IIO_ALIGN);
 };
 
 static const struct regmap_config ad5770r_spi_regmap_config = {
-- 
2.36.0

[PATCH 55/92] iio: dac: ad5791: Fix alignment for DMA saftey

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 791bb52a0cd2 ("iio:ad5791: Do not store transfer buffers on the stack")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/dac/ad5791.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ad5791.c b/drivers/iio/dac/ad5791.c
index 2b14914b4050..b0fa7bca877b 100644
--- a/drivers/iio/dac/ad5791.c
+++ b/drivers/iio/dac/ad5791.c
@@ -95,7 +95,7 @@ struct ad5791_state {
 	union {
 		__be32 d32;
 		u8 d8[4];
-	} data[3] ____cacheline_aligned;
+	} data[3] __aligned(IIO_ALIGN);
 };
 
 enum ad5791_supported_device_ids {
-- 
2.36.0

[PATCH 56/92] iio: dac: ad7293: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 0bb12606c05f ("iio:dac:ad7293: add support for AD7293")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 drivers/iio/dac/ad7293.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ad7293.c b/drivers/iio/dac/ad7293.c
index 59a38ca4c3c7..c2532d431214 100644
--- a/drivers/iio/dac/ad7293.c
+++ b/drivers/iio/dac/ad7293.c
@@ -144,7 +144,7 @@ struct ad7293_state {
 	struct regulator *reg_avdd;
 	struct regulator *reg_vdrive;
 	u8 page_select;
-	u8 data[3] ____cacheline_aligned;
+	u8 data[3] __aligned(IIO_ALIGN);
 };
 
 static int ad7293_page_select(struct ad7293_state *st, unsigned int reg)
-- 
2.36.0

[PATCH 57/92] iio: dac: ad7303: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: f83478240e74 ("iio:dac: Add support for the AD7303")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/dac/ad7303.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ad7303.c b/drivers/iio/dac/ad7303.c
index 91eaaf793b3e..2a439ea9d1c7 100644
--- a/drivers/iio/dac/ad7303.c
+++ b/drivers/iio/dac/ad7303.c
@@ -44,10 +44,10 @@ struct ad7303_state {
 
 	struct mutex lock;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	__be16 data ____cacheline_aligned;
+	__be16 data __aligned(IIO_ALIGN);
 };
 
 static int ad7303_write(struct ad7303_state *st, unsigned int chan,
-- 
2.36.0

[PATCH 58/92] iio: dac: ad8801: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 7f270bc9a2d9 ("iio: dac: AD8801: add Analog Devices AD8801/AD8803 support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/dac/ad8801.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ad8801.c b/drivers/iio/dac/ad8801.c
index 6be35c92d435..dfe2640d6af2 100644
--- a/drivers/iio/dac/ad8801.c
+++ b/drivers/iio/dac/ad8801.c
@@ -26,7 +26,7 @@ struct ad8801_state {
 	struct regulator *vrefh_reg;
 	struct regulator *vrefl_reg;
 
-	__be16 data ____cacheline_aligned;
+	__be16 data __aligned(IIO_ALIGN);
 };
 
 static int ad8801_spi_write(struct ad8801_state *state,
-- 
2.36.0

[PATCH 59/92] iio: dac: ltc2688: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Update the comment to include 'may'.

Fixes: 832cb9eeb931 ("iio: dac: add support for ltc2688")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Nuno Sá <nuno.sa@analog.com>
---
 drivers/iio/dac/ltc2688.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ltc2688.c b/drivers/iio/dac/ltc2688.c
index 2f9c384885f4..6bf1ba8bf5f2 100644
--- a/drivers/iio/dac/ltc2688.c
+++ b/drivers/iio/dac/ltc2688.c
@@ -91,10 +91,10 @@ struct ltc2688_state {
 	struct mutex lock;
 	int vref;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	u8 tx_data[6] ____cacheline_aligned;
+	u8 tx_data[6] __aligned(IIO_ALIGN);
 	u8 rx_data[3];
 };
 
-- 
2.36.0

[PATCH 60/92] iio: dac: mcp3922: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 1b791fadf3a1 ("iio: dac: mcp4902/mcp4912/mcp4922 dac driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Michael Welling <mwelling@ieee.org>
---
 drivers/iio/dac/mcp4922.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/mcp4922.c b/drivers/iio/dac/mcp4922.c
index cb9e60e71b91..5252cc93f693 100644
--- a/drivers/iio/dac/mcp4922.c
+++ b/drivers/iio/dac/mcp4922.c
@@ -29,7 +29,7 @@ struct mcp4922_state {
 	unsigned int value[MCP4922_NUM_CHANNELS];
 	unsigned int vref_mv;
 	struct regulator *vref_reg;
-	u8 mosi[2] ____cacheline_aligned;
+	u8 mosi[2] __aligned(IIO_ALIGN);
 };
 
 #define MCP4922_CHAN(chan, bits) {			\
-- 
2.36.0

[PATCH 61/92] iio: dac: ti-dac082s085: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 61011264c1af ("iio: dac: Add Texas Instruments 8/10/12-bit 2/4-channel DAC driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/dac/ti-dac082s085.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ti-dac082s085.c b/drivers/iio/dac/ti-dac082s085.c
index 4e1156e6deb2..f2ae659c4787 100644
--- a/drivers/iio/dac/ti-dac082s085.c
+++ b/drivers/iio/dac/ti-dac082s085.c
@@ -55,7 +55,7 @@ struct ti_dac_chip {
 	bool powerdown;
 	u8 powerdown_mode;
 	u8 resolution;
-	u8 buf[2] ____cacheline_aligned;
+	u8 buf[2] __aligned(IIO_ALIGN);
 };
 
 #define WRITE_NOT_UPDATE(chan)	(0x00 | (chan) << 6)
-- 
2.36.0

[PATCH 62/92] iio: dac: ti-dac5571: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: df38a4a72a3b ("iio: dac: add TI DAC5571 family support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Sean Nyekjaer <sean.nyekjaer@prevas.dk>
---
 drivers/iio/dac/ti-dac5571.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ti-dac5571.c b/drivers/iio/dac/ti-dac5571.c
index 0b775f943db3..0a13df8101b4 100644
--- a/drivers/iio/dac/ti-dac5571.c
+++ b/drivers/iio/dac/ti-dac5571.c
@@ -52,7 +52,7 @@ struct dac5571_data {
 	struct dac5571_spec const *spec;
 	int (*dac5571_cmd)(struct dac5571_data *data, int channel, u16 val);
 	int (*dac5571_pwrdwn)(struct dac5571_data *data, int channel, u8 pwrdwn);
-	u8 buf[3] ____cacheline_aligned;
+	u8 buf[3] __aligned(IIO_ALIGN);
 };
 
 #define DAC5571_POWERDOWN(mode)		((mode) + 1)
-- 
2.36.0

[PATCH 63/92] iio: dac: ti-dac7311: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 7a02ef7907d8 ("iio:dac:ti-dac7311 Add driver for Texas Instrument DAC7311")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Charles-Antoine Couret <charles-antoine.couret@essensium.com>
---
 drivers/iio/dac/ti-dac7311.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/dac/ti-dac7311.c b/drivers/iio/dac/ti-dac7311.c
index e10d17e60ed3..d86567be138a 100644
--- a/drivers/iio/dac/ti-dac7311.c
+++ b/drivers/iio/dac/ti-dac7311.c
@@ -52,7 +52,7 @@ struct ti_dac_chip {
 	bool powerdown;
 	u8 powerdown_mode;
 	u8 resolution;
-	u8 buf[2] ____cacheline_aligned;
+	u8 buf[2] __aligned(IIO_ALIGN);
 };
 
 static u8 ti_dac_get_power(struct ti_dac_chip *ti_dac, bool powerdown)
-- 
2.36.0

[PATCH 64/92] iio: dac: ti-dac7612: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: 977724d20584 ("iio:dac:ti-dac7612: Add driver for Texas Instruments DAC7612")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ricardo Ribalda <ribalda@kernel.org>
---
 drivers/iio/dac/ti-dac7612.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/dac/ti-dac7612.c b/drivers/iio/dac/ti-dac7612.c
index 4c0f4b5e9ff4..d118df004539 100644
--- a/drivers/iio/dac/ti-dac7612.c
+++ b/drivers/iio/dac/ti-dac7612.c
@@ -31,10 +31,10 @@ struct dac7612 {
 	struct mutex lock;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
+	 * DMA (thus cache coherency maintenance) may require the
 	 * transfer buffers to live in their own cache lines.
 	 */
-	uint8_t data[2] ____cacheline_aligned;
+	uint8_t data[2] __aligned(IIO_ALIGN);
 };
 
 static int dac7612_cmd_single(struct dac7612 *priv, int channel, u16 val)
-- 
2.36.0

[PATCH 65/92] iio: frequency: ad9523: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: cd1678f96329 ("iio: frequency: New driver for AD9523 SPI Low Jitter Clock Generator")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/frequency/ad9523.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/frequency/ad9523.c b/drivers/iio/frequency/ad9523.c
index a0f92c336fc4..d9fd187cb4dd 100644
--- a/drivers/iio/frequency/ad9523.c
+++ b/drivers/iio/frequency/ad9523.c
@@ -287,13 +287,13 @@ struct ad9523_state {
 	struct mutex		lock;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
-	 * transfer buffers to live in their own cache lines.
+	 * DMA (thus cache coherency maintenance) may require that
+	 * transfer buffers live in their own cache lines.
 	 */
 	union {
 		__be32 d32;
 		u8 d8[4];
-	} data[2] ____cacheline_aligned;
+	} data[2] __aligned(IIO_ALIGN);
 };
 
 static int ad9523_read(struct iio_dev *indio_dev, unsigned int addr)
-- 
2.36.0

[PATCH 66/92] iio: frequency: adf4350: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: e31166f0fd48 ("iio: frequency: New driver for Analog Devices ADF4350/ADF4351 Wideband Synthesizers")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/frequency/adf4350.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/frequency/adf4350.c b/drivers/iio/frequency/adf4350.c
index be1218d86291..eba8616fc295 100644
--- a/drivers/iio/frequency/adf4350.c
+++ b/drivers/iio/frequency/adf4350.c
@@ -56,10 +56,10 @@ struct adf4350_state {
 	 */
 	struct mutex			lock;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
-	 * transfer buffers to live in their own cache lines.
+	 * DMA (thus cache coherency maintenance) may require that
+	 * transfer buffers live in their own cache lines.
 	 */
-	__be32				val ____cacheline_aligned;
+	__be32				val __aligned(IIO_ALIGN);
 };
 
 static struct adf4350_platform_data default_pdata = {
-- 
2.36.0

[PATCH 67/92] iio: frequency: adf4371: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 7f699bd14913 ("iio: frequency: adf4371: Add support for ADF4371 PLL")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/frequency/adf4371.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/frequency/adf4371.c b/drivers/iio/frequency/adf4371.c
index ecd5e18995ad..edc5d1e8b5d7 100644
--- a/drivers/iio/frequency/adf4371.c
+++ b/drivers/iio/frequency/adf4371.c
@@ -175,7 +175,7 @@ struct adf4371_state {
 	unsigned int mod2;
 	unsigned int rf_div_sel;
 	unsigned int ref_div_factor;
-	u8 buf[10] ____cacheline_aligned;
+	u8 buf[10] __aligned(IIO_ALIGN);
 };
 
 static unsigned long long adf4371_pll_fract_n_get_rate(struct adf4371_state *st,
-- 
2.36.0

[PATCH 68/92] iio: frequency: admv1013: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: da35a7b526d9 ("iio: frequency: admv1013: add support for ADMV1013")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 drivers/iio/frequency/admv1013.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/frequency/admv1013.c b/drivers/iio/frequency/admv1013.c
index b0e1f6571afb..caa81b411483 100644
--- a/drivers/iio/frequency/admv1013.c
+++ b/drivers/iio/frequency/admv1013.c
@@ -100,7 +100,7 @@ struct admv1013_state {
 	unsigned int		input_mode;
 	unsigned int		quad_se_mode;
 	bool			det_en;
-	u8			data[3] ____cacheline_aligned;
+	u8			data[3] __aligned(IIO_ALIGN);
 };
 
 static int __admv1013_spi_read(struct admv1013_state *st, unsigned int reg,
-- 
2.36.0

[PATCH 69/92] iio: frequency: admv1014: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: f4eb9ac7842f ("iio: frequency: admv1014: add support for ADMV1014")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 drivers/iio/frequency/admv1014.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/frequency/admv1014.c b/drivers/iio/frequency/admv1014.c
index a7994f8e6b9b..7eda479d286f 100644
--- a/drivers/iio/frequency/admv1014.c
+++ b/drivers/iio/frequency/admv1014.c
@@ -127,7 +127,7 @@ struct admv1014_state {
 	unsigned int			quad_se_mode;
 	unsigned int			p1db_comp;
 	bool				det_en;
-	u8				data[3] ____cacheline_aligned;
+	u8				data[3] __aligned(IIO_ALIGN);
 };
 
 static const int mixer_vgate_table[] = {106, 107, 108, 110, 111, 112, 113, 114,
-- 
2.36.0

[PATCH 70/92] iio: frequency: admv4420: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: b59c04155901 ("iio: frequency: admv4420.c: Add support for ADMV4420")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Cristian Pop <cristian.pop@analog.com>
---
 drivers/iio/frequency/admv4420.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/frequency/admv4420.c b/drivers/iio/frequency/admv4420.c
index 51134aee8510..71c1af6fd56b 100644
--- a/drivers/iio/frequency/admv4420.c
+++ b/drivers/iio/frequency/admv4420.c
@@ -113,7 +113,7 @@ struct admv4420_state {
 	struct admv4420_n_counter	n_counter;
 	enum admv4420_mux_sel		mux_sel;
 	struct mutex			lock;
-	u8				transf_buf[4] ____cacheline_aligned;
+	u8				transf_buf[4] __aligned(IIO_ALIGN);
 };
 
 static const struct regmap_config admv4420_regmap_config = {
-- 
2.36.0

[PATCH 71/92] iio: frequency: adrf6780: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 63aaf6d06d87 ("iio: frequency: adrf6780: add support for ADRF6780")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Antoniu Miclaus <antoniu.miclaus@analog.com>
---
 drivers/iio/frequency/adrf6780.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/frequency/adrf6780.c b/drivers/iio/frequency/adrf6780.c
index 8255ffd174f6..788de3b05e3a 100644
--- a/drivers/iio/frequency/adrf6780.c
+++ b/drivers/iio/frequency/adrf6780.c
@@ -86,7 +86,7 @@ struct adrf6780_state {
 	bool			uc_bias_en;
 	bool			lo_sideband;
 	bool			vdet_out_en;
-	u8			data[3] ____cacheline_aligned;
+	u8			data[3] __aligned(IIO_ALIGN);
 };
 
 static int __adrf6780_spi_read(struct adrf6780_state *st, unsigned int reg,
-- 
2.36.0

[PATCH 72/92] iio: gyro: adis16080: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes tag is inaccurate but unlikely anyone will backport this
beyond that point so I haven't chased the history futher than 2013.

Fixes: 3c80372dae17 ("staging:iio:adis16080: be16 cleanups")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/gyro/adis16080.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/gyro/adis16080.c b/drivers/iio/gyro/adis16080.c
index acef59d822b1..b97c07f31370 100644
--- a/drivers/iio/gyro/adis16080.c
+++ b/drivers/iio/gyro/adis16080.c
@@ -45,7 +45,7 @@ struct adis16080_state {
 	const struct adis16080_chip_info *info;
 	struct mutex			lock;
 
-	__be16 buf ____cacheline_aligned;
+	__be16 buf __aligned(IIO_ALIGN);
 };
 
 static int adis16080_read_sample(struct iio_dev *indio_dev,
-- 
2.36.0

[PATCH 73/92] iio: gyro: adis16130: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 8e67875141b2 ("staging:iio:gyro: adis16130 cleanup, move to abi and bug fixes.")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/gyro/adis16130.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/gyro/adis16130.c b/drivers/iio/gyro/adis16130.c
index b9c952e65b55..f7de3c415702 100644
--- a/drivers/iio/gyro/adis16130.c
+++ b/drivers/iio/gyro/adis16130.c
@@ -41,7 +41,7 @@
 struct adis16130_state {
 	struct spi_device		*us;
 	struct mutex			buf_lock;
-	u8				buf[4] ____cacheline_aligned;
+	u8				buf[4] __aligned(IIO_ALIGN);
 };
 
 static int adis16130_spi_read(struct iio_dev *indio_dev, u8 reg_addr, u32 *val)
-- 
2.36.0

[PATCH 74/92] iio: gyro: adxrs450: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes tag is inaccurate but unlikely anyone will be interested in
backporting beyond that point.

Fixes: 53ac8500ba9b ("staging:iio:adxrs450: Move header file contents to main file")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/gyro/adxrs450.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/gyro/adxrs450.c b/drivers/iio/gyro/adxrs450.c
index 04f350025215..248841461ac4 100644
--- a/drivers/iio/gyro/adxrs450.c
+++ b/drivers/iio/gyro/adxrs450.c
@@ -73,7 +73,7 @@ enum {
 struct adxrs450_state {
 	struct spi_device	*us;
 	struct mutex		buf_lock;
-	__be32			tx ____cacheline_aligned;
+	__be32			tx __aligned(IIO_ALIGN);
 	__be32			rx;
 
 };
-- 
2.36.0

[PATCH 75/92] iio: gyro: fxas210002c: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Updated the comment to 'may' require.

Fixes: a0701b6263ae ("iio: gyro: add core driver for fxas21002c")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Rui Miguel Silva <rui.silva@linaro.org>
---
 drivers/iio/gyro/fxas21002c_core.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c
index 410e5e9f2672..d89dab48956a 100644
--- a/drivers/iio/gyro/fxas21002c_core.c
+++ b/drivers/iio/gyro/fxas21002c_core.c
@@ -150,10 +150,10 @@ struct fxas21002c_data {
 	struct regulator *vddio;
 
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
-	 * transfer buffers to live in their own cache lines.
+	 * DMA (thus cache coherency maintenance) may require the
+	 * transfer buffers live in their own cache lines.
 	 */
-	s16 buffer[8] ____cacheline_aligned;
+	s16 buffer[8] __aligned(IIO_ALIGN);
 };
 
 enum fxas21002c_channel_index {
-- 
2.36.0

[PATCH 76/92] iio: imu: fxos8700: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 84e5ddd5c46e ("iio: imu: Add support for the FXOS8700 IMU")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Robert Jones <rjones@gateworks.com>
---
 drivers/iio/imu/fxos8700_core.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/imu/fxos8700_core.c b/drivers/iio/imu/fxos8700_core.c
index ab288186f36e..8d2a9b9533db 100644
--- a/drivers/iio/imu/fxos8700_core.c
+++ b/drivers/iio/imu/fxos8700_core.c
@@ -167,7 +167,7 @@
 struct fxos8700_data {
 	struct regmap *regmap;
 	struct iio_trigger *trig;
-	__be16 buf[FXOS8700_DATA_BUF_SIZE] ____cacheline_aligned;
+	__be16 buf[FXOS8700_DATA_BUF_SIZE] __aligned(IIO_ALIGN);
 };
 
 /* Regmap info */
-- 
2.36.0

[PATCH 77/92] iio: imu_icm42600: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Partial fix for this driver as a second instance was introduced in
a later patch.

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: a095fadb443b ("iio: imu: inv_icm42600: add gyroscope IIO device")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
---
 drivers/iio/imu/inv_icm42600/inv_icm42600.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600.h b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
index c0f5059b13b3..5b3740cb364f 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
@@ -140,7 +140,7 @@ struct inv_icm42600_state {
 	struct inv_icm42600_suspended suspended;
 	struct iio_dev *indio_gyro;
 	struct iio_dev *indio_accel;
-	uint8_t buffer[2] ____cacheline_aligned;
+	uint8_t buffer[2] __aligned(IIO_ALIGN);
 	struct inv_icm42600_fifo fifo;
 	struct {
 		int64_t gyro;
-- 
2.36.0

[PATCH 78/92] iio: imu: icm42600: Fix alignment for DMA safety in buffer code.

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Second fix for this driver due to different introducing patches.

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 7f85e42a6c54 ("iio: imu: inv_icm42600: add buffer support in iio devices")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
---
 drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h b/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h
index de2a3949dcc7..56545638bfcd 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h
@@ -39,7 +39,7 @@ struct inv_icm42600_fifo {
 		size_t accel;
 		size_t total;
 	} nb;
-	uint8_t data[2080] ____cacheline_aligned;
+	uint8_t data[2080] __aligned(IIO_ALIGN);
 };
 
 /* FIFO data packet */
-- 
2.36.0

[PATCH 79/92] iio: imu: mpu6050: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 6b0cc5dce072 ("iio:imu:inv_mpu6050 Fix dma and ts alignment and data leak issues.")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
---
 drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
index c6aa36ee966a..18bd1a50463c 100644
--- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
+++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
@@ -203,7 +203,7 @@ struct inv_mpu6050_state {
 	s32 magn_raw_to_gauss[3];
 	struct iio_mount_matrix magn_orient;
 	unsigned int suspended_sensors;
-	u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] ____cacheline_aligned;
+	u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] __aligned(IIO_ALIGN);
 };
 
 /*register and associated bit definition*/
-- 
2.36.0

[PATCH 80/92] iio: potentiometer: ad5110: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: d03a74bfacce ("iio: potentiometer: Add driver support for AD5110")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Mugilraj Dhavachelvan <dmugil2000@gmail.com>
---
 drivers/iio/potentiometer/ad5110.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/potentiometer/ad5110.c b/drivers/iio/potentiometer/ad5110.c
index d4eeedae56e5..29f9a9037077 100644
--- a/drivers/iio/potentiometer/ad5110.c
+++ b/drivers/iio/potentiometer/ad5110.c
@@ -63,10 +63,10 @@ struct ad5110_data {
 	struct mutex            lock;
 	const struct ad5110_cfg	*cfg;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
-	 * transfer buffers to live in their own cache lines.
+	 * DMA (thus cache coherency maintenance) may require the
+	 * transfer buffers live in their own cache lines.
 	 */
-	u8			buf[2] ____cacheline_aligned;
+	u8			buf[2] __aligned(IIO_ALIGN);
 };
 
 static const struct iio_chan_spec ad5110_channels[] = {
-- 
2.36.0

[PATCH 81/92] iio: potentiometer: ad5272: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 79e8a32d2aa9 ("iio: ad5272: Add support for Analog Devices digital potentiometers")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Phil Reid <preid@electromag.com.au>
---
 drivers/iio/potentiometer/ad5272.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/potentiometer/ad5272.c b/drivers/iio/potentiometer/ad5272.c
index d8cbd170262f..e023c0f92242 100644
--- a/drivers/iio/potentiometer/ad5272.c
+++ b/drivers/iio/potentiometer/ad5272.c
@@ -50,7 +50,7 @@ struct ad5272_data {
 	struct i2c_client       *client;
 	struct mutex            lock;
 	const struct ad5272_cfg *cfg;
-	u8                      buf[2] ____cacheline_aligned;
+	u8                      buf[2] __aligned(IIO_ALIGN);
 };
 
 static const struct iio_chan_spec ad5272_channel = {
-- 
2.36.0

[PATCH 82/92] iio: potentiometer: max5481: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: df1fd2de118e ("iio: max5481: Add support for Maxim digital potentiometers")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/potentiometer/max5481.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/potentiometer/max5481.c b/drivers/iio/potentiometer/max5481.c
index 098d144a8fdd..6e22b31cbe8b 100644
--- a/drivers/iio/potentiometer/max5481.c
+++ b/drivers/iio/potentiometer/max5481.c
@@ -44,7 +44,7 @@ static const struct max5481_cfg max5481_cfg[] = {
 struct max5481_data {
 	struct spi_device *spi;
 	const struct max5481_cfg *cfg;
-	u8 msg[3] ____cacheline_aligned;
+	u8 msg[3] __aligned(IIO_ALIGN);
 };
 
 #define MAX5481_CHANNEL {					\
-- 
2.36.0

[PATCH 83/92] iio: potentiometer: mcp41010: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 092cb71a604e ("iio: potentiometer: Add driver for Microchip MCP41xxx/42xxx")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/potentiometer/mcp41010.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/potentiometer/mcp41010.c b/drivers/iio/potentiometer/mcp41010.c
index 30a4594d4e11..2726a3b4a782 100644
--- a/drivers/iio/potentiometer/mcp41010.c
+++ b/drivers/iio/potentiometer/mcp41010.c
@@ -60,7 +60,7 @@ struct mcp41010_data {
 	const struct mcp41010_cfg *cfg;
 	struct mutex lock; /* Protect write sequences */
 	unsigned int value[MCP41010_MAX_WIPERS]; /* Cache wiper values */
-	u8 buf[2] ____cacheline_aligned;
+	u8 buf[2] __aligned(IIO_ALIGN);
 };
 
 #define MCP41010_CHANNEL(ch) {					\
-- 
2.36.0

[PATCH 84/92] iio: potentiometer: mcp4131: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 22d199a53910 ("iio: potentiometer: add driver for Microchip MCP413X/414X/415X/416X/423X/424X/425X/426X")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/potentiometer/mcp4131.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/potentiometer/mcp4131.c b/drivers/iio/potentiometer/mcp4131.c
index 7c8c18ab8764..f0dfac60fc8c 100644
--- a/drivers/iio/potentiometer/mcp4131.c
+++ b/drivers/iio/potentiometer/mcp4131.c
@@ -129,7 +129,7 @@ struct mcp4131_data {
 	struct spi_device *spi;
 	const struct mcp4131_cfg *cfg;
 	struct mutex lock;
-	u8 buf[2] ____cacheline_aligned;
+	u8 buf[2] __aligned(IIO_ALIGN);
 };
 
 #define MCP4131_CHANNEL(ch) {					\
-- 
2.36.0

[PATCH 85/92] iio: pressure: dlhl60d: Drop unnecessary alignment forcing.

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

I2C doesn't use the buffers directly for DMA so there is no need
to enforce alignment.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Tomislav Denis <tomislav.denis@avl.com>
---
 drivers/iio/pressure/dlhl60d.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/pressure/dlhl60d.c b/drivers/iio/pressure/dlhl60d.c
index ade73267d5eb..5f6bb3603a8b 100644
--- a/drivers/iio/pressure/dlhl60d.c
+++ b/drivers/iio/pressure/dlhl60d.c
@@ -47,7 +47,7 @@ struct dlh_state {
 	struct dlh_info info;
 	bool use_interrupt;
 	struct completion completion;
-	u8 rx_buf[DLH_NUM_READ_BYTES] ____cacheline_aligned;
+	u8 rx_buf[DLH_NUM_READ_BYTES];
 };
 
 static struct dlh_info dlh_info_tbl[] = {
-- 
2.36.0

[PATCH 86/92] iio: proximity: as3935: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 24ddb0e4bba4 ("iio: Add AS3935 lightning sensor support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Matt Ranostay <mranostay@gmail.com>
---
 drivers/iio/proximity/as3935.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/proximity/as3935.c b/drivers/iio/proximity/as3935.c
index 67891ce2bd09..e4a6d0de47f4 100644
--- a/drivers/iio/proximity/as3935.c
+++ b/drivers/iio/proximity/as3935.c
@@ -65,7 +65,7 @@ struct as3935_state {
 		u8 chan;
 		s64 timestamp __aligned(8);
 	} scan;
-	u8 buf[2] ____cacheline_aligned;
+	u8 buf[2] __aligned(IIO_ALIGN);
 };
 
 static const struct iio_chan_spec as3935_channels[] = {
-- 
2.36.0

[PATCH 87/92] iio: proximity: vcnl3020: Drop unnecessary alignment requirement for i2c device

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

I2C does not by default use buffers directly for DMA so there is
no need to ensure they are DMA safe.

Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ivan Mikhaylov <i.mikhaylov@yadro.com>
---
 drivers/iio/proximity/vcnl3020.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/iio/proximity/vcnl3020.c b/drivers/iio/proximity/vcnl3020.c
index ff83638db16f..cbc8400c773c 100644
--- a/drivers/iio/proximity/vcnl3020.c
+++ b/drivers/iio/proximity/vcnl3020.c
@@ -71,14 +71,14 @@ static const int vcnl3020_prox_sampling_frequency[][2] = {
  * @dev:	vcnl3020 device.
  * @rev:	revision id.
  * @lock:	lock for protecting access to device hardware registers.
- * @buf:	DMA safe __be16 buffer.
+ * @buf:	__be16 buffer.
  */
 struct vcnl3020_data {
 	struct regmap *regmap;
 	struct device *dev;
 	u8 rev;
 	struct mutex lock;
-	__be16 buf ____cacheline_aligned;
+	__be16 buf;
 };
 
 /**
-- 
2.36.0

[PATCH 88/92] iio: resolver: ad2s1200: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes tag is probably not where the issue was first introduced, but
is likely to be as far as anyone considers backporting this fix.

Fixes: 0bd3d338f61b ("staging: iio: ad2s1200: Improve readability with be16_to_cpup")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/resolver/ad2s1200.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/resolver/ad2s1200.c b/drivers/iio/resolver/ad2s1200.c
index 9746bd935628..c568d2990141 100644
--- a/drivers/iio/resolver/ad2s1200.c
+++ b/drivers/iio/resolver/ad2s1200.c
@@ -41,7 +41,7 @@ struct ad2s1200_state {
 	struct spi_device *sdev;
 	struct gpio_desc *sample;
 	struct gpio_desc *rdvel;
-	__be16 rx ____cacheline_aligned;
+	__be16 rx __aligned(IIO_ALIGN);
 };
 
 static int ad2s1200_read_raw(struct iio_dev *indio_dev,
-- 
2.36.0

[PATCH 89/92] iio: resolver: ad2s90: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes tag is probably not where the issue was first introduced, but
is likely to be far beyond the point where anyone considers
backporting this fix.

Fixes: 58f08b0af857 ("staging:iio:resolver:ad2s90 general cleanup")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 drivers/iio/resolver/ad2s90.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/resolver/ad2s90.c b/drivers/iio/resolver/ad2s90.c
index d6a91f137e13..d8850e6cf911 100644
--- a/drivers/iio/resolver/ad2s90.c
+++ b/drivers/iio/resolver/ad2s90.c
@@ -24,7 +24,7 @@
 struct ad2s90_state {
 	struct mutex lock; /* lock to protect rx buffer */
 	struct spi_device *sdev;
-	u8 rx[2] ____cacheline_aligned;
+	u8 rx[2] __aligned(IIO_ALIGN);
 };
 
 static int ad2s90_read_raw(struct iio_dev *indio_dev,
-- 
2.36.0

[PATCH 90/92] iio: temp: ltc2983: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: f110f3188e56 ("iio: temperature: Add support for LTC2983")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Nuno Sá <nuno.sa@analog.com>
---
 drivers/iio/temperature/ltc2983.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/drivers/iio/temperature/ltc2983.c b/drivers/iio/temperature/ltc2983.c
index 301c3f13fb26..cc90a4abdf3d 100644
--- a/drivers/iio/temperature/ltc2983.c
+++ b/drivers/iio/temperature/ltc2983.c
@@ -200,11 +200,11 @@ struct ltc2983_data {
 	u8 num_channels;
 	u8 iio_channels;
 	/*
-	 * DMA (thus cache coherency maintenance) requires the
-	 * transfer buffers to live in their own cache lines.
+	 * DMA (thus cache coherency maintenance) may require the
+	 * transfer buffers live in their own cache lines.
 	 * Holds the converted temperature
 	 */
-	__be32 temp ____cacheline_aligned;
+	__be32 temp __aligned(IIO_ALIGN);
 };
 
 struct ltc2983_sensor {
-- 
2.36.0

[PATCH 91/92] iio: temp: max31865: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition

Fixes: e112dc4e18ea ("iio: temperature: Add MAX31865 RTD Support")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Navin Sankar Velliangiri <navin@linumiz.com>
---
 drivers/iio/temperature/max31865.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/temperature/max31865.c b/drivers/iio/temperature/max31865.c
index 86c3f3509a26..e68cda4d25dc 100644
--- a/drivers/iio/temperature/max31865.c
+++ b/drivers/iio/temperature/max31865.c
@@ -53,7 +53,7 @@ struct max31865_data {
 	struct mutex lock;
 	bool filter_50hz;
 	bool three_wire;
-	u8 buf[2] ____cacheline_aligned;
+	u8 buf[2] __aligned(IIO_ALIGN);
 };
 
 static int max31865_read(struct max31865_data *data, u8 reg,
-- 
2.36.0

[PATCH 92/92] iio: temp: maxim_thermocouple: Fix alignment for DMA safety

[Jonathan Cameron]

From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition

Fixes: 1f25ca11d84a ("iio: temperature: add support for Maxim thermocouple chips")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Matt Ranostay <mranostay@gmail.com>
---
 drivers/iio/temperature/maxim_thermocouple.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/temperature/maxim_thermocouple.c b/drivers/iio/temperature/maxim_thermocouple.c
index 98c41cddc6f0..03f561af6dba 100644
--- a/drivers/iio/temperature/maxim_thermocouple.c
+++ b/drivers/iio/temperature/maxim_thermocouple.c
@@ -122,7 +122,7 @@ struct maxim_thermocouple_data {
 	struct spi_device *spi;
 	const struct maxim_thermocouple_chip *chip;
 
-	u8 buffer[16] ____cacheline_aligned;
+	u8 buffer[16] __aligned(IIO_ALIGN);
 	char tc_type;
 };
 
-- 
2.36.0

Re: [PATCH 08/92] iio: accel: sca3000: Fix alignment for DMA safety

[Tomas Melin]

Hi,

>[PATCH 08/92] iio: accel: sca3000: Fix alignment for DMA safety
Small typo in commit headline, should be sca3300, otherwise LGTM.


On 03/05/2022 11:58, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> ____cacheline_aligned is insufficient guarantee for non-coherent DMA.
> Switch to the updated IIO_ALIGN definition.
> 
> Fixes: 9cc9806e22178 ("iio: accel: Add driver for Murata SCA3300 accelerometer")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Tomas Melin <tomas.melin@vaisala.com>

Reviewed-by: Tomas Melin <tomas.melin@vaisala.com>

Thanks,
Tomas


> ---
>  drivers/iio/accel/sca3300.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/accel/sca3300.c b/drivers/iio/accel/sca3300.c
> index f7ef8ecfd34a..0e87746829a4 100644
> --- a/drivers/iio/accel/sca3300.c
> +++ b/drivers/iio/accel/sca3300.c
> @@ -115,7 +115,7 @@ struct sca3300_data {
>  		s16 channels[4];
>  		s64 ts __aligned(sizeof(s64));
>  	} scan;
> -	u8 txbuf[4] ____cacheline_aligned;
> +	u8 txbuf[4] __aligned(IIO_ALIGN);
>  	u8 rxbuf[4];
>  };
>  

Re: [PATCH 51/92] iio: dac: ad5761: Fix alignment for DMA safety

[Ricardo Ribalda Delgado]

On Tue, May 3, 2022 at 10:59 AM Jonathan Cameron <jic23@kernel.org> wrote:
>
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
>
> Update the comment to include 'may'.
>
> Fixes: 131497acd88a ("iio: add ad5761 DAC driver")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
> ---
>  drivers/iio/dac/ad5761.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iio/dac/ad5761.c b/drivers/iio/dac/ad5761.c
> index 4cb8471db81e..2f493f9ae2d2 100644
> --- a/drivers/iio/dac/ad5761.c
> +++ b/drivers/iio/dac/ad5761.c
> @@ -70,13 +70,13 @@ struct ad5761_state {
>         enum ad5761_voltage_range range;
>
>         /*
> -        * DMA (thus cache coherency maintenance) requires the
> +        * DMA (thus cache coherency maintenance) may require the
>          * transfer buffers to live in their own cache lines.
>          */
>         union {
>                 __be32 d32;
>                 u8 d8[4];
> -       } data[3] ____cacheline_aligned;
> +       } data[3] __aligned(IIO_ALIGN);
>  };
>
>  static const struct ad5761_range_params ad5761_range_params[] = {
> --
> 2.36.0
>

Re: [PATCH 64/92] iio: dac: ti-dac7612: Fix alignment for DMA safety

[Ricardo Ribalda Delgado]

On Tue, May 3, 2022 at 11:01 AM Jonathan Cameron <jic23@kernel.org> wrote:
>
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
>
> Updated help text to 'may' require buffers to be in their own cacheline.
>
> Fixes: 977724d20584 ("iio:dac:ti-dac7612: Add driver for Texas Instruments DAC7612")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Ricardo Ribalda <ribalda@chromium.org>
> Cc: Ricardo Ribalda <ribalda@kernel.org>
> ---
>  drivers/iio/dac/ti-dac7612.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iio/dac/ti-dac7612.c b/drivers/iio/dac/ti-dac7612.c
> index 4c0f4b5e9ff4..d118df004539 100644
> --- a/drivers/iio/dac/ti-dac7612.c
> +++ b/drivers/iio/dac/ti-dac7612.c
> @@ -31,10 +31,10 @@ struct dac7612 {
>         struct mutex lock;
>
>         /*
> -        * DMA (thus cache coherency maintenance) requires the
> +        * DMA (thus cache coherency maintenance) may require the
>          * transfer buffers to live in their own cache lines.
>          */
> -       uint8_t data[2] ____cacheline_aligned;
> +       uint8_t data[2] __aligned(IIO_ALIGN);
>  };
>
>  static int dac7612_cmd_single(struct dac7612 *priv, int channel, u16 val)
> --
> 2.36.0
>

Re: [PATCH 77/92] iio: imu_icm42600: Fix alignment for DMA safety

[Jean-Baptiste Maneyrol]

Acked-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>


From: Jonathan Cameron <jic23@kernel.org>
Sent: Tuesday, May 3, 2022 10:59
To: linux-iio@vger.kernel.org <linux-iio@vger.kernel.org>
Cc: Akinobu Mita <akinobu.mita@gmail.com>; Alexandru Lazar <alazar@startmail.com>; Alexandru Tachici <alexandru.tachici@analog.com>; Antoniu Miclaus <antoniu.miclaus@analog.com>; Charles-Antoine Couret <charles-antoine.couret@essensium.com>; Cosmin Tanislav <cosmin.tanislav@analog.com>; Cristian Pop <cristian.pop@analog.com>; David Lechner <david@lechnology.com>; Ivan Mikhaylov <i.mikhaylov@yadro.com>; Jacopo Mondi <jacopo+renesas@jmondi.org>; Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>; Lars-Peter Clausen <lars@metafoo.de>; Marcelo Schmitt <marcelo.schmitt1@gmail.com>; Mårten Lindahl <martenli@axis.com>; Matt Ranostay <mranostay@gmail.com>; Michael Hennerich <michael.hennerich@analog.com>; Michael Welling <mwelling@ieee.org>; Mugilraj Dhavachelvan <dmugil2000@gmail.com>; Navin Sankar Velliangiri <navin@linumiz.com>; Nuno Sá <nuno.sa@analog.com>; Paul Cercueil <paul@crapouillou.net>; Phil Reid <preid@electromag.com.au>; Puranjay Mohan <puranjay12@gmail.com>; Ricardo Ribalda <ribalda@kernel.org>; Robert Jones <rjones@gateworks.com>; Rui Miguel Silva <rui.silva@linaro.org>; Sean Nyekjaer <sean.nyekjaer@prevas.dk>; Tomas Melin <tomas.melin@vaisala.com>; Tomislav Denis <tomislav.denis@avl.com>; Uwe Kleine-König <u.kleine-koenig@pengutronix.de>; Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: [PATCH 77/92] iio: imu_icm42600: Fix alignment for DMA safety 
 
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======================================================================
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Partial fix for this driver as a second instance was introduced in
a later patch.

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: a095fadb443b ("iio: imu: inv_icm42600: add gyroscope IIO device")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
---
 drivers/iio/imu/inv_icm42600/inv_icm42600.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600.h b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
index c0f5059b13b3..5b3740cb364f 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600.h
@@ -140,7 +140,7 @@ struct inv_icm42600_state {
         struct inv_icm42600_suspended suspended;
         struct iio_dev *indio_gyro;
         struct iio_dev *indio_accel;
-       uint8_t buffer[2] ____cacheline_aligned;
+       uint8_t buffer[2] __aligned(IIO_ALIGN);
         struct inv_icm42600_fifo fifo;
         struct {
                 int64_t gyro;
-- 
2.36.0

Re: [PATCH 78/92] iio: imu: icm42600: Fix alignment for DMA safety in buffer code.

[Jean-Baptiste Maneyrol]

Acked-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>


From: Jonathan Cameron <jic23@kernel.org>
Sent: Tuesday, May 3, 2022 10:59
To: linux-iio@vger.kernel.org <linux-iio@vger.kernel.org>
Cc: Akinobu Mita <akinobu.mita@gmail.com>; Alexandru Lazar <alazar@startmail.com>; Alexandru Tachici <alexandru.tachici@analog.com>; Antoniu Miclaus <antoniu.miclaus@analog.com>; Charles-Antoine Couret <charles-antoine.couret@essensium.com>; Cosmin Tanislav <cosmin.tanislav@analog.com>; Cristian Pop <cristian.pop@analog.com>; David Lechner <david@lechnology.com>; Ivan Mikhaylov <i.mikhaylov@yadro.com>; Jacopo Mondi <jacopo+renesas@jmondi.org>; Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>; Lars-Peter Clausen <lars@metafoo.de>; Marcelo Schmitt <marcelo.schmitt1@gmail.com>; Mårten Lindahl <martenli@axis.com>; Matt Ranostay <mranostay@gmail.com>; Michael Hennerich <michael.hennerich@analog.com>; Michael Welling <mwelling@ieee.org>; Mugilraj Dhavachelvan <dmugil2000@gmail.com>; Navin Sankar Velliangiri <navin@linumiz.com>; Nuno Sá <nuno.sa@analog.com>; Paul Cercueil <paul@crapouillou.net>; Phil Reid <preid@electromag.com.au>; Puranjay Mohan <puranjay12@gmail.com>; Ricardo Ribalda <ribalda@kernel.org>; Robert Jones <rjones@gateworks.com>; Rui Miguel Silva <rui.silva@linaro.org>; Sean Nyekjaer <sean.nyekjaer@prevas.dk>; Tomas Melin <tomas.melin@vaisala.com>; Tomislav Denis <tomislav.denis@avl.com>; Uwe Kleine-König <u.kleine-koenig@pengutronix.de>; Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: [PATCH 78/92] iio: imu: icm42600: Fix alignment for DMA safety in buffer code. 
 
[CAUTION] This is EXTERNAL email. Do not click any links or open attachments unless you recognize the sender and know the content is safe.

======================================================================
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

Second fix for this driver due to different introducing patches.

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 7f85e42a6c54 ("iio: imu: inv_icm42600: add buffer support in iio devices")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
---
 drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h b/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h
index de2a3949dcc7..56545638bfcd 100644
--- a/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h
+++ b/drivers/iio/imu/inv_icm42600/inv_icm42600_buffer.h
@@ -39,7 +39,7 @@ struct inv_icm42600_fifo {
                 size_t accel;
                 size_t total;
         } nb;
-       uint8_t data[2080] ____cacheline_aligned;
+       uint8_t data[2080] __aligned(IIO_ALIGN);
 };
 
 /* FIFO data packet */
-- 
2.36.0

Re: [PATCH 79/92] iio: imu: mpu6050: Fix alignment for DMA safety

[Jean-Baptiste Maneyrol]

Acked-by: Jean-Baptiste Maneyrol <jean-baptiste.maneyrol@tdk.com>


From: Jonathan Cameron <jic23@kernel.org>
Sent: Tuesday, May 3, 2022 10:59
To: linux-iio@vger.kernel.org <linux-iio@vger.kernel.org>
Cc: Akinobu Mita <akinobu.mita@gmail.com>; Alexandru Lazar <alazar@startmail.com>; Alexandru Tachici <alexandru.tachici@analog.com>; Antoniu Miclaus <antoniu.miclaus@analog.com>; Charles-Antoine Couret <charles-antoine.couret@essensium.com>; Cosmin Tanislav <cosmin.tanislav@analog.com>; Cristian Pop <cristian.pop@analog.com>; David Lechner <david@lechnology.com>; Ivan Mikhaylov <i.mikhaylov@yadro.com>; Jacopo Mondi <jacopo+renesas@jmondi.org>; Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>; Lars-Peter Clausen <lars@metafoo.de>; Marcelo Schmitt <marcelo.schmitt1@gmail.com>; Mårten Lindahl <martenli@axis.com>; Matt Ranostay <mranostay@gmail.com>; Michael Hennerich <michael.hennerich@analog.com>; Michael Welling <mwelling@ieee.org>; Mugilraj Dhavachelvan <dmugil2000@gmail.com>; Navin Sankar Velliangiri <navin@linumiz.com>; Nuno Sá <nuno.sa@analog.com>; Paul Cercueil <paul@crapouillou.net>; Phil Reid <preid@electromag.com.au>; Puranjay Mohan <puranjay12@gmail.com>; Ricardo Ribalda <ribalda@kernel.org>; Robert Jones <rjones@gateworks.com>; Rui Miguel Silva <rui.silva@linaro.org>; Sean Nyekjaer <sean.nyekjaer@prevas.dk>; Tomas Melin <tomas.melin@vaisala.com>; Tomislav Denis <tomislav.denis@avl.com>; Uwe Kleine-König <u.kleine-koenig@pengutronix.de>; Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: [PATCH 79/92] iio: imu: mpu6050: Fix alignment for DMA safety 
 
[CAUTION] This is EXTERNAL email. Do not click any links or open attachments unless you recognize the sender and know the content is safe.

======================================================================
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_ALIGN definition.

Fixes: 6b0cc5dce072 ("iio:imu:inv_mpu6050 Fix dma and ts alignment and data leak issues.")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
---
 drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
index c6aa36ee966a..18bd1a50463c 100644
--- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
+++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
@@ -203,7 +203,7 @@ struct inv_mpu6050_state {
         s32 magn_raw_to_gauss[3];
         struct iio_mount_matrix magn_orient;
         unsigned int suspended_sensors;
-       u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] ____cacheline_aligned;
+       u8 data[INV_MPU6050_OUTPUT_DATA_SIZE] __aligned(IIO_ALIGN);
 };
 
 /*register and associated bit definition*/
-- 
2.36.0

Re: [PATCH 75/92] iio: gyro: fxas210002c: Fix alignment for DMA safety

[Rui Miguel Silva]

Hi Jonathan,
Thanks for fixing this.

On Tue, May 03, 2022 at 09:59:18AM +0100, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
> 
> Updated the comment to 'may' require.
> 
> Fixes: a0701b6263ae ("iio: gyro: add core driver for fxas21002c")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Rui Miguel Silva <rui.silva@linaro.org>

Reviewed-by: Rui Miguel Silva <rui.silva@linaro.org>

Cheers,
   Rui
> ---
>  drivers/iio/gyro/fxas21002c_core.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/iio/gyro/fxas21002c_core.c b/drivers/iio/gyro/fxas21002c_core.c
> index 410e5e9f2672..d89dab48956a 100644
> --- a/drivers/iio/gyro/fxas21002c_core.c
> +++ b/drivers/iio/gyro/fxas21002c_core.c
> @@ -150,10 +150,10 @@ struct fxas21002c_data {
>  	struct regulator *vddio;
>  
>  	/*
> -	 * DMA (thus cache coherency maintenance) requires the
> -	 * transfer buffers to live in their own cache lines.
> +	 * DMA (thus cache coherency maintenance) may require the
> +	 * transfer buffers live in their own cache lines.
>  	 */
> -	s16 buffer[8] ____cacheline_aligned;
> +	s16 buffer[8] __aligned(IIO_ALIGN);
>  };
>  
>  enum fxas21002c_channel_index {
> -- 
> 2.36.0
> 

Re: [PATCH 24/92] iio: adc: max11100: Fix alignment for DMA safety

[Jacopo Mondi]

Hi Jonathan,

On Tue, May 03, 2022 at 09:58:27AM +0100, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
>
> Update the comment to include 'may'.
>
> Fixes: a8e7e88df9ec ("iio: adc: Add Maxim MAX11100 driver")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Jacopo Mondi <jacopo+renesas@jmondi.org>

Thanks

Acked-by: Jacopo Mondi <jacopo@jmondi.org>

> ---
>  drivers/iio/adc/max11100.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/iio/adc/max11100.c b/drivers/iio/adc/max11100.c
> index eb1ce6a0315c..4766d45344f7 100644
> --- a/drivers/iio/adc/max11100.c
> +++ b/drivers/iio/adc/max11100.c
> @@ -33,10 +33,10 @@ struct max11100_state {
>  	struct spi_device *spi;
>
>  	/*
> -	 * DMA (thus cache coherency maintenance) requires the
> +	 * DMA (thus cache coherency maintenance) may require the
>  	 * transfer buffers to live in their own cache lines.
>  	 */
> -	u8 buffer[3] ____cacheline_aligned;
> +	u8 buffer[3] __aligned(IIO_ALIGN);
>  };
>
>  static const struct iio_chan_spec max11100_channels[] = {
> --
> 2.36.0
>

Re: [PATCH 02/92] iio: accel: adxl313: Fix alignment for DMA safety

[Lars-Peter Clausen]

On 5/3/22 10:58, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>
> ____cacheline_aligned is insufficient guarantee for non-coherent DMA.
> Switch to the update IIO_ALIGN definition.
>
> Fixes: 636d44633039 ("iio: accel: Add driver support for ADXL313")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>   drivers/iio/accel/adxl313_core.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/iio/accel/adxl313_core.c b/drivers/iio/accel/adxl313_core.c
> index 9e4193e64765..508fccbd4347 100644
> --- a/drivers/iio/accel/adxl313_core.c
> +++ b/drivers/iio/accel/adxl313_core.c
> @@ -46,7 +46,7 @@ EXPORT_SYMBOL_NS_GPL(adxl313_writable_regs_table, IIO_ADXL313);
>   struct adxl313_data {
>   	struct regmap	*regmap;
>   	struct mutex	lock; /* lock to protect transf_buf */
> -	__le16		transf_buf ____cacheline_aligned;
> +	__le16		transf_buf __aligned(IIO_ALIGN);
How about making __aligned(IIO_ALIGN) a macro in case we ever want to 
change it.
>   };
>   
>   static const int adxl313_odr_freqs[][2] = {

Re: [PATCH 26/92] iio: adc: max1241: Fix alignment for DMA safety

[Alexandru Lazar]

On 5/3/2022 11:58 AM, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
> 
> Fixes: 8a80a71d9020 ("iio: adc: Add MAX1241 driver")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Alexandru Lazar <alazar@startmail.com>
> ---
>   drivers/iio/adc/max1241.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/adc/max1241.c b/drivers/iio/adc/max1241.c
> index a5afd84af58b..e3dbcc2e4e77 100644
> --- a/drivers/iio/adc/max1241.c
> +++ b/drivers/iio/adc/max1241.c
> @@ -26,7 +26,7 @@ struct max1241 {
>   	struct regulator *vref;
>   	struct gpio_desc *shutdown;
>   
> -	__be16 data ____cacheline_aligned;
> +	__be16 data __aligned(IIO_ALIGN);
>   };
>   
>   static const struct iio_chan_spec max1241_channels[] = {

Looks good, I think we can call this

Acked-by: Alexandru Lazar <alazar@startmail.com>

Thanks!

In addition to that, I also think the changes in max1118 and max1027 are 
OK but I can't test either of them so take this with a grain of salt.

All the best,
Alex

(P.S. Fingers crossed that Thunderbird doesn't screw this up, I'm 
nowhere near my development machine for the next two weeks :-( . 
Apologies if it does!)

Re: [PATCH 01/92] iio: core: Fix IIO_ALIGN as it was not sufficiently large on some platforms.

[Uwe Kleine-König]

[-- Attachment #1: Type: text/plain, Size: 3174 bytes --]

On Tue, May 03, 2022 at 09:58:04AM +0100, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> Discussion of the series:
> https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/
> mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that
> our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm
> platforms out their with non coherent DMA and larger cache lines at
> at higher levels of their cache hierarchy.
> 
> Note this patch will greatly reduce the padding on some architectures
> that have smaller requirements for DMA safe buffers.
> 
> The history of changing values of ARCH_KMALLOC_MINALIGN via
> ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this
> as fixing a particular patch from that route as it's not clear what to tag.
> 
> Most recently a change to bring them back inline was reverted because
> of some Qualcomm Kryo cores with an L2 cache with 128-byte lines
> sitting above the point of coherency.
> 
> c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)"
> That reverts:
> 65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which
> refers to the change originally being motivated by Thunder x1 performance
> rather than correctness.
> 
> Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data space to iio_allocate_device")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> ---
>  include/linux/iio/iio.h | 10 ++++++++--
>  1 file changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h
> index faf00f2c0be6..30937f8f9424 100644
> --- a/include/linux/iio/iio.h
> +++ b/include/linux/iio/iio.h
> @@ -9,6 +9,7 @@
>  
>  #include <linux/device.h>
>  #include <linux/cdev.h>
> +#include <linux/slab.h>
>  #include <linux/iio/types.h>
>  #include <linux/of.h>
>  /* IIO TODO LIST */
> @@ -657,8 +658,13 @@ static inline void *iio_device_get_drvdata(const struct iio_dev *indio_dev)
>  	return dev_get_drvdata(&indio_dev->dev);
>  }
>  
> -/* Can we make this smaller? */
> -#define IIO_ALIGN L1_CACHE_BYTES
> +/*
> + * Used to ensure the iio_priv() structure is aligned to allow that structure
> + * to in turn include IIO_ALIGN'd elements such as buffers which must not share
> + * cachelines with the rest of the structure, thus making them safe for use with
> + * non-coherent DMA.
> + */
> +#define IIO_ALIGN ARCH_KMALLOC_MINALIGN

Given the purpose of IIO_ALIGN is to define the alignment for DMA'able
memory, I wonder why it's called "IIO_ALIGN" and not for example
"DMA_MINALIGN".

There is nothing iio specific about this value, is there? Then
consequently it doesn't need to be defined in an iio header, but
somewhere generic. Or even one step further: Why isn't there a macro
__align_for_dma that can be used directly to annotate the relevant
member in a struct?

Best regards
Uwe

-- 
Pengutronix e.K.                           | Uwe Kleine-König            |
Industrial Linux Solutions                 | https://www.pengutronix.de/ |

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Re: [PATCH 01/92] iio: core: Fix IIO_ALIGN as it was not sufficiently large on some platforms.

[Jonathan Cameron]

On Tue, 3 May 2022 16:27:25 +0200
Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote:

> On Tue, May 03, 2022 at 09:58:04AM +0100, Jonathan Cameron wrote:
> > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > 
> > Discussion of the series:
> > https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/
> > mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that
> > our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm
> > platforms out their with non coherent DMA and larger cache lines at
> > at higher levels of their cache hierarchy.
> > 
> > Note this patch will greatly reduce the padding on some architectures
> > that have smaller requirements for DMA safe buffers.
> > 
> > The history of changing values of ARCH_KMALLOC_MINALIGN via
> > ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this
> > as fixing a particular patch from that route as it's not clear what to tag.
> > 
> > Most recently a change to bring them back inline was reverted because
> > of some Qualcomm Kryo cores with an L2 cache with 128-byte lines
> > sitting above the point of coherency.
> > 
> > c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)"
> > That reverts:
> > 65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which
> > refers to the change originally being motivated by Thunder x1 performance
> > rather than correctness.
> > 
> > Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data space to iio_allocate_device")
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >  include/linux/iio/iio.h | 10 ++++++++--
> >  1 file changed, 8 insertions(+), 2 deletions(-)
> > 
> > diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h
> > index faf00f2c0be6..30937f8f9424 100644
> > --- a/include/linux/iio/iio.h
> > +++ b/include/linux/iio/iio.h
> > @@ -9,6 +9,7 @@
> >  
> >  #include <linux/device.h>
> >  #include <linux/cdev.h>
> > +#include <linux/slab.h>
> >  #include <linux/iio/types.h>
> >  #include <linux/of.h>
> >  /* IIO TODO LIST */
> > @@ -657,8 +658,13 @@ static inline void *iio_device_get_drvdata(const struct iio_dev *indio_dev)
> >  	return dev_get_drvdata(&indio_dev->dev);
> >  }
> >  
> > -/* Can we make this smaller? */
> > -#define IIO_ALIGN L1_CACHE_BYTES
> > +/*
> > + * Used to ensure the iio_priv() structure is aligned to allow that structure
> > + * to in turn include IIO_ALIGN'd elements such as buffers which must not share
> > + * cachelines with the rest of the structure, thus making them safe for use with
> > + * non-coherent DMA.
> > + */
> > +#define IIO_ALIGN ARCH_KMALLOC_MINALIGN  
> 
> Given the purpose of IIO_ALIGN is to define the alignment for DMA'able
> memory, I wonder why it's called "IIO_ALIGN" and not for example
> "DMA_MINALIGN".

Much like crypto I want a single place that provides the IIO requirements
for this.  Could rename it IIO_DMA_MINALIGN I guess.  The reason behind
that is to allow for a switch on mass if a new approach is accepted
along the lines of what Catalin proposed.  The discussions around
CRYPTO made it clear that there are sometimes additional requirements
from a subsystem beyond simply that of DMA (IIO has a similar issue
to crypto that mean it's not simple to shift the alignment requirements
at runtime because the compiler is getting told things are aligned to
a higher degree than the allocations).

https://lore.kernel.org/all/20220405135758.774016-8-catalin.marinas@arm.com/
and below that point.

> 
> There is nothing iio specific about this value, is there? Then
> consequently it doesn't need to be defined in an iio header, but
> somewhere generic. Or even one step further: Why isn't there a macro
> __align_for_dma that can be used directly to annotate the relevant
> member in a struct?

There is, but it's not currently available on all architectures.

ARCH_DMA_MINALIGN

Catalin's series proposed making it generally available:
https://lore.kernel.org/all/20220405135758.774016-2-catalin.marinas@arm.com/

but suggestion for now was to go with ARCH_KMALLOC_MINALIGN

https://lore.kernel.org/linux-iio/Yl6jB5DOUy+Yqyzl@arm.com/

Thanks,

Jonathan


> 
> Best regards
> Uwe
> 

Re: [PATCH 02/92] iio: accel: adxl313: Fix alignment for DMA safety

[Jonathan Cameron]

On Tue, 3 May 2022 15:11:26 +0200
Lars-Peter Clausen <lars@metafoo.de> wrote:

> On 5/3/22 10:58, Jonathan Cameron wrote:
> > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> >
> > ____cacheline_aligned is insufficient guarantee for non-coherent DMA.
> > Switch to the update IIO_ALIGN definition.
> >
> > Fixes: 636d44633039 ("iio: accel: Add driver support for ADXL313")
> > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > ---
> >   drivers/iio/accel/adxl313_core.c | 2 +-
> >   1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/iio/accel/adxl313_core.c b/drivers/iio/accel/adxl313_core.c
> > index 9e4193e64765..508fccbd4347 100644
> > --- a/drivers/iio/accel/adxl313_core.c
> > +++ b/drivers/iio/accel/adxl313_core.c
> > @@ -46,7 +46,7 @@ EXPORT_SYMBOL_NS_GPL(adxl313_writable_regs_table, IIO_ADXL313);
> >   struct adxl313_data {
> >   	struct regmap	*regmap;
> >   	struct mutex	lock; /* lock to protect transf_buf */
> > -	__le16		transf_buf ____cacheline_aligned;
> > +	__le16		transf_buf __aligned(IIO_ALIGN);  
> How about making __aligned(IIO_ALIGN) a macro in case we ever want to 
> change it.

Could do I suppose, though scripts are already getting confused enough
at __aligned() :( (Try running check patch on this series!)

That can be fixed but adds another step.

I also can't actually think of why we would want to change an
align force to something other than an align force.  The value of
IIO_ALIGN might well change of course.

Jonathan



> >   };
> >   
> >   static const int adxl313_odr_freqs[][2] = {  
> 
> 

Re: [PATCH 36/92] iio: adc: ti-ads7950: Fix alignment for DMA safety

[David Lechner]

On 5/3/22 3:58 AM, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
> 
> Update the comment to include 'may'.
> 
> Fixes: 902c4b2446d4 ("iio: adc: New driver for TI ADS7950 chips")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: David Lechner <david@lechnology.com>
> ---

Acked-by: David Lechner <david@lechnology.com>

Re: [PATCH 81/92] iio: potentiometer: ad5272: Fix alignment for DMA safety

[Phil Reid]

On 3/05/2022 16:59, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
> 
> Fixes: 79e8a32d2aa9 ("iio: ad5272: Add support for Analog Devices digital potentiometers")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Phil Reid <preid@electromag.com.au>

Reviewed-by: Phil Reid <preid@electromag.com.au>

> ---
>   drivers/iio/potentiometer/ad5272.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/potentiometer/ad5272.c b/drivers/iio/potentiometer/ad5272.c
> index d8cbd170262f..e023c0f92242 100644
> --- a/drivers/iio/potentiometer/ad5272.c
> +++ b/drivers/iio/potentiometer/ad5272.c
> @@ -50,7 +50,7 @@ struct ad5272_data {
>   	struct i2c_client       *client;
>   	struct mutex            lock;
>   	const struct ad5272_cfg *cfg;
> -	u8                      buf[2] ____cacheline_aligned;
> +	u8                      buf[2] __aligned(IIO_ALIGN);
>   };
>   
>   static const struct iio_chan_spec ad5272_channel = {


-- 
Regards
Phil Reid

Re: [PATCH 29/92] iio: adc: ti-adc084s021: Fix alignment for DMA safety

[Marten Lindahl]

On Tue, May 03, 2022 at 10:58:32AM +0200, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
> 
> Update the comment to include 'may'.
> 
> Fixes: 3691e5a69449 ("iio: adc: add driver for the ti-adc084s021 chip")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Mårten Lindahl <martenli@axis.com>

Acked-by: Mårten Lindahl <marten.lindahl@axis.com>

> ---
>  drivers/iio/adc/ti-adc084s021.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/iio/adc/ti-adc084s021.c b/drivers/iio/adc/ti-adc084s021.c
> index c9b5d9aec3dc..6464541319af 100644
> --- a/drivers/iio/adc/ti-adc084s021.c
> +++ b/drivers/iio/adc/ti-adc084s021.c
> @@ -32,10 +32,10 @@ struct adc084s021 {
>  		s64 ts __aligned(8);
>  	} scan;
>  	/*
> -	 * DMA (thus cache coherency maintenance) requires the
> +	 * DMA (thus cache coherency maintenance) may require the
>  	 * transfer buffers to live in their own cache line.
>  	 */
> -	u16 tx_buf[4] ____cacheline_aligned;
> +	u16 tx_buf[4] __aligned(IIO_ALIGN);
>  	__be16 rx_buf[5]; /* First 16-bits are trash */
>  };
>  
> -- 
> 2.36.0
> 

RE: [PATCH 00/92] IIO: Fix alignment of buffers for DMA

[Sa, Nuno]

Hi Jonathan,

> From: Jonathan Cameron <jic23@kernel.org>
> Sent: Tuesday, May 3, 2022 10:58 AM
> To: linux-iio@vger.kernel.org
> Cc: Akinobu Mita <akinobu.mita@gmail.com>; Alexandru Lazar
> <alazar@startmail.com>; Tachici, Alexandru
> <Alexandru.Tachici@analog.com>; Miclaus, Antoniu
> <Antoniu.Miclaus@analog.com>; Charles-Antoine Couret <charles-
> antoine.couret@essensium.com>; Tanislav, Cosmin
> <Cosmin.Tanislav@analog.com>; Cristian Pop
> <cristian.pop@analog.com>; David Lechner <david@lechnology.com>;
> Ivan Mikhaylov <i.mikhaylov@yadro.com>; Jacopo Mondi
> <jacopo+renesas@jmondi.org>; Jean-Baptiste Maneyrol
> <jmaneyrol@invensense.com>; Lars-Peter Clausen
> <lars@metafoo.de>; Marcelo Schmitt <marcelo.schmitt1@gmail.com>;
> Mårten Lindahl <martenli@axis.com>; Matt Ranostay
> <mranostay@gmail.com>; Hennerich, Michael
> <Michael.Hennerich@analog.com>; Michael Welling
> <mwelling@ieee.org>; Mugilraj Dhavachelvan
> <dmugil2000@gmail.com>; Navin Sankar Velliangiri
> <navin@linumiz.com>; Sa, Nuno <Nuno.Sa@analog.com>; Paul
> Cercueil <paul@crapouillou.net>; Phil Reid
> <preid@electromag.com.au>; Puranjay Mohan
> <puranjay12@gmail.com>; Ricardo Ribalda <ribalda@kernel.org>;
> Robert Jones <rjones@gateworks.com>; Rui Miguel Silva
> <rui.silva@linaro.org>; Sean Nyekjaer <sean.nyekjaer@prevas.dk>;
> Tomas Melin <tomas.melin@vaisala.com>; Tomislav Denis
> <tomislav.denis@avl.com>; Uwe Kleine-König <u.kleine-
> koenig@pengutronix.de>; Jonathan Cameron
> <Jonathan.Cameron@huawei.com>; catalin.marinas@arm.com
> Subject: [PATCH 00/92] IIO: Fix alignment of buffers for DMA
> 
> [External]
> 
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> Many years ago, IIO started using ____cacheline_aligned to ensure
> that buffers that might be used for DMA were not sharing a cacheline
> with other data that might lead to DMA safety issues.
> 
> As it turns out, that was fine at the time, but not based on the
> correct alignment requirement (though I believe it was a conservative
> choice at the time).  Note that on many architectures this was
> introducing
> unecessary padding.  We should have been using
> ARCH_KMALLOC_MINALIGN
> as other subsystems such as crypto have done for a long time.
> 
> Patch 1 discription contains more information but in short, there are
> ARM64 SoCs out their that have a larger cachline size for caches
> beyond
> L1. In many cases they maintain coherency for all DMA devices
> attached
> and so this isn't a problem, but there are exceptions that do not.
> 
> So, this is a rather large patch set and just covers those drivers
> that are in the last kernel release and in drivers/iio.
> 
> Many of these drivers are somewhat old so I haven't specifically
> cc'd anyone so will be relying on those kind enough to sanity check
> patches on drivers that are beyond their own.
> 
> Given there is ongoing discussion around reducing the alignment
> requirements where possible, I've adopted the existing IIO_ALIGN
> define througout.  That way we have a single point to update if
> that becomes relevant in future.
> 

Nice to see this in... Since we are here, I guess in a couple of patches where we have:

struct {
	...
	u8 rx[] __aligned();
	u8 tx[] __aligned();
};

we could make it such that only the first member is aligned. But bah, I get that this
is already a huge patchset to diverge from it. Anyhow,

Acked-by: Nuno Sá <nuno.sa@analog.com>

Re: [PATCH 00/92] IIO: Fix alignment of buffers for DMA

[Jonathan Cameron]

On Wed, 4 May 2022 13:00:58 +0000
"Sa, Nuno" <Nuno.Sa@analog.com> wrote:

> Hi Jonathan,
> 
> > From: Jonathan Cameron <jic23@kernel.org>
> > Sent: Tuesday, May 3, 2022 10:58 AM
> > To: linux-iio@vger.kernel.org
> > Cc: Akinobu Mita <akinobu.mita@gmail.com>; Alexandru Lazar
> > <alazar@startmail.com>; Tachici, Alexandru
> > <Alexandru.Tachici@analog.com>; Miclaus, Antoniu
> > <Antoniu.Miclaus@analog.com>; Charles-Antoine Couret <charles-  
> > antoine.couret@essensium.com>; Tanislav, Cosmin  
> > <Cosmin.Tanislav@analog.com>; Cristian Pop
> > <cristian.pop@analog.com>; David Lechner <david@lechnology.com>;
> > Ivan Mikhaylov <i.mikhaylov@yadro.com>; Jacopo Mondi
> > <jacopo+renesas@jmondi.org>; Jean-Baptiste Maneyrol
> > <jmaneyrol@invensense.com>; Lars-Peter Clausen
> > <lars@metafoo.de>; Marcelo Schmitt <marcelo.schmitt1@gmail.com>;
> > Mårten Lindahl <martenli@axis.com>; Matt Ranostay
> > <mranostay@gmail.com>; Hennerich, Michael
> > <Michael.Hennerich@analog.com>; Michael Welling
> > <mwelling@ieee.org>; Mugilraj Dhavachelvan
> > <dmugil2000@gmail.com>; Navin Sankar Velliangiri
> > <navin@linumiz.com>; Sa, Nuno <Nuno.Sa@analog.com>; Paul
> > Cercueil <paul@crapouillou.net>; Phil Reid
> > <preid@electromag.com.au>; Puranjay Mohan
> > <puranjay12@gmail.com>; Ricardo Ribalda <ribalda@kernel.org>;
> > Robert Jones <rjones@gateworks.com>; Rui Miguel Silva
> > <rui.silva@linaro.org>; Sean Nyekjaer <sean.nyekjaer@prevas.dk>;
> > Tomas Melin <tomas.melin@vaisala.com>; Tomislav Denis
> > <tomislav.denis@avl.com>; Uwe Kleine-König <u.kleine-  
> > koenig@pengutronix.de>; Jonathan Cameron  
> > <Jonathan.Cameron@huawei.com>; catalin.marinas@arm.com
> > Subject: [PATCH 00/92] IIO: Fix alignment of buffers for DMA
> > 
> > [External]
> > 
> > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > 
> > Many years ago, IIO started using ____cacheline_aligned to ensure
> > that buffers that might be used for DMA were not sharing a cacheline
> > with other data that might lead to DMA safety issues.
> > 
> > As it turns out, that was fine at the time, but not based on the
> > correct alignment requirement (though I believe it was a conservative
> > choice at the time).  Note that on many architectures this was
> > introducing
> > unecessary padding.  We should have been using
> > ARCH_KMALLOC_MINALIGN
> > as other subsystems such as crypto have done for a long time.
> > 
> > Patch 1 discription contains more information but in short, there are
> > ARM64 SoCs out their that have a larger cachline size for caches
> > beyond
> > L1. In many cases they maintain coherency for all DMA devices
> > attached
> > and so this isn't a problem, but there are exceptions that do not.
> > 
> > So, this is a rather large patch set and just covers those drivers
> > that are in the last kernel release and in drivers/iio.
> > 
> > Many of these drivers are somewhat old so I haven't specifically
> > cc'd anyone so will be relying on those kind enough to sanity check
> > patches on drivers that are beyond their own.
> > 
> > Given there is ongoing discussion around reducing the alignment
> > requirements where possible, I've adopted the existing IIO_ALIGN
> > define througout.  That way we have a single point to update if
> > that becomes relevant in future.
> >   
> 
> Nice to see this in... Since we are here, I guess in a couple of patches where we have:
> 
> struct {
> 	...
> 	u8 rx[] __aligned();
> 	u8 tx[] __aligned();
> };
> 
> we could make it such that only the first member is aligned. But bah, I get that this
> is already a huge patchset to diverge from it. Anyhow,

Yup. I thought about tidying those up but decided it would just make
things harder to explain so could be done as a follow up.
I should have said so in the cover letter though!

I particularly like the case where (a long time ago) I added
a question on whether there was a need for separate alignment
and left that question in the final code. Oops.
> 
> Acked-by: Nuno Sá <nuno.sa@analog.com>

Thanks for looking through all these.

We haven't yet concluded on the questions of naming and possible
additional define for __aligned(XXX) but if we do make such a change
it should be purely mechanical hence I'll keep all the tags people
have given and not bother them again :)

Thanks,

Jonathan

Re: [PATCH 11/92] iio: adc: ad7292: Fix alignment for DMA safety

[Marcelo Schmitt]

On 05/03, Jonathan Cameron wrote:
> From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> 
> ____cacheline_aligned is an insufficient guarantee for non-coherent DMA
> on platforms with 128 byte cachelines above L1.  Switch to the updated
> IIO_ALIGN definition.
> 
> Fixes: 506d2e317a0a ("iio: adc: Add driver support for AD7292")
> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> Cc: Marcelo Schmitt <marcelo.schmitt1@gmail.com>

Acked-by: Marcelo Schmitt <marcelo.schmitt1@gmail.com>

Thanks,
Marcelo

> ---
>  drivers/iio/adc/ad7292.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/iio/adc/ad7292.c b/drivers/iio/adc/ad7292.c
> index 3271a31afde1..08985fc5c200 100644
> --- a/drivers/iio/adc/ad7292.c
> +++ b/drivers/iio/adc/ad7292.c
> @@ -80,7 +80,7 @@ struct ad7292_state {
>  	struct regulator *reg;
>  	unsigned short vref_mv;
>  
> -	__be16 d16 ____cacheline_aligned;
> +	__be16 d16 __aligned(IIO_ALIGN);
>  	u8 d8[2];
>  };
>  
> -- 
> 2.36.0
> 

Re: [PATCH 01/92] iio: core: Fix IIO_ALIGN as it was not sufficiently large on some platforms.

[Jonathan Cameron]

On Tue, 3 May 2022 17:24:21 +0100
Jonathan Cameron <Jonathan.Cameron@Huawei.com> wrote:

> On Tue, 3 May 2022 16:27:25 +0200
> Uwe Kleine-König <u.kleine-koenig@pengutronix.de> wrote:
> 
> > On Tue, May 03, 2022 at 09:58:04AM +0100, Jonathan Cameron wrote:  
> > > From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > 
> > > Discussion of the series:
> > > https://lore.kernel.org/all/20220405135758.774016-1-catalin.marinas@arm.com/
> > > mm, arm64: Reduce ARCH_KMALLOC_MINALIGN brought to my attention that
> > > our current IIO usage of L1CACHE_ALIGN is insufficient as their are Arm
> > > platforms out their with non coherent DMA and larger cache lines at
> > > at higher levels of their cache hierarchy.
> > > 
> > > Note this patch will greatly reduce the padding on some architectures
> > > that have smaller requirements for DMA safe buffers.
> > > 
> > > The history of changing values of ARCH_KMALLOC_MINALIGN via
> > > ARCH_DMA_MINALIGN on arm64 is rather complex. I'm not tagging this
> > > as fixing a particular patch from that route as it's not clear what to tag.
> > > 
> > > Most recently a change to bring them back inline was reverted because
> > > of some Qualcomm Kryo cores with an L2 cache with 128-byte lines
> > > sitting above the point of coherency.
> > > 
> > > c1132702c71f Revert "arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)"
> > > That reverts:
> > > 65688d2a05de arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES) which
> > > refers to the change originally being motivated by Thunder x1 performance
> > > rather than correctness.
> > > 
> > > Fixes: 6f7c8ee585e9d ("staging:iio: Add ability to allocate private data space to iio_allocate_device")
> > > Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
> > > ---
> > >  include/linux/iio/iio.h | 10 ++++++++--
> > >  1 file changed, 8 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/include/linux/iio/iio.h b/include/linux/iio/iio.h
> > > index faf00f2c0be6..30937f8f9424 100644
> > > --- a/include/linux/iio/iio.h
> > > +++ b/include/linux/iio/iio.h
> > > @@ -9,6 +9,7 @@
> > >  
> > >  #include <linux/device.h>
> > >  #include <linux/cdev.h>
> > > +#include <linux/slab.h>
> > >  #include <linux/iio/types.h>
> > >  #include <linux/of.h>
> > >  /* IIO TODO LIST */
> > > @@ -657,8 +658,13 @@ static inline void *iio_device_get_drvdata(const struct iio_dev *indio_dev)
> > >  	return dev_get_drvdata(&indio_dev->dev);
> > >  }
> > >  
> > > -/* Can we make this smaller? */
> > > -#define IIO_ALIGN L1_CACHE_BYTES
> > > +/*
> > > + * Used to ensure the iio_priv() structure is aligned to allow that structure
> > > + * to in turn include IIO_ALIGN'd elements such as buffers which must not share
> > > + * cachelines with the rest of the structure, thus making them safe for use with
> > > + * non-coherent DMA.
> > > + */
> > > +#define IIO_ALIGN ARCH_KMALLOC_MINALIGN    
> > 
> > Given the purpose of IIO_ALIGN is to define the alignment for DMA'able
> > memory, I wonder why it's called "IIO_ALIGN" and not for example
> > "DMA_MINALIGN".  
> 
> Much like crypto I want a single place that provides the IIO requirements
> for this.  Could rename it IIO_DMA_MINALIGN I guess. 

I've switched to this naming for v2.

> The reason behind
> that is to allow for a switch on mass if a new approach is accepted
> along the lines of what Catalin proposed.  The discussions around
> CRYPTO made it clear that there are sometimes additional requirements
> from a subsystem beyond simply that of DMA (IIO has a similar issue
> to crypto that mean it's not simple to shift the alignment requirements
> at runtime because the compiler is getting told things are aligned to
> a higher degree than the allocations).
> 
> https://lore.kernel.org/all/20220405135758.774016-8-catalin.marinas@arm.com/
> and below that point.
> 
> > 
> > There is nothing iio specific about this value, is there? Then
> > consequently it doesn't need to be defined in an iio header, but
> > somewhere generic. Or even one step further: Why isn't there a macro
> > __align_for_dma that can be used directly to annotate the relevant
> > member in a struct?  
> 
> There is, but it's not currently available on all architectures.
> 
> ARCH_DMA_MINALIGN
> 
> Catalin's series proposed making it generally available:
> https://lore.kernel.org/all/20220405135758.774016-2-catalin.marinas@arm.com/
> 
> but suggestion for now was to go with ARCH_KMALLOC_MINALIGN
> 
> https://lore.kernel.org/linux-iio/Yl6jB5DOUy+Yqyzl@arm.com/
> 
> Thanks,
> 
> Jonathan
> 
> 
> > 
> > Best regards
> > Uwe
> >   
>