From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shreyansh Jain Subject: Re: [PATCH v5 0/3] Introduce Intel FPGA BUS Date: Wed, 4 Apr 2018 10:14:22 +0000 Message-ID: References: <1521553556-62982-1-git-send-email-rosen.xu@intel.com> <1522824677-86958-1-git-send-email-rosen.xu@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Cc: "declan.doherty@intel.com" , "bruce.richardson@intel.com" , "ferruh.yigit@intel.com" , "konstantin.ananyev@intel.com" , "tianfei.zhang@intel.com" , "hao.wu@intel.com" , "gaetan.rivet@6wind.com" To: Rosen Xu , "dev@dpdk.org" Return-path: Received: from EUR03-DB5-obe.outbound.protection.outlook.com (mail-eopbgr40088.outbound.protection.outlook.com [40.107.4.88]) by dpdk.org (Postfix) with ESMTP id B2DCA1BDA8 for ; Wed, 4 Apr 2018 12:14:27 +0200 (CEST) In-Reply-To: <1522824677-86958-1-git-send-email-rosen.xu@intel.com> Content-Language: en-US List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hello Rosen, > -----Original Message----- > From: Rosen Xu [mailto:rosen.xu@intel.com] > Sent: Wednesday, April 4, 2018 12:21 PM > To: dev@dpdk.org > Cc: declan.doherty@intel.com; bruce.richardson@intel.com; Shreyansh Jain > ; ferruh.yigit@intel.com; > konstantin.ananyev@intel.com; tianfei.zhang@intel.com; hao.wu@intel.com; > gaetan.rivet@6wind.com > Subject: [PATCH v5 0/3] Introduce Intel FPGA BUS >=20 > Intel FPGA BUS in DPDK > ------------------------- >=20 > This patch set introduces Intel FPGA BUS support in DPDK. >=20 > v5 updates: > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > - Fixed SHARED LIB Build issue > - Changed command name to IFPGA Rawdev name, > so remove pci library datastruct and function. > - Fixed PATCH v2/v3/v4 comments >=20 [...] Primary problems I see with your patches: 1. They are not split enough. Still the patch 2/3 is dependent on 3/3. That= mean, it would break the compilation. There is no simpler way to solve thi= s except breaking the patch into multiple patches and slowly introducing ea= ch function/feature. (One obvious way would be to have 3/3 as 2/3 and vice-versa - Not sure wha= t that blocks). 2. Documentation - there is none right now. Being a special use case for PC= I, I think a lot of people would benefit if you can explain the comments ab= out why iFPGA bus is required through documentation. 3. Meson as requested by Bruce. Problem you will face is that rawdev doesn'= t yet have meson enabled. I will work on that. If you can still rework your= patches for (1)+(2), I think meson enable over rawdev would be trivial. Other issues being license plate in opae code not being SPDX. But, I will l= eave that you and maintainers to decice.