From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751434AbdFAIea (ORCPT ); Thu, 1 Jun 2017 04:34:30 -0400 Received: from mail-he1eur01on0069.outbound.protection.outlook.com ([104.47.0.69]:30144 "EHLO EUR01-HE1-obe.outbound.protection.outlook.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751036AbdFAIe2 (ORCPT ); Thu, 1 Jun 2017 04:34:28 -0400 From: Andy Tang To: Stephen Boyd CC: "mturquette@baylibre.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Scott Wood Subject: RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a Thread-Topic: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a Thread-Index: AQHSoSTypYwKVtOtGEe6GtD2noLhsqIQH7AAgAAA0SA= Date: Thu, 1 Jun 2017 08:34:24 +0000 Message-ID: References: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> <1489977443-33582-2-git-send-email-andy.tang@nxp.com> <20170601082804.GE20170@codeaurora.org> In-Reply-To: <20170601082804.GE20170@codeaurora.org> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: codeaurora.org; dkim=none (message not signed) header.d=none;codeaurora.org; dmarc=none action=none header.from=nxp.com; x-originating-ip: [192.158.241.86] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;HE1PR0402MB2828;7:TOz3BWL+i/UQPxzf0MixayFWgOkayOOWKfRYObPQX/hC3BZE2SCv0ae92iD3NlF5GF9vAE2XtmoPgY8XJ+Ntl6biLvW4uKNO9CiZKWCt8AM7oLv52SZPtRINKDUO0M6gVISTWfc/mev9YSep8wLgAinZ2wcfeyUdQ2jaPYVWRgOionxtk19lAfnlOElQCYSVo7OFQRY5x/5SCUJRwhlSM0yFfBm4S8GyTAdE2lBIyYDBv78aOFh85Mte3/K669oTgEYwnAYcd+H523uxkSfi/D+IhnG71s8Z362Mzg2oKjqgRVM2nQCR6Kt+ollwf/pxOVf5H52IgUAvasAF65CaGQ== x-ms-traffictypediagnostic: HE1PR0402MB2828: x-ms-office365-filtering-correlation-id: c3c65320-206c-43ba-1e8a-08d4a8c90262 x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: UriScan:;BCL:0;PCL:0;RULEID:(22001)(2017030254075)(48565401081)(201703131423075)(201703031133081);SRVR:HE1PR0402MB2828; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917)(9452136761055)(185117386973197)(258649278758335); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(100000700087)(100105000095)(100000701087)(100105300095)(100000702087)(100105100095)(6040450)(601004)(2401047)(5005006)(8121501046)(3002001)(100000703087)(100105400095)(10201501046)(93006095)(93001095)(6055026)(6041248)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123555025)(20161123564025)(20161123558100)(20161123560025)(20161123562025)(6072148)(100000704087)(100105200095)(100000705087)(100105500095);SRVR:HE1PR0402MB2828;BCL:0;PCL:0;RULEID:(100000800087)(100110000095)(100000801087)(100110300095)(100000802087)(100110100095)(100000803087)(100110400095)(100000804087)(100110200095)(100000805087)(100110500095);SRVR:HE1PR0402MB2828; x-forefront-prvs: 0325F6C77B x-forefront-antispam-report: SFV:NSPM;SFS:(10009020)(6009001)(39850400002)(39410400002)(39400400002)(39860400002)(39840400002)(39450400003)(377454003)(24454002)(13464003)(4326008)(53936002)(2950100002)(6436002)(76176999)(229853002)(189998001)(55016002)(50986999)(54906002)(3280700002)(2906002)(53546009)(3660700001)(6506006)(25786009)(99286003)(966005)(6916009)(14454004)(478600001)(86362001)(8936002)(6116002)(2900100001)(3846002)(6246003)(110136004)(8676002)(33656002)(38730400002)(5250100002)(5660300001)(74316002)(66066001)(9686003)(102836003)(7696004)(7736002)(81166006)(6306002)(305945005)(54356999);DIR:OUT;SFP:1101;SCL:1;SRVR:HE1PR0402MB2828;H:HE1PR0402MB2828.eurprd04.prod.outlook.com;FPR:;SPF:None;MLV:sfv;LANG:en; spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Jun 2017 08:34:24.6397 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-Transport-CrossTenantHeadersStamped: HE1PR0402MB2828 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id v518Yn84004752 Hi Stephen, Thanks for your applying. There are other two patches sent on April 6, 2017: https://patchwork.kernel.org/patch/9665973/ https://patchwork.kernel.org/patch/9665977/ Hope they are in your review queue. Please give it a review. Regards, Andy -----Original Message----- From: Stephen Boyd [mailto:sboyd@codeaurora.org] Sent: Thursday, June 01, 2017 4:28 PM To: Andy Tang Cc: mturquette@baylibre.com; robh+dt@kernel.org; mark.rutland@arm.com; linux-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Scott Wood Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a On 03/20, Yuantian Tang wrote: > From: Scott Wood > > ls1012a has separate input root clocks for core PLLs versus the > platform PLL, with the latter described as sysclk in the hw docs. > If a second input clock, named "coreclk", is present, this clock will > be used for the core PLLs. > > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > Acked-by: Rob Herring > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Tang Subject: RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a Date: Thu, 1 Jun 2017 08:34:24 +0000 Message-ID: References: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> <1489977443-33582-2-git-send-email-andy.tang@nxp.com> <20170601082804.GE20170@codeaurora.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Return-path: In-Reply-To: <20170601082804.GE20170@codeaurora.org> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Stephen Boyd Cc: "mturquette@baylibre.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Scott Wood List-Id: devicetree@vger.kernel.org Hi Stephen, Thanks for your applying. There are other two patches sent on April 6, 2017: https://patchwork.kernel.org/patch/9665973/ https://patchwork.kernel.org/patch/9665977/ Hope they are in your review queue. Please give it a review. Regards, Andy -----Original Message----- From: Stephen Boyd [mailto:sboyd@codeaurora.org]=20 Sent: Thursday, June 01, 2017 4:28 PM To: Andy Tang Cc: mturquette@baylibre.com; robh+dt@kernel.org; mark.rutland@arm.com; linu= x-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel= .org; linux-arm-kernel@lists.infradead.org; Scott Wood Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core = PLLs on ls1012a On 03/20, Yuantian Tang wrote: > From: Scott Wood >=20 > ls1012a has separate input root clocks for core PLLs versus the=20 > platform PLL, with the latter described as sysclk in the hw docs. > If a second input clock, named "coreclk", is present, this clock will=20 > be used for the core PLLs. >=20 > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > Acked-by: Rob Herring > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux = Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Andy Tang To: Stephen Boyd CC: "mturquette@baylibre.com" , "robh+dt@kernel.org" , "mark.rutland@arm.com" , "linux-clk@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Scott Wood Subject: RE: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a Date: Thu, 1 Jun 2017 08:34:24 +0000 Message-ID: References: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> <1489977443-33582-2-git-send-email-andy.tang@nxp.com> <20170601082804.GE20170@codeaurora.org> In-Reply-To: <20170601082804.GE20170@codeaurora.org> Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 List-ID: Hi Stephen, Thanks for your applying. There are other two patches sent on April 6, 2017: https://patchwork.kernel.org/patch/9665973/ https://patchwork.kernel.org/patch/9665977/ Hope they are in your review queue. Please give it a review. Regards, Andy -----Original Message----- From: Stephen Boyd [mailto:sboyd@codeaurora.org]=20 Sent: Thursday, June 01, 2017 4:28 PM To: Andy Tang Cc: mturquette@baylibre.com; robh+dt@kernel.org; mark.rutland@arm.com; linu= x-clk@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel= .org; linux-arm-kernel@lists.infradead.org; Scott Wood Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core = PLLs on ls1012a On 03/20, Yuantian Tang wrote: > From: Scott Wood >=20 > ls1012a has separate input root clocks for core PLLs versus the=20 > platform PLL, with the latter described as sysclk in the hw docs. > If a second input clock, named "coreclk", is present, this clock will=20 > be used for the core PLLs. >=20 > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > Acked-by: Rob Herring > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux = Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 From: andy.tang@nxp.com (Andy Tang) Date: Thu, 1 Jun 2017 08:34:24 +0000 Subject: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a In-Reply-To: <20170601082804.GE20170@codeaurora.org> References: <1489977443-33582-1-git-send-email-andy.tang@nxp.com> <1489977443-33582-2-git-send-email-andy.tang@nxp.com> <20170601082804.GE20170@codeaurora.org> Message-ID: To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Stephen, Thanks for your applying. There are other two patches sent on April 6, 2017: https://patchwork.kernel.org/patch/9665973/ https://patchwork.kernel.org/patch/9665977/ Hope they are in your review queue. Please give it a review. Regards, Andy -----Original Message----- From: Stephen Boyd [mailto:sboyd at codeaurora.org] Sent: Thursday, June 01, 2017 4:28 PM To: Andy Tang Cc: mturquette at baylibre.com; robh+dt at kernel.org; mark.rutland at arm.com; linux-clk at vger.kernel.org; devicetree at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm-kernel at lists.infradead.org; Scott Wood Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core PLLs on ls1012a On 03/20, Yuantian Tang wrote: > From: Scott Wood > > ls1012a has separate input root clocks for core PLLs versus the > platform PLL, with the latter described as sysclk in the hw docs. > If a second input clock, named "coreclk", is present, this clock will > be used for the core PLLs. > > Signed-off-by: Scott Wood > Signed-off-by: Tang Yuantian > Acked-by: Rob Herring > --- Applied to clk-next -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project