From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Kuusisaari, Juhamatti" Subject: Re: [PATCH] lib: move rte_ring read barrier to correct location Date: Tue, 12 Jul 2016 04:10:59 +0000 Message-ID: References: <20160711102055.14855-1-juhamatti.kuusisaari@coriant.com> <2601191342CEEE43887BDE71AB97725836B7C858@irsmsx105.ger.corp.intel.com> <5837bceb-070e-76d4-d548-8d5e9f1cce32@6wind.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable To: Olivier Matz , "Ananyev, Konstantin" , "dev@dpdk.org" Return-path: Received: from EUR01-DB5-obe.outbound.protection.outlook.com (mail-db5eur01on0044.outbound.protection.outlook.com [104.47.2.44]) by dpdk.org (Postfix) with ESMTP id B27172BA1 for ; Tue, 12 Jul 2016 06:11:01 +0200 (CEST) In-Reply-To: <5837bceb-070e-76d4-d548-8d5e9f1cce32@6wind.com> Content-Language: en-US List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Hello, > >>> -----Original Message----- > >>> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Juhamatti > >>> Kuusisaari > >>> Sent: Monday, July 11, 2016 11:21 AM > >>> To: dev@dpdk.org > >>> Subject: [dpdk-dev] [PATCH] lib: move rte_ring read barrier to > >>> correct location > >>> > >>> Fix the location of the rte_ring data dependency read barrier. > >>> It needs to be called before accessing indexed data to ensure that > >>> the data itself is guaranteed to be correctly updated. > >>> > >>> See more details at kernel/Documentation/memory-barriers.txt > >>> section 'Data dependency barriers'. > >> > >> > >> Any explanation why? > >> From my point smp_rmb()s are on the proper places here :) Konstantin > > > > The problem here is that on a weak memory model system the CPU is > > allowed to load the address data out-of-order in advance. > > If the read barrier is after the DEQUEUE, you might end up having the > > old data there on a race situation when the buffer is continuously full= . > > Having it before the DEQUEUE guarantees that the load is not done in > > advance. > > > > On Intel, it should not matter due to different memory model, so this > > is limited to weak memory model systems. >=20 >=20 > I agree with Juhamatti. To me, the reading of consumer_head must occur > before the reading of objects ptrs. >=20 > That was the case before, and this is something I already noticed when I = sent > that mail: > http://dpdk.org/ml/archives/dev/2014-March/001742.html >=20 > At that time, only Intel CPUs were supported, so it did not make any > difference. >=20 > Juhamatti, do you have a setup where you can trigger the issue or is it > something you've seen by code review? This was found on a code review when we investigated a problem that could h= ave=20 caused issues that this kind of bug would introduce. I suppose one would be= =20 able to see this with very short ring queue lengths and high load, but it d= epends on the HW used of course too.=20 BR, -- Juhamatti > Thanks, > Olivier