From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jacky Bai <ping.bai-3arQi8VN3Tc@public.gmane.org>
Subject: RE: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
Date: Fri, 2 Feb 2018 08:13:56 +0000
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References: <20180201183126.32384-1-l.stach@pengutronix.de>
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To: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>, Shawn Guo <shawnguo-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
Cc: Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>, Mark Rutland <mark.rutland-5wv7dgnIgG8@public.gmane.org>, Catalin Marinas <catalin.marinas-5wv7dgnIgG8@public.gmane.org>, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>, Fabio Estevam <fabio.estevam-3arQi8VN3Tc@public.gmane.org>, dl-linux-imx <linux-imx-3arQi8VN3Tc@public.gmane.org>, "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" <devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>, "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>, "kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org" <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>, "patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org" <patchwork-lst-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>, "A.s. Dong" <aisheng.dong-3arQi8VN3Tc@public.gmane.org>, Baruch Siach <baruch-NswTu9S1W3P6gbPvEgmw2w@public.gmane.org>
List-Id: devicetree@vger.kernel.org

> Subject: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
>=20
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
>=20
> This is enough to get a very basic board support up and running.
>=20
> One known limitation is that the driver for the GPC interrupt
> controller is still missing, rendering the CPU sleep states unusable
> as there is nothing waking them up anymore. This will be fixed in
> due course.
>=20

The cpu sleep states can NOT be supported in community kernel due to hardwa=
re limitation.

BR
Jacky Bai
> Signed-off-by: Lucas Stach <l.stach-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> ---
> v2:
>  - move to freescale folder
>  - change compatibles to "fsl" vendor prefix
>  - remove unnecessary newlines
>  - move status property to be the last in all node
>  - remove imx21 compatibles from UART nodes
>  - document compatible
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt  |   4 +
>  arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623
> +++++++++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi      | 411 ++++++++++++++++
>  3 files changed, 1038 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8mq.dtsi
>=20
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> b/Documentation/devicetree/bindings/arm/fsl.txt
> index cdb9dd705754..85d1c9ec6fa3 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -75,6 +75,10 @@ i.MX6q generic board
>  Required root node properties:
>      - compatible =3D "fsl,imx6q";
>=20
> +i.MX8MQ generic board
> +Required root node properties:
> +    - compatible =3D "fsl,imx8mq";
> +
>  Freescale Vybrid Platform Device Tree Bindings
>  ----------------------------------------------
>=20
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> new file mode 100644
> index 000000000000..b94b02080a34
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> @@ -0,0 +1,623 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017 NXP
> + */
> +
> +#ifndef __DTS_IMX8MQ_PINFUNC_H
> +#define __DTS_IMX8MQ_PINFUNC_H
> +
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +
> +#define
> MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ
> 0x014 0x27C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ
> 0x018 0x280 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF
> 0x01C 0x284 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B
> 0x020 0x288 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B
> 0x024 0x28C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0
> 0x028 0x290 0x000 0x0 0x0
> +#define
> MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT
> 0x028 0x290 0x4C0 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> 0x028 0x290 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1
> 0x028 0x290 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL
> 0x028 0x290 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1
> 0x02C 0x294 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT
> 0x02C 0x294 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M
> 0x02C 0x294 0x4BC 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2
> 0x02C 0x294 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE
> 0x02C 0x294 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2
> 0x030 0x298 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
> 0x030 0x298 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY
> 0x030 0x298 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B
> 0x030 0x298 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3
> 0x034 0x29C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT
> 0x034 0x29C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0
> 0x034 0x29C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK
> 0x034 0x29C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE
> 0x034 0x29C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4
> 0x038 0x2A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> 0x038 0x2A0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1
> 0x038 0x2A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV
> 0x038 0x2A0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG
> 0x038 0x2A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5
> 0x03C 0x2A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI
> 0x03C 0x2A4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY
> 0x03C 0x2A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT
> 0x03C 0x2A4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG
> 0x03C 0x2A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6
> 0x040 0x2A8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC
> 0x040 0x2A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B
> 0x040 0x2A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3
> 0x040 0x2A8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG
> 0x040 0x2A8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7
> 0x044 0x2AC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO
> 0x044 0x2AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP
> 0x044 0x2AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4
> 0x044 0x2AC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG
> 0x044 0x2AC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8
> 0x048 0x2B0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN
> 0x048 0x2B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B
> 0x048 0x2B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT
> 0x048 0x2B0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG
> 0x048 0x2B0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9
> 0x04C 0x2B4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT
> 0x04C 0x2B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0
> 0x04C 0x2B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP
> 0x04C 0x2B4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG
> 0x04C 0x2B4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10
> 0x050 0x2B8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID
> 0x050 0x2B8 0x000 0x1 0x0
> +#define
> MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED
> 0x050 0x2B8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11
> 0x054 0x2BC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID
> 0x054 0x2BC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY
> 0x054 0x2BC 0x4BC 0x5 0x1
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0
> 0x054 0x2BC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS
> 0x054 0x2BC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12
> 0x058 0x2C0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR
> 0x058 0x2C0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1
> 0x058 0x2C0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1
> 0x058 0x2C0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0
> 0x058 0x2C0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13
> 0x05C 0x2C4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC
> 0x05C 0x2C4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT
> 0x05C 0x2C4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2
> 0x05C 0x2C4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1
> 0x05C 0x2C4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14
> 0x060 0x2C8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR
> 0x060 0x2C8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT
> 0x060 0x2C8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1
> 0x060 0x2C8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2
> 0x060 0x2C8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15
> 0x064 0x2CC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC
> 0x064 0x2CC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT
> 0x064 0x2CC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2
> 0x064 0x2CC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB
> 0x064 0x2CC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC
> 0x068 0x2D0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16
> 0x068 0x2D0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO
> 0x06C 0x2D4 0x4C0 0x0 0x1
> +#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17
> 0x06C 0x2D4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
> 0x070 0x2D8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18
> 0x070 0x2D8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
> 0x074 0x2DC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK
> 0x074 0x2DC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19
> 0x074 0x2DC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
> 0x078 0x2E0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20
> 0x078 0x2E0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
> 0x07C 0x2E4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21
> 0x07C 0x2E4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> 0x080 0x2E8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22
> 0x080 0x2E8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
> 0x084 0x2EC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER
> 0x084 0x2EC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23
> 0x084 0x2EC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
> 0x088 0x2F0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24
> 0x088 0x2F0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
> 0x08C 0x2F4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER
> 0x08C 0x2F4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25
> 0x08C 0x2F4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
> 0x090 0x2F8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26
> 0x090 0x2F8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
> 0x094 0x2FC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27
> 0x094 0x2FC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
> 0x098 0x300 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28
> 0x098 0x300 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
> 0x09C 0x304 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29
> 0x09C 0x304 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
> 0x0A0 0x308 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0
> 0x0A0 0x308 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
> 0x0A4 0x30C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1
> 0x0A4 0x30C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 0x0A8 0x310 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2
> 0x0A8 0x31  0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 0x0AC 0x314 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3
> 0x0AC 0x314 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 0x0B0 0x318 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4
> 0x0B0 0x318 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 0x0B4 0x31C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5
> 0x0B4 0x31C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
> 0x0B8 0x320 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6
> 0x0B8 0x320 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
> 0x0BC 0x324 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7
> 0x0BC 0x324 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
> 0x0C0 0x328 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8
> 0x0C0 0x328 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
> 0x0C4 0x32C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9
> 0x0C4 0x32C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
> 0x0C8 0x330 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10
> 0x0C8 0x330 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
> 0x0CC 0x334 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11
> 0x0CC 0x334 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B
> 0x0D0 0x338 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12
> 0x0D0 0x338 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
> 0x0D4 0x33C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13
> 0x0D4 0x33C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0
> 0x0D4 0x33C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0
> 0x0D4 0x33C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
> 0x0D8 0x340 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14
> 0x0D8 0x340 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1
> 0x0D8 0x340 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1
> 0x0D8 0x340 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x0DC 0x344 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15
> 0x0DC 0x344 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2
> 0x0DC 0x344 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2
> 0x0DC 0x344 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x0E0 0x348 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16
> 0x0E0 0x348 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT
> 0x0E0 0x348 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3
> 0x0E0 0x348 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x0E4 0x34C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17
> 0x0E4 0x34C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP
> 0x0E4 0x34C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4
> 0x0E4 0x34C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x0E8 0x350 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18
> 0x0E8 0x350 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET
> 0x0E8 0x350 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B
> 0x0EC 0x354 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19
> 0x0EC 0x354 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET
> 0x0EC 0x354 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP
> 0x0F0 0x358 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20
> 0x0F0 0x358 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK
> 0x0F0 0x358 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE
> 0x0F4 0x35C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK
> 0x0F4 0x35C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0
> 0x0F4 0x35C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0
> 0x0F4 0x35C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B
> 0x0F8 0x360 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B
> 0x0F8 0x360 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1
> 0x0F8 0x360 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1
> 0x0F8 0x360 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B
> 0x0FC 0x364 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B
> 0x0FC 0x364 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2
> 0x0FC 0x364 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2
> 0x0FC 0x364 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B
> 0x100 0x368 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B
> 0x100 0x368 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3
> 0x100 0x368 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3
> 0x100 0x368 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B
> 0x104 0x36C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B
> 0x104 0x36C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4
> 0x104 0x36C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0
> 0x104 0x36C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE
> 0x108 0x370 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK
> 0x108 0x370 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5
> 0x108 0x370 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1
> 0x108 0x370 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00
> 0x10C 0x374 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0
> 0x10C 0x374 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6
> 0x10C 0x374 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2
> 0x10C 0x374 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01
> 0x110 0x378 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1
> 0x110 0x378 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7
> 0x110 0x378 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3
> 0x110 0x378 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02
> 0x114 0x37C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2
> 0x114 0x37C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8
> 0x114 0x37C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4
> 0x114 0x37C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03
> 0x118 0x380 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3
> 0x118 0x380 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9
> 0x118 0x380 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5
> 0x118 0x380 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04
> 0x11C 0x384 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0
> 0x11C 0x384 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10
> 0x11C 0x384 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6
> 0x11C 0x384 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05
> 0x120 0x388 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1
> 0x120 0x388 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11
> 0x120 0x388 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7
> 0x120 0x388 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06
> 0x124 0x38C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2
> 0x124 0x38C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12
> 0x124 0x38C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8
> 0x124 0x38C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07
> 0x128 0x390 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3
> 0x128 0x390 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13
> 0x128 0x390 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9
> 0x128 0x390 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS
> 0x12C 0x394 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS
> 0x12C 0x394 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14
> 0x12C 0x394 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10
> 0x12C 0x394 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B
> 0x130 0x398 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS
> 0x130 0x398 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15
> 0x130 0x398 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11
> 0x130 0x398 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B
> 0x134 0x39C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16
> 0x134 0x39C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12
> 0x134 0x39C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B
> 0x138 0x3A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17
> 0x138 0x3A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13
> 0x138 0x3A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B
> 0x13C 0x3A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18
> 0x13C 0x3A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14
> 0x13C 0x3A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC
> 0x140 0x3A8 0x4E4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0
> 0x140 0x3A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19
> 0x140 0x3A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK
> 0x144 0x3AC 0x4D0 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1
> 0x144 0x3AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20
> 0x144 0x3AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0
> 0x148 0x3B0 0x4D4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2
> 0x148 0x3B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21
> 0x148 0x3B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1
> 0x14C 0x3B4 0x4D8 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3
> 0x14C 0x3B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC
> 0x14C 0x3B4 0x4CC 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC
> 0x14C 0x3B4 0x4EC 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22
> 0x14C 0x3B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2
> 0x150 0x3B8 0x4DC 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4
> 0x150 0x3B8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC
> 0x150 0x3B8 0x4CC 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK
> 0x150 0x3B8 0x4E8 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23
> 0x150 0x3B8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3
> 0x154 0x3BC 0x4E0 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5
> 0x154 0x3BC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC
> 0x154 0x3BC 0x4CC 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0
> 0x154 0x3BC 0x000 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24
> 0x154 0x3BC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK
> 0x158 0x3C0 0x52C 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK
> 0x158 0x3C0 0x4C8 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK
> 0x158 0x3C0 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25
> 0x158 0x3C0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK
> 0x158 0x3C0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC
> 0x15C 0x3C4 0x4C4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC
> 0x15C 0x3C4 0x4E4 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK
> 0x15C 0x3C4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0
> 0x15C 0x3C4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15
> 0x15C 0x3C4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK
> 0x160 0x3C8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK
> 0x160 0x3C8 0x4D0 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL
> 0x160 0x3C8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1
> 0x160 0x3C8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16
> 0x160 0x3C8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0
> 0x164 0x3CC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0
> 0x164 0x3CC 0x4D4 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0
> 0x164 0x3CC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2
> 0x164 0x3CC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0
> 0x164 0x3CC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17
> 0x164 0x3CC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1
> 0x168 0x3D0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1
> 0x168 0x3D0 0x4D8 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1
> 0x168 0x3D0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3
> 0x168 0x3D0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1
> 0x168 0x3D0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18
> 0x168 0x3D0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2
> 0x16C 0x3D4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2
> 0x16C 0x3D4 0x4DC 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2
> 0x16C 0x3D4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4
> 0x16C 0x3D4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2
> 0x16C 0x3D4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19
> 0x16C 0x3D4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3
> 0x170 0x3D8 0x4E0 0x0 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3
> 0x170 0x3D8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3
> 0x170 0x3D8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5
> 0x170 0x3D8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3
> 0x170 0x3D8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20
> 0x170 0x3D8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4
> 0x174 0x3DC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK
> 0x174 0x3DC 0x51C 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK
> 0x174 0x3DC 0x510 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4
> 0x174 0x3DC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6
> 0x174 0x3DC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4
> 0x174 0x3DC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21
> 0x174 0x3DC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5
> 0x178 0x3E0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0
> 0x178 0x3E0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0
> 0x178 0x3E0 0x514 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC
> 0x178 0x3E0 0x4C4 0x3 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5
> 0x178 0x3E0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7
> 0x178 0x3E0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5
> 0x178 0x3E0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22
> 0x178 0x3E0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6
> 0x17C 0x3E4 0x520 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC
> 0x17C 0x3E4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC
> 0x17C 0x3E4 0x518 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6
> 0x17C 0x3E4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8
> 0x17C 0x3E4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6
> 0x17C 0x3E4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23
> 0x17C 0x3E4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7
> 0x180 0x3E8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK
> 0x180 0x3E8 0x530 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC
> 0x180 0x3E8 0x4CC 0x2 0x4
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4
> 0x180 0x3E8 0x000 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7
> 0x180 0x3E8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9
> 0x180 0x3E8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7
> 0x180 0x3E8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24
> 0x180 0x3E8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC
> 0x184 0x3EC 0x4CC 0x0 0x3
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC
> 0x184 0x3EC 0x4EC 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO
> 0x184 0x3EC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10
> 0x184 0x3EC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25
> 0x184 0x3EC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK
> 0x188 0x3F0 0x4C8 0x0 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK
> 0x188 0x3F0 0x4E8 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI
> 0x188 0x3F0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11
> 0x188 0x3F0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26
> 0x188 0x3F0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0
> 0x18C 0x3F4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0
> 0x18C 0x3F4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8
> 0x18C 0x3F4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12
> 0x18C 0x3F4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8
> 0x18C 0x3F4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27
> 0x18C 0x3F4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1
> 0x190 0x3F8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1
> 0x190 0x3F8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9
> 0x190 0x3F8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13
> 0x190 0x3F8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9
> 0x190 0x3F8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28
> 0x190 0x3F8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
> 0x194 0x3FC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2
> 0x194 0x3FC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10
> 0x194 0x3FC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14
> 0x194 0x3FC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10
> 0x194 0x3FC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29
> 0x194 0x3FC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3
> 0x198 0x400 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3
> 0x198 0x400 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11
> 0x198 0x400 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15
> 0x198 0x400 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11
> 0x198 0x400 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30
> 0x198 0x400 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4
> 0x19C 0x404 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK
> 0x19C 0x404 0x510 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK
> 0x19C 0x404 0x51C 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12
> 0x19C 0x404 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16
> 0x19C 0x404 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12
> 0x19C 0x404 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31
> 0x19C 0x404 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5
> 0x1A0 0x408 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0
> 0x1A0 0x408 0x514 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0
> 0x1A0 0x408 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13
> 0x1A0 0x408 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17
> 0x1A0 0x408 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13
> 0x1A0 0x408 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0
> 0x1A0 0x408 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6
> 0x1A4 0x40C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC
> 0x1A4 0x40C 0x518 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC
> 0x1A4 0x40C 0x520 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14
> 0x1A4 0x40C 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18
> 0x1A4 0x40C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14
> 0x1A4 0x40C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1
> 0x1A4 0x40C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7
> 0x1A8 0x410 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK
> 0x1A8 0x410 0x530 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15
> 0x1A8 0x410 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19
> 0x1A8 0x410 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15
> 0x1A8 0x410 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2
> 0x1A8 0x410 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK
> 0x1AC 0x414 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK
> 0x1AC 0x414 0x52C 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK
> 0x1AC 0x414 0x4C8 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20
> 0x1AC 0x414 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP
> 0x1AC 0x414 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC
> 0x1B0 0x418 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC
> 0x1B0 0x418 0x4EC 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21
> 0x1B0 0x418 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0
> 0x1B0 0x418 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK
> 0x1B4 0x41C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK
> 0x1B4 0x41C 0x4E8 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22
> 0x1B4 0x41C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1
> 0x1B4 0x41C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0
> 0x1B8 0x420 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0
> 0x1B8 0x420 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23
> 0x1B8 0x420 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2
> 0x1B8 0x420 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC
> 0x1BC 0x424 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1
> 0x1BC 0x424 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24
> 0x1BC 0x424 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE
> 0x1BC 0x424 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK
> 0x1C0 0x428 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2
> 0x1C0 0x428 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25
> 0x1C0 0x428 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT
> 0x1C0 0x428 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
> 0x1C4 0x42C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3
> 0x1C4 0x42C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26
> 0x1C4 0x42C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK
> 0x1C4 0x42C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK
> 0x1C8 0x430 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK
> 0x1C8 0x430 0x52C 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27
> 0x1C8 0x430 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR
> 0x1C8 0x430 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC
> 0x1CC 0x434 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1
> 0x1CC 0x434 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC
> 0x1CC 0x434 0x4E4 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28
> 0x1CC 0x434 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0
> 0x1CC 0x434 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK
> 0x1D0 0x438 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2
> 0x1D0 0x438 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK
> 0x1D0 0x438 0x4D0 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29
> 0x1D0 0x438 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1
> 0x1D0 0x438 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0
> 0x1D4 0x43C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1
> 0x1D4 0x43C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0
> 0x1D4 0x43C 0x4D4 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30
> 0x1D4 0x43C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0
> 0x1D4 0x43C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC
> 0x1D8 0x440 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK
> 0x1D8 0x440 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1
> 0x1D8 0x440 0x4D8 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31
> 0x1D8 0x440 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1
> 0x1D8 0x440 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK
> 0x1DC 0x444 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2
> 0x1DC 0x444 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2
> 0x1DC 0x444 0x4DC 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0
> 0x1DC 0x444 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2
> 0x1DC 0x444 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0
> 0x1E0 0x448 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3
> 0x1E0 0x448 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3
> 0x1E0 0x448 0x4E0 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1
> 0x1E0 0x448 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3
> 0x1E0 0x448 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK
> 0x1E4 0x44C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT
> 0x1E4 0x44C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK
> 0x1E4 0x44C 0x52C 0x2 0x3
> +#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2
> 0x1E4 0x44C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4
> 0x1E4 0x44C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT
> 0x1E8 0x450 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT
> 0x1E8 0x450 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3
> 0x1E8 0x450 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5
> 0x1E8 0x450 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN
> 0x1EC 0x454 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT
> 0x1EC 0x454 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4
> 0x1EC 0x454 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6
> 0x1EC 0x454 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK
> 0x1F0 0x458 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT
> 0x1F0 0x458 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
> 0x1F0 0x458 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7
> 0x1F0 0x458 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK
> 0x1F4 0x45C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX
> 0x1F4 0x45C 0x504 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX
> 0x1F4 0x45C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6
> 0x1F4 0x45C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8
> 0x1F4 0x45C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI
> 0x1F8 0x460 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX
> 0x1F8 0x460 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX
> 0x1F8 0x460 0x504 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7
> 0x1F8 0x460 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9
> 0x1F8 0x460 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO
> 0x1FC 0x464 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B
> 0x1FC 0x464 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B
> 0x1FC 0x464 0x500 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8
> 0x1FC 0x464 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10
> 0x1FC 0x464 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0
> 0x200 0x468 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B
> 0x200 0x468 0x500 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B
> 0x200 0x468 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9
> 0x200 0x468 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11
> 0x200 0x468 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
> 0x204 0x46C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX
> 0x204 0x46C 0x50C 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX
> 0x204 0x46C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10
> 0x204 0x46C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12
> 0x204 0x46C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
> 0x208 0x470 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX
> 0x208 0x470 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX
> 0x208 0x470 0x50C 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11
> 0x208 0x470 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13
> 0x208 0x470 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
> 0x20C 0x474 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B
> 0x20C 0x474 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B
> 0x20C 0x474 0x508 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12
> 0x20C 0x474 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14
> 0x20C 0x474 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0
> 0x210 0x478 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B
> 0x210 0x478 0x508 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B
> 0x210 0x478 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13
> 0x210 0x478 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15
> 0x210 0x478 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
> 0x214 0x47C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC
> 0x214 0x47C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14
> 0x214 0x47C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16
> 0x214 0x47C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
> 0x218 0x480 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO
> 0x218 0x480 0x4C0 0x1 0x2
> +#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15
> 0x218 0x480 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17
> 0x218 0x480 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL
> 0x21C 0x484 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN
> 0x21C 0x484 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16
> 0x21C 0x484 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18
> 0x21C 0x484 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA
> 0x220 0x488 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT
> 0x220 0x488 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17
> 0x220 0x488 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19
> 0x220 0x488 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL
> 0x224 0x48C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT
> 0x224 0x48C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK
> 0x224 0x48C 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18
> 0x224 0x48C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20
> 0x224 0x48C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA
> 0x228 0x490 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT
> 0x228 0x490 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK
> 0x228 0x490 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19
> 0x228 0x490 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21
> 0x228 0x490 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL
> 0x22C 0x494 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT
> 0x22C 0x494 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B
> 0x22C 0x494 0x524 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20
> 0x22C 0x494 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22
> 0x22C 0x494 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA
> 0x230 0x498 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT
> 0x230 0x498 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B
> 0x230 0x498 0x528 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21
> 0x230 0x498 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23
> 0x230 0x498 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
> 0x234 0x49C 0x4F4 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX
> 0x234 0x49C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK
> 0x234 0x49C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22
> 0x234 0x49C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24
> 0x234 0x49C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
> 0x238 0x4A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX
> 0x238 0x4A0 0x4F4 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI
> 0x238 0x4A0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23
> 0x238 0x4A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25
> 0x238 0x4A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX
> 0x23C 0x4A4 0x4FC 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX
> 0x23C 0x4A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO
> 0x23C 0x4A4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24
> 0x23C 0x4A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26
> 0x23C 0x4A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX
> 0x240 0x4A8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX
> 0x240 0x4A8 0x4FC 0x0 0x1
> +#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0
> 0x240 0x4A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25
> 0x240 0x4A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27
> 0x240 0x4A8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX
> 0x244 0x4AC 0x504 0x0 0x2
> +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX
> 0x244 0x4AC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B
> 0x244 0x4AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B
> 0x244 0x4AC 0x4F0 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26
> 0x244 0x4AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28
> 0x244 0x4AC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX
> 0x248 0x4B0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX
> 0x248 0x4B0 0x504 0x0 0x3
> +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B
> 0x248 0x4B0 0x4F0 0x1 0x1
> +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B
> 0x248 0x4B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27
> 0x248 0x4B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29
> 0x248 0x4B0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX
> 0x24C 0x4B4 0x50C 0x0 0x2
> +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX
> 0x24C 0x4B4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B
> 0x24C 0x4B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B
> 0x24C 0x4B4 0x4F8 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B
> 0x24C 0x4B4 0x524 0x2 0x1
> +#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28
> 0x24C 0x4B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30
> 0x24C 0x4B4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX
> 0x250 0x4B8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX
> 0x250 0x4B8 0x50C 0x0 0x3
> +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B
> 0x250 0x4B8 0x4F8 0x1 0x1
> +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B
> 0x250 0x4B8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B
> 0x250 0x4B8 0x528 0x2 0x1
> +#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29
> 0x250 0x4B8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31
> 0x250 0x4B8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_TEST_MODE
> 0x000 0x254 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_BOOT_MODE0
> 0x000 0x258 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_BOOT_MODE1
> 0x000 0x25C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_MOD
> 0x000 0x260 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TRST_B
> 0x000 0x264 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TDI
> 0x000 0x268 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TMS
> 0x000 0x26C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TCK
> 0x000 0x270 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TDO
> 0x000 0x274 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_RTC
> 0x000 0x278 0x000 0x0 0x0
> +
> +#endif /* __DTS_IMX8MQ_PINFUNC_H */
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> new file mode 100644
> index 000000000000..50ed302d299a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017 NXP
> + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org>
> + */
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "imx8mq-pinfunc.h"
> +
> +/* first 128 KiB of memory are owned by ATF */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +/ {
> +	/* This should really be the GPC, but we need a driver for this first *=
/
> +	interrupt-parent =3D <&gic>;
> +
> +	#address-cells =3D <2>;
> +	#size-cells =3D <2>;
> +
> +	aliases {
> +		i2c0 =3D &i2c1;
> +		i2c1 =3D &i2c2;
> +		i2c2 =3D &i2c3;
> +		i2c3 =3D &i2c4;
> +		serial0 =3D &uart1;
> +		serial1 =3D &uart2;
> +		serial2 =3D &uart3;
> +		serial3 =3D &uart4;
> +	};
> +
> +	ckil: clk-ckil {
> +		compatible =3D "fixed-clock";
> +		#clock-cells =3D <0>;
> +		clock-frequency =3D <32768>;
> +		clock-output-names =3D "ckil";
> +	};
> +
> +	osc_25m: clk-osc-25m {
> +		compatible =3D "fixed-clock";
> +		#clock-cells =3D <0>;
> +		clock-frequency =3D <25000000>;
> +		clock-output-names =3D "osc_25m";
> +	};
> +
> +	osc_27m: clk-osc-27m {
> +		compatible =3D "fixed-clock";
> +		#clock-cells =3D <0>;
> +		clock-frequency =3D <27000000>;
> +		clock-output-names =3D "osc_27m";
> +	};
> +
> +	clk_ext1: clk-ext1 {
> +		compatible =3D "fixed-clock";
> +		#clock-cells =3D <0>;
> +		clock-frequency =3D <133000000>;
> +		clock-output-names =3D "clk_ext1";
> +	};
> +
> +	clk_ext2: clk-ext2 {
> +		compatible =3D "fixed-clock";
> +		#clock-cells =3D <0>;
> +		clock-frequency =3D <133000000>;
> +		clock-output-names =3D "clk_ext2";
> +	};
> +
> +	clk_ext3: clk-ext3 {
> +		compatible =3D "fixed-clock";
> +		#clock-cells =3D <0>;
> +		clock-frequency =3D <133000000>;
> +		clock-output-names =3D "clk_ext3";
> +	};
> +
> +	clk_ext4: clk-ext4 {
> +		compatible =3D "fixed-clock";
> +		#clock-cells =3D <0>;
> +		clock-frequency=3D <133000000>;
> +		clock-output-names =3D "clk_ext4";
> +	};
> +
> +	cpus {
> +		#address-cells =3D <1>;
> +		#size-cells =3D <0>;
> +
> +		idle-states {
> +			entry-method =3D "psci";
> +
> +			CPU_SLEEP: cpu-sleep {
> +				compatible =3D "arm,idle-state";
> +				arm,psci-suspend-param =3D <0x0010033>;
> +				local-timer-stop;
> +				entry-latency-us =3D <1000>;
> +				exit-latency-us =3D <700>;
> +				min-residency-us =3D <2700>;
> +				wakeup-latency-us =3D <1500>;
> +			};
> +		};
> +
> +		A53_0: cpu@0 {
> +			device_type =3D "cpu";
> +			compatible =3D "arm,cortex-a53";
> +			reg =3D <0x0>;
> +			enable-method =3D "psci";
> +			next-level-cache =3D <&A53_L2>;
> +			cpu-idle-states =3D <&CPU_SLEEP>;
> +		};
> +
> +		A53_1: cpu@1 {
> +			device_type =3D "cpu";
> +			compatible =3D "arm,cortex-a53";
> +			reg =3D <0x1>;
> +			enable-method =3D "psci";
> +			next-level-cache =3D <&A53_L2>;
> +			cpu-idle-states =3D <&CPU_SLEEP>;
> +		};
> +
> +		A53_2: cpu@2 {
> +			device_type =3D "cpu";
> +			compatible =3D "arm,cortex-a53";
> +			reg =3D <0x2>;
> +			enable-method =3D "psci";
> +			next-level-cache =3D <&A53_L2>;
> +			cpu-idle-states =3D <&CPU_SLEEP>;
> +		};
> +
> +		A53_3: cpu@3 {
> +			device_type =3D "cpu";
> +			compatible =3D "arm,cortex-a53";
> +			reg =3D <0x3>;
> +			enable-method =3D "psci";
> +			next-level-cache =3D <&A53_L2>;
> +			cpu-idle-states =3D <&CPU_SLEEP>;
> +		};
> +
> +		A53_L2: l2-cache0 {
> +			compatible =3D "cache";
> +		};
> +	};
> +
> +	psci {
> +		compatible =3D "arm,psci-1.0";
> +		method =3D "smc";
> +	};
> +
> +	timer {
> +		compatible =3D "arm,armv8-timer";
> +		interrupts =3D <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> +		             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> +		             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> +		             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> +		clock-frequency =3D <8333333>;
> +		interrupt-parent =3D <&gic>;
> +		arm,no-tick-in-suspend;
> +	};
> +
> +	peripherals@0 {
> +		compatible =3D "simple-bus";
> +		#address-cells =3D <1>;
> +		#size-cells =3D <1>;
> +		ranges =3D <0x0 0x0 0x0 0x3e000000>;
> +
> +		bus@30000000 { /* AIPS1 */
> +			compatible =3D "fsl,imx8mq-aips-bus", "simple-bus";
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			ranges =3D <0x30000000 0x30000000 0x400000>;
> +
> +			gpio1: gpio@30200000 {
> +				compatible =3D "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg =3D <0x30200000 0x10000>;
> +				interrupts =3D <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> +				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells =3D <2>;
> +				interrupt-controller;
> +				#interrupt-cells =3D <2>;
> +			};
> +
> +			gpio2: gpio@30210000 {
> +				compatible =3D "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg =3D <0x30210000 0x10000>;
> +				interrupts =3D <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> +				        <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells =3D <2>;
> +				interrupt-controller;
> +				#interrupt-cells =3D <2>;
> +			};
> +
> +			gpio3: gpio@30220000 {
> +				compatible =3D "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg =3D <0x30220000 0x10000>;
> +				interrupts =3D <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> +				        <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells =3D <2>;
> +				interrupt-controller;
> +				#interrupt-cells =3D <2>;
> +			};
> +
> +			gpio4: gpio@30230000 {
> +				compatible =3D "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg =3D <0x30230000 0x10000>;
> +				interrupts =3D <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> +				                <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells =3D <2>;
> +				interrupt-controller;
> +				#interrupt-cells =3D <2>;
> +			};
> +
> +			gpio5: gpio@30240000 {
> +				compatible =3D "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg =3D <0x30240000 0x10000>;
> +				interrupts =3D <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> +				        <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells =3D <2>;
> +				interrupt-controller;
> +				#interrupt-cells =3D <2>;
> +			};
> +
> +			iomuxc: iomuxc@30330000 {
> +				compatible =3D "fsl,imx8mq-iomuxc";
> +				reg =3D <0x30330000 0x10000>;
> +			};
> +
> +			gpr: iomuxc-gpr@30340000 {
> +				compatible =3D "fsl,imx8mq-iomuxc-gpr", "syscon";
> +				reg =3D <0x30340000 0x10000>;
> +			};
> +
> +			anatop: anatop@30360000 {
> +				compatible =3D "fsl,imx8mq-anatop", "syscon";
> +				reg =3D <0x30360000 0x10000>;
> +				interrupts =3D <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			clk: clock-controller@30380000 {
> +				compatible =3D "fsl,imx8mq-ccm";
> +				reg =3D <0x30380000 0x10000>;
> +				interrupts =3D <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> +				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +				#clock-cells =3D <1>;
> +				clocks =3D <&ckil>, <&osc_25m>, <&osc_27m>,
> +				         <&clk_ext1>, <&clk_ext2>,
> +				         <&clk_ext3>, <&clk_ext4>;
> +				clock-names =3D "ckil", "osc_25m", "osc_27m",
> +				              "clk_ext1", "clk_ext2",
> +				              "clk_ext3", "clk_ext4";
> +			};
> +		};
> +
> +		bus@30400000 { /* AIPS2 */
> +			compatible =3D "fsl,imx8mq-aips-bus", "simple-bus";
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			ranges =3D <0x30400000 0x30400000 0x400000>;
> +		};
> +
> +		bus@30800000 { /* AIPS3 */
> +			compatible =3D "fsl,imx8mq-aips-bus", "simple-bus";
> +			#address-cells =3D <1>;
> +			#size-cells =3D <1>;
> +			ranges =3D <0x30800000 0x30800000 0x400000>;
> +
> +			uart1: serial@30860000 {
> +				compatible =3D "fsl,imx8mq-uart",
> +				             "fsl,imx6q-uart";
> +				reg =3D <0x30860000 0x10000>;
> +				interrupts =3D <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_UART1_ROOT>,
> +				         <&clk IMX8MQ_CLK_UART1_ROOT>;
> +				clock-names =3D "ipg", "per";
> +				status =3D "disabled";
> +			};
> +
> +			uart3: serial@30880000 {
> +				compatible =3D "fsl,imx8mq-uart",
> +				             "fsl,imx6q-uart";
> +				reg =3D <0x30880000 0x10000>;
> +				interrupts =3D <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_UART3_ROOT>,
> +				         <&clk IMX8MQ_CLK_UART3_ROOT>;
> +				clock-names =3D "ipg", "per";
> +				status =3D "disabled";
> +			};
> +
> +			uart2: serial@30890000 {
> +				compatible =3D "fsl,imx8mq-uart",
> +				             "fsl,imx6q-uart";
> +				reg =3D <0x30890000 0x10000>;
> +				interrupts =3D <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_UART2_ROOT>,
> +				         <&clk IMX8MQ_CLK_UART2_ROOT>;
> +				clock-names =3D "ipg", "per";
> +				status =3D "disabled";
> +			};
> +
> +			i2c1: i2c@30a20000 {
> +				compatible =3D "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> +				reg =3D <0x30a20000 0x10000>;
> +				interrupts =3D <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_I2C1_ROOT>;
> +				#address-cells =3D <1>;
> +				#size-cells =3D <0>;
> +				status =3D "disabled";
> +			};
> +
> +			i2c2: i2c@30a30000 {
> +				compatible =3D "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> +				reg =3D <0x30a30000 0x10000>;
> +				interrupts =3D <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_I2C2_ROOT>;
> +				#address-cells =3D <1>;
> +				#size-cells =3D <0>;
> +				status =3D "disabled";
> +			};
> +
> +			i2c3: i2c@30a40000 {
> +				compatible =3D "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> +				reg =3D <0x30a40000 0x10000>;
> +				interrupts =3D <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_I2C3_ROOT>;
> +				#address-cells =3D <1>;
> +				#size-cells =3D <0>;
> +				status =3D "disabled";
> +			};
> +
> +			i2c4: i2c@30a50000 {
> +				compatible =3D "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> +				reg =3D <0x30a50000 0x10000>;
> +				interrupts =3D <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_I2C4_ROOT>;
> +				#address-cells =3D <1>;
> +				#size-cells =3D <0>;
> +				status =3D "disabled";
> +			};
> +
> +			uart4: serial@30a60000 {
> +				compatible =3D "fsl,imx8mq-uart",
> +				             "fsl,imx6q-uart";
> +				reg =3D <0x30a60000 0x10000>;
> +				interrupts =3D <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_UART4_ROOT>,
> +				         <&clk IMX8MQ_CLK_UART4_ROOT>;
> +				clock-names =3D "ipg", "per";
> +				status =3D "disabled";
> +			};
> +
> +			usdhc1: usdhc@30b40000 {
> +				compatible =3D "fsl,imx8mq-usdhc",
> +				             "fsl,imx7d-usdhc";
> +				reg =3D <0x30b40000 0x10000>;
> +				interrupts =3D <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_DUMMY>,
> +				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> +				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
> +				clock-names =3D "ipg", "ahb", "per";
> +				fsl,tuning-start-tap =3D <20>;
> +				fsl,tuning-step =3D <2>;
> +				bus-width =3D <4>;
> +				status =3D "disabled";
> +			};
> +
> +			usdhc2: usdhc@30b50000 {
> +				compatible =3D "fsl,imx8mq-usdhc",
> +				             "fsl,imx7d-usdhc";
> +				reg =3D <0x30b50000 0x10000>;
> +				interrupts =3D <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_DUMMY>,
> +				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> +				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
> +				clock-names =3D "ipg", "ahb", "per";
> +				fsl,tuning-start-tap =3D <20>;
> +				fsl,tuning-step =3D <2>;
> +				bus-width =3D <4>;
> +				status =3D "disabled";
> +			};
> +
> +			fec1: ethernet@30be0000 {
> +				compatible =3D "fsl,imx8mq-fec", "fsl,imx6sx-fec";
> +				reg =3D <0x30be0000 0x10000>;
> +				interrupts =3D <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> +				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> +				             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks =3D <&clk IMX8MQ_CLK_ENET1_ROOT>,
> +				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
> +				         <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
> +				         <&clk IMX8MQ_CLK_ENET_REF_DIV>,
> +				         <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
> +				clock-names =3D "ipg", "ahb", "ptp",
> +				              "enet_clk_ref", "enet_out";
> +				fsl,num-tx-queues =3D <3>;
> +				fsl,num-rx-queues =3D <3>;
> +				status =3D "disabled";
> +			};
> +		};
> +
> +		gic: interrupt-controller@38800000 {
> +			compatible =3D "arm,gic-v3";
> +			reg =3D <0x38800000 0x10000>, /* GIC Dist */
> +			      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base)
> */
> +			#interrupt-cells =3D <3>;
> +			interrupt-controller;
> +			interrupts =3D <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-parent =3D <&gic>;
> +		};
> +	};
> +};
> --
> 2.15.1

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From mboxrd@z Thu Jan  1 00:00:00 1970
From: ping.bai@nxp.com (Jacky Bai)
Date: Fri, 2 Feb 2018 08:13:56 +0000
Subject: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
In-Reply-To: <20180201183126.32384-2-l.stach@pengutronix.de>
References: <20180201183126.32384-1-l.stach@pengutronix.de>
 <20180201183126.32384-2-l.stach@pengutronix.de>
Message-ID: <HE1PR04MB3113FF72B02D642392D625DF87F90@HE1PR04MB3113.eurprd04.prod.outlook.com>
To: linux-arm-kernel@lists.infradead.org
List-Id: linux-arm-kernel.lists.infradead.org

> Subject: [PATCH v2 2/4] arm64: add basic DTS for i.MX8MQ
> 
> This adds the basic DTS for the i.MX8MQ.
> For now only the following peripherals are supported:
> - IOMUXC (pin controller)
> - CCM (clock controller)
> - GPIO
> - UART
> - uSDHC (SD/eMMC controller)
> - FEC (ethernet controller)
> - i2c
> 
> This is enough to get a very basic board support up and running.
> 
> One known limitation is that the driver for the GPC interrupt
> controller is still missing, rendering the CPU sleep states unusable
> as there is nothing waking them up anymore. This will be fixed in
> due course.
> 

The cpu sleep states can NOT be supported in community kernel due to hardware limitation.

BR
Jacky Bai
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> v2:
>  - move to freescale folder
>  - change compatibles to "fsl" vendor prefix
>  - remove unnecessary newlines
>  - move status property to be the last in all node
>  - remove imx21 compatibles from UART nodes
>  - document compatible
> ---
>  Documentation/devicetree/bindings/arm/fsl.txt  |   4 +
>  arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h | 623
> +++++++++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8mq.dtsi      | 411 ++++++++++++++++
>  3 files changed, 1038 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
>  create mode 100644 arch/arm64/boot/dts/freescale/imx8mq.dtsi
> 
> diff --git a/Documentation/devicetree/bindings/arm/fsl.txt
> b/Documentation/devicetree/bindings/arm/fsl.txt
> index cdb9dd705754..85d1c9ec6fa3 100644
> --- a/Documentation/devicetree/bindings/arm/fsl.txt
> +++ b/Documentation/devicetree/bindings/arm/fsl.txt
> @@ -75,6 +75,10 @@ i.MX6q generic board
>  Required root node properties:
>      - compatible = "fsl,imx6q";
> 
> +i.MX8MQ generic board
> +Required root node properties:
> +    - compatible = "fsl,imx8mq";
> +
>  Freescale Vybrid Platform Device Tree Bindings
>  ----------------------------------------------
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> new file mode 100644
> index 000000000000..b94b02080a34
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h
> @@ -0,0 +1,623 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +/*
> + * Copyright (C) 2016 Freescale Semiconductor, Inc.
> + * Copyright 2017 NXP
> + */
> +
> +#ifndef __DTS_IMX8MQ_PINFUNC_H
> +#define __DTS_IMX8MQ_PINFUNC_H
> +
> +/*
> + * The pin function ID is a tuple of
> + * <mux_reg conf_reg input_reg mux_mode input_val>
> + */
> +
> +#define
> MX8MQ_IOMUXC_PMIC_STBY_REQ_CCMSRCGPCMIX_PMIC_STBY_REQ
> 0x014 0x27C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_PMIC_ON_REQ_SNVSMIX_PMIC_ON_REQ
> 0x018 0x280 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ONOFF_SNVSMIX_ONOFF
> 0x01C 0x284 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_POR_B_SNVSMIX_POR_B
> 0x020 0x288 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_RTC_RESET_B_SNVSMIX_RTC_RESET_B
> 0x024 0x28C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0
> 0x028 0x290 0x000 0x0 0x0
> +#define
> MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_ENET_PHY_REF_CLK_ROOT
> 0x028 0x290 0x4C0 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K
> 0x028 0x290 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_CCMSRCGPCMIX_EXT_CLK1
> 0x028 0x290 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO00_SJC_FAIL
> 0x028 0x290 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_GPIO1_IO1
> 0x02C 0x294 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_PWM1_OUT
> 0x02C 0x294 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_ANAMIX_REF_CLK_24M
> 0x02C 0x294 0x4BC 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_CCMSRCGPCMIX_EXT_CLK2
> 0x02C 0x294 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO01_SJC_ACTIVE
> 0x02C 0x294 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_GPIO1_IO2
> 0x030 0x298 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B
> 0x030 0x298 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_ANY
> 0x030 0x298 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO02_SJC_DE_B
> 0x030 0x298 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3
> 0x034 0x29C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_USDHC1_VSELECT
> 0x034 0x29C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_SDMA1_EXT_EVENT0
> 0x034 0x29C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_ANAMIX_XTAL_OK
> 0x034 0x29C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO03_SJC_DONE
> 0x034 0x29C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_GPIO1_IO4
> 0x038 0x2A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT
> 0x038 0x2A0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_SDMA1_EXT_EVENT1
> 0x038 0x2A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_ANAMIX_XTAL_OK_LV
> 0x038 0x2A0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO04_USDHC1_TEST_TRIG
> 0x038 0x2A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5
> 0x03C 0x2A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_M4_NMI
> 0x03C 0x2A4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_PMIC_READY
> 0x03C 0x2A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_CCMSRCGPCMIX_INT_BOOT
> 0x03C 0x2A4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO05_USDHC2_TEST_TRIG
> 0x03C 0x2A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6
> 0x040 0x2A8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_ENET1_MDC
> 0x040 0x2A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_USDHC1_CD_B
> 0x040 0x2A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_CCMSRCGPCMIX_EXT_CLK3
> 0x040 0x2A8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO06_ECSPI1_TEST_TRIG
> 0x040 0x2A8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_GPIO1_IO7
> 0x044 0x2AC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_ENET1_MDIO
> 0x044 0x2AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_USDHC1_WP
> 0x044 0x2AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_CCMSRCGPCMIX_EXT_CLK4
> 0x044 0x2AC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO07_ECSPI2_TEST_TRIG
> 0x044 0x2AC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8
> 0x048 0x2B0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_ENET1_1588_EVENT0_IN
> 0x048 0x2B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_USDHC2_RESET_B
> 0x048 0x2B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_CCMSRCGPCMIX_WAIT
> 0x048 0x2B0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO08_QSPI_TEST_TRIG
> 0x048 0x2B0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9
> 0x04C 0x2B4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_ENET1_1588_EVENT0_OUT
> 0x04C 0x2B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_SDMA2_EXT_EVENT0
> 0x04C 0x2B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_CCMSRCGPCMIX_STOP
> 0x04C 0x2B4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO09_RAWNAND_TEST_TRIG
> 0x04C 0x2B4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO10_GPIO1_IO10
> 0x050 0x2B8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO10_USB1_OTG_ID
> 0x050 0x2B8 0x000 0x1 0x0
> +#define
> MX8MQ_IOMUXC_GPIO1_IO10_OCOTP_CTRL_WRAPPER_FUSE_LATCHED
> 0x050 0x2B8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11
> 0x054 0x2BC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_USB2_OTG_ID
> 0x054 0x2BC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_PMIC_READY
> 0x054 0x2BC 0x4BC 0x5 0x1
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CCMSRCGPCMIX_OUT0
> 0x054 0x2BC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO11_CAAM_WRAPPER_RNG_OSC_OBS
> 0x054 0x2BC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12
> 0x058 0x2C0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_USB1_OTG_PWR
> 0x058 0x2C0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_SDMA2_EXT_EVENT1
> 0x058 0x2C0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_CCMSRCGPCMIX_OUT1
> 0x058 0x2C0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO12_CSU_CSU_ALARM_AUT0
> 0x058 0x2C0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13
> 0x05C 0x2C4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_USB1_OTG_OC
> 0x05C 0x2C4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_PWM2_OUT
> 0x05C 0x2C4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_CCMSRCGPCMIX_OUT2
> 0x05C 0x2C4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO13_CSU_CSU_ALARM_AUT1
> 0x05C 0x2C4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_GPIO1_IO14
> 0x060 0x2C8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_USB2_OTG_PWR
> 0x060 0x2C8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_PWM3_OUT
> 0x060 0x2C8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1
> 0x060 0x2C8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO14_CSU_CSU_ALARM_AUT2
> 0x060 0x2C8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_GPIO1_IO15
> 0x064 0x2CC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_USB2_OTG_OC
> 0x064 0x2CC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_PWM4_OUT
> 0x064 0x2CC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2
> 0x064 0x2CC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_GPIO1_IO15_CSU_CSU_INT_DEB
> 0x064 0x2CC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC
> 0x068 0x2D0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_MDC_GPIO1_IO16
> 0x068 0x2D0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO
> 0x06C 0x2D4 0x4C0 0x0 0x1
> +#define MX8MQ_IOMUXC_ENET_MDIO_GPIO1_IO17
> 0x06C 0x2D4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3
> 0x070 0x2D8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD3_GPIO1_IO18
> 0x070 0x2D8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2
> 0x074 0x2DC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_ENET1_TX_CLK
> 0x074 0x2DC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19
> 0x074 0x2DC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1
> 0x078 0x2E0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD1_GPIO1_IO20
> 0x078 0x2E0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0
> 0x07C 0x2E4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TD0_GPIO1_IO21
> 0x07C 0x2E4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL
> 0x080 0x2E8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TX_CTL_GPIO1_IO22
> 0x080 0x2E8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC
> 0x084 0x2EC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_ENET1_TX_ER
> 0x084 0x2EC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_TXC_GPIO1_IO23
> 0x084 0x2EC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL
> 0x088 0x2F0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RX_CTL_GPIO1_IO24
> 0x088 0x2F0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC
> 0x08C 0x2F4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_ENET1_RX_ER
> 0x08C 0x2F4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ENET_RXC_GPIO1_IO25
> 0x08C 0x2F4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0
> 0x090 0x2F8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD0_GPIO1_IO26
> 0x090 0x2F8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1
> 0x094 0x2FC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD1_GPIO1_IO27
> 0x094 0x2FC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2
> 0x098 0x300 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD2_GPIO1_IO28
> 0x098 0x300 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3
> 0x09C 0x304 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ENET_RD3_GPIO1_IO29
> 0x09C 0x304 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK
> 0x0A0 0x308 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_CLK_GPIO2_IO0
> 0x0A0 0x308 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD
> 0x0A4 0x30C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_CMD_GPIO2_IO1
> 0x0A4 0x30C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0
> 0x0A8 0x310 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA0_GPIO2_IO2
> 0x0A8 0x31  0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1
> 0x0AC 0x314 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA1_GPIO2_IO3
> 0x0AC 0x314 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2
> 0x0B0 0x318 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA2_GPIO2_IO4
> 0x0B0 0x318 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3
> 0x0B4 0x31C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA3_GPIO2_IO5
> 0x0B4 0x31C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4
> 0x0B8 0x320 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA4_GPIO2_IO6
> 0x0B8 0x320 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5
> 0x0BC 0x324 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA5_GPIO2_IO7
> 0x0BC 0x324 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6
> 0x0C0 0x328 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA6_GPIO2_IO8
> 0x0C0 0x328 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7
> 0x0C4 0x32C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_DATA7_GPIO2_IO9
> 0x0C4 0x32C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B
> 0x0C8 0x330 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_RESET_B_GPIO2_IO10
> 0x0C8 0x330 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE
> 0x0CC 0x334 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD1_STROBE_GPIO2_IO11
> 0x0CC 0x334 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CD_B_USDHC2_CD_B
> 0x0D0 0x338 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12
> 0x0D0 0x338 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK
> 0x0D4 0x33C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_GPIO2_IO13
> 0x0D4 0x33C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_CCMSRCGPCMIX_OBSERVE0
> 0x0D4 0x33C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_CLK_OBSERVE_MUX_OUT0
> 0x0D4 0x33C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD
> 0x0D8 0x340 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_GPIO2_IO14
> 0x0D8 0x340 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_CCMSRCGPCMIX_OBSERVE1
> 0x0D8 0x340 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_CMD_OBSERVE_MUX_OUT1
> 0x0D8 0x340 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0
> 0x0DC 0x344 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_GPIO2_IO15
> 0x0DC 0x344 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_CCMSRCGPCMIX_OBSERVE2
> 0x0DC 0x344 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA0_OBSERVE_MUX_OUT2
> 0x0DC 0x344 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1
> 0x0E0 0x348 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_GPIO2_IO16
> 0x0E0 0x348 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_CCMSRCGPCMIX_WAIT
> 0x0E0 0x348 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA1_OBSERVE_MUX_OUT3
> 0x0E0 0x348 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2
> 0x0E4 0x34C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_GPIO2_IO17
> 0x0E4 0x34C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_CCMSRCGPCMIX_STOP
> 0x0E4 0x34C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA2_OBSERVE_MUX_OUT4
> 0x0E4 0x34C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3
> 0x0E8 0x350 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_GPIO2_IO18
> 0x0E8 0x350 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_DATA3_CCMSRCGPCMIX_EARLY_RESET
> 0x0E8 0x350 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_USDHC2_RESET_B
> 0x0EC 0x354 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19
> 0x0EC 0x354 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_RESET_B_CCMSRCGPCMIX_SYSTEM_RESET
> 0x0EC 0x354 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_USDHC2_WP
> 0x0F0 0x358 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_GPIO2_IO20
> 0x0F0 0x358 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SD2_WP_SIM_M_HMASTLOCK
> 0x0F0 0x358 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_RAWNAND_ALE
> 0x0F4 0x35C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK
> 0x0F4 0x35C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_GPIO3_IO0
> 0x0F4 0x35C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_ALE_SIM_M_HPROT0
> 0x0F4 0x35C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_RAWNAND_CE0_B
> 0x0F8 0x360 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B
> 0x0F8 0x360 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_GPIO3_IO1
> 0x0F8 0x360 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE0_B_SIM_M_HPROT1
> 0x0F8 0x360 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_RAWNAND_CE1_B
> 0x0FC 0x364 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_QSPI_A_SS1_B
> 0x0FC 0x364 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_GPIO3_IO2
> 0x0FC 0x364 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE1_B_SIM_M_HPROT2
> 0x0FC 0x364 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_RAWNAND_CE2_B
> 0x100 0x368 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_QSPI_B_SS0_B
> 0x100 0x368 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3
> 0x100 0x368 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE2_B_SIM_M_HPROT3
> 0x100 0x368 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_RAWNAND_CE3_B
> 0x104 0x36C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_QSPI_B_SS1_B
> 0x104 0x36C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_GPIO3_IO4
> 0x104 0x36C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CE3_B_SIM_M_HADDR0
> 0x104 0x36C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_RAWNAND_CLE
> 0x108 0x370 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_QSPI_B_SCLK
> 0x108 0x370 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5
> 0x108 0x370 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_CLE_SIM_M_HADDR1
> 0x108 0x370 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_RAWNAND_DATA00
> 0x10C 0x374 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0
> 0x10C 0x374 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_GPIO3_IO6
> 0x10C 0x374 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA00_SIM_M_HADDR2
> 0x10C 0x374 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_RAWNAND_DATA01
> 0x110 0x378 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1
> 0x110 0x378 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_GPIO3_IO7
> 0x110 0x378 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA01_SIM_M_HADDR3
> 0x110 0x378 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_RAWNAND_DATA02
> 0x114 0x37C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2
> 0x114 0x37C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_GPIO3_IO8
> 0x114 0x37C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA02_SIM_M_HADDR4
> 0x114 0x37C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_RAWNAND_DATA03
> 0x118 0x380 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3
> 0x118 0x380 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9
> 0x118 0x380 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA03_SIM_M_HADDR5
> 0x118 0x380 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_RAWNAND_DATA04
> 0x11C 0x384 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_QSPI_B_DATA0
> 0x11C 0x384 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_GPIO3_IO10
> 0x11C 0x384 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA04_SIM_M_HADDR6
> 0x11C 0x384 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_RAWNAND_DATA05
> 0x120 0x388 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_QSPI_B_DATA1
> 0x120 0x388 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_GPIO3_IO11
> 0x120 0x388 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA05_SIM_M_HADDR7
> 0x120 0x388 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_RAWNAND_DATA06
> 0x124 0x38C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_QSPI_B_DATA2
> 0x124 0x38C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_GPIO3_IO12
> 0x124 0x38C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA06_SIM_M_HADDR8
> 0x124 0x38C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_RAWNAND_DATA07
> 0x128 0x390 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_QSPI_B_DATA3
> 0x128 0x390 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_GPIO3_IO13
> 0x128 0x390 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DATA07_SIM_M_HADDR9
> 0x128 0x390 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_RAWNAND_DQS
> 0x12C 0x394 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_QSPI_A_DQS
> 0x12C 0x394 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_GPIO3_IO14
> 0x12C 0x394 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_DQS_SIM_M_HADDR10
> 0x12C 0x394 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_RAWNAND_RE_B
> 0x130 0x398 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_QSPI_B_DQS
> 0x130 0x398 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15
> 0x130 0x398 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_RE_B_SIM_M_HADDR11
> 0x130 0x398 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_RAWNAND_READY_B
> 0x134 0x39C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16
> 0x134 0x39C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_READY_B_SIM_M_HADDR12
> 0x134 0x39C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_RAWNAND_WE_B
> 0x138 0x3A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17
> 0x138 0x3A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_WE_B_SIM_M_HADDR13
> 0x138 0x3A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_RAWNAND_WP_B
> 0x13C 0x3A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18
> 0x13C 0x3A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_NAND_WP_B_SIM_M_HADDR14
> 0x13C 0x3A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC
> 0x140 0x3A8 0x4E4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_SAI1_TX_DATA0
> 0x140 0x3A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXFS_GPIO3_IO19
> 0x140 0x3A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK
> 0x144 0x3AC 0x4D0 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_SAI1_TX_DATA1
> 0x144 0x3AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXC_GPIO3_IO20
> 0x144 0x3AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0
> 0x148 0x3B0 0x4D4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_SAI1_TX_DATA2
> 0x148 0x3B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD0_GPIO3_IO21
> 0x148 0x3B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1
> 0x14C 0x3B4 0x4D8 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_DATA3
> 0x14C 0x3B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI1_TX_SYNC
> 0x14C 0x3B4 0x4CC 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_SAI5_TX_SYNC
> 0x14C 0x3B4 0x4EC 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD1_GPIO3_IO22
> 0x14C 0x3B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2
> 0x150 0x3B8 0x4DC 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_DATA4
> 0x150 0x3B8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI1_TX_SYNC
> 0x150 0x3B8 0x4CC 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI5_RXD2_SAI5_TX_BCLK
> 0x150 0x3B8 0x4E8 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23
> 0x150 0x3B8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3
> 0x154 0x3BC 0x4E0 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_DATA5
> 0x154 0x3BC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI1_TX_SYNC
> 0x154 0x3BC 0x4CC 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI5_RXD3_SAI5_TX_DATA0
> 0x154 0x3BC 0x000 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI5_RXD3_GPIO3_IO24
> 0x154 0x3BC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK
> 0x158 0x3C0 0x52C 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI1_TX_BCLK
> 0x158 0x3C0 0x4C8 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_SAI4_MCLK
> 0x158 0x3C0 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_GPIO3_IO25
> 0x158 0x3C0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI5_MCLK_CCMSRCGPCMIX_TESTER_ACK
> 0x158 0x3C0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI1_RX_SYNC
> 0x15C 0x3C4 0x4C4 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SAI5_RX_SYNC
> 0x15C 0x3C4 0x4E4 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXFS_CORESIGHT_TRACE_CLK
> 0x15C 0x3C4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_GPIO4_IO0
> 0x15C 0x3C4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXFS_SIM_M_HADDR15
> 0x15C 0x3C4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SAI1_RX_BCLK
> 0x160 0x3C8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SAI5_RX_BCLK
> 0x160 0x3C8 0x4D0 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXC_CORESIGHT_TRACE_CTL
> 0x160 0x3C8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_GPIO4_IO1
> 0x160 0x3C8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXC_SIM_M_HADDR16
> 0x160 0x3C8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0
> 0x164 0x3CC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0
> 0x164 0x3CC 0x4D4 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD0_CORESIGHT_TRACE0
> 0x164 0x3CC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_GPIO4_IO2
> 0x164 0x3CC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_CCMSRCGPCMIX_BOOT_CFG0
> 0x164 0x3CC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD0_SIM_M_HADDR17
> 0x164 0x3CC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1
> 0x168 0x3D0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SAI5_RX_DATA1
> 0x168 0x3D0 0x4D8 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD1_CORESIGHT_TRACE1
> 0x168 0x3D0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_GPIO4_IO3
> 0x168 0x3D0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_CCMSRCGPCMIX_BOOT_CFG1
> 0x168 0x3D0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD1_SIM_M_HADDR18
> 0x168 0x3D0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2
> 0x16C 0x3D4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SAI5_RX_DATA2
> 0x16C 0x3D4 0x4DC 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD2_CORESIGHT_TRACE2
> 0x16C 0x3D4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_GPIO4_IO4
> 0x16C 0x3D4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_CCMSRCGPCMIX_BOOT_CFG2
> 0x16C 0x3D4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD2_SIM_M_HADDR19
> 0x16C 0x3D4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3
> 0x170 0x3D8 0x4E0 0x0 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SAI5_RX_DATA3
> 0x170 0x3D8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_CORESIGHT_TRACE3
> 0x170 0x3D8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_GPIO4_IO5
> 0x170 0x3D8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_CCMSRCGPCMIX_BOOT_CFG3
> 0x170 0x3D8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD3_SIM_M_HADDR20
> 0x170 0x3D8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI1_RX_DATA4
> 0x174 0x3DC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_TX_BCLK
> 0x174 0x3DC 0x51C 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SAI6_RX_BCLK
> 0x174 0x3DC 0x510 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_CORESIGHT_TRACE4
> 0x174 0x3DC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_GPIO4_IO6
> 0x174 0x3DC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_CCMSRCGPCMIX_BOOT_CFG4
> 0x174 0x3DC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD4_SIM_M_HADDR21
> 0x174 0x3DC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_DATA5
> 0x178 0x3E0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_TX_DATA0
> 0x178 0x3E0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI6_RX_DATA0
> 0x178 0x3E0 0x514 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SAI1_RX_SYNC
> 0x178 0x3E0 0x4C4 0x3 0x1
> +#define MX8MQ_IOMUXC_SAI1_RXD5_CORESIGHT_TRACE5
> 0x178 0x3E0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_GPIO4_IO7
> 0x178 0x3E0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_CCMSRCGPCMIX_BOOT_CFG5
> 0x178 0x3E0 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD5_SIM_M_HADDR22
> 0x178 0x3E0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI1_RX_DATA6
> 0x17C 0x3E4 0x520 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_TX_SYNC
> 0x17C 0x3E4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SAI6_RX_SYNC
> 0x17C 0x3E4 0x518 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_CORESIGHT_TRACE6
> 0x17C 0x3E4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_GPIO4_IO8
> 0x17C 0x3E4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_CCMSRCGPCMIX_BOOT_CFG6
> 0x17C 0x3E4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD6_SIM_M_HADDR23
> 0x17C 0x3E4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_RX_DATA7
> 0x180 0x3E8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI6_MCLK
> 0x180 0x3E8 0x530 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC
> 0x180 0x3E8 0x4CC 0x2 0x4
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4
> 0x180 0x3E8 0x000 0x3 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_CORESIGHT_TRACE7
> 0x180 0x3E8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_GPIO4_IO9
> 0x180 0x3E8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_CCMSRCGPCMIX_BOOT_CFG7
> 0x180 0x3E8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_RXD7_SIM_M_HADDR24
> 0x180 0x3E8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC
> 0x184 0x3EC 0x4CC 0x0 0x3
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SAI5_TX_SYNC
> 0x184 0x3EC 0x4EC 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXFS_CORESIGHT_EVENTO
> 0x184 0x3EC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_GPIO4_IO10
> 0x184 0x3EC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXFS_SIM_M_HADDR25
> 0x184 0x3EC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK
> 0x188 0x3F0 0x4C8 0x0 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXC_SAI5_TX_BCLK
> 0x188 0x3F0 0x4E8 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXC_CORESIGHT_EVENTI
> 0x188 0x3F0 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_GPIO4_IO11
> 0x188 0x3F0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXC_SIM_M_HADDR26
> 0x188 0x3F0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0
> 0x18C 0x3F4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SAI5_TX_DATA0
> 0x18C 0x3F4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_CORESIGHT_TRACE8
> 0x18C 0x3F4 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_GPIO4_IO12
> 0x18C 0x3F4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_CCMSRCGPCMIX_BOOT_CFG8
> 0x18C 0x3F4 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD0_SIM_M_HADDR27
> 0x18C 0x3F4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1
> 0x190 0x3F8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SAI5_TX_DATA1
> 0x190 0x3F8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_CORESIGHT_TRACE9
> 0x190 0x3F8 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_GPIO4_IO13
> 0x190 0x3F8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_CCMSRCGPCMIX_BOOT_CFG9
> 0x190 0x3F8 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD1_SIM_M_HADDR28
> 0x190 0x3F8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2
> 0x194 0x3FC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SAI5_TX_DATA2
> 0x194 0x3FC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_CORESIGHT_TRACE10
> 0x194 0x3FC 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_GPIO4_IO14
> 0x194 0x3FC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_CCMSRCGPCMIX_BOOT_CFG10
> 0x194 0x3FC 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD2_SIM_M_HADDR29
> 0x194 0x3FC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3
> 0x198 0x400 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SAI5_TX_DATA3
> 0x198 0x400 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_CORESIGHT_TRACE11
> 0x198 0x400 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_GPIO4_IO15
> 0x198 0x400 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_CCMSRCGPCMIX_BOOT_CFG11
> 0x198 0x400 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD3_SIM_M_HADDR30
> 0x198 0x400 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4
> 0x19C 0x404 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_RX_BCLK
> 0x19C 0x404 0x510 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SAI6_TX_BCLK
> 0x19C 0x404 0x51C 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD4_CORESIGHT_TRACE12
> 0x19C 0x404 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_GPIO4_IO16
> 0x19C 0x404 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_CCMSRCGPCMIX_BOOT_CFG12
> 0x19C 0x404 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD4_SIM_M_HADDR31
> 0x19C 0x404 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5
> 0x1A0 0x408 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_RX_DATA0
> 0x1A0 0x408 0x514 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SAI6_TX_DATA0
> 0x1A0 0x408 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_CORESIGHT_TRACE13
> 0x1A0 0x408 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_GPIO4_IO17
> 0x1A0 0x408 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_CCMSRCGPCMIX_BOOT_CFG13
> 0x1A0 0x408 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD5_SIM_M_HBURST0
> 0x1A0 0x408 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6
> 0x1A4 0x40C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_RX_SYNC
> 0x1A4 0x40C 0x518 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SAI6_TX_SYNC
> 0x1A4 0x40C 0x520 0x2 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD6_CORESIGHT_TRACE14
> 0x1A4 0x40C 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_GPIO4_IO18
> 0x1A4 0x40C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_CCMSRCGPCMIX_BOOT_CFG14
> 0x1A4 0x40C 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD6_SIM_M_HBURST1
> 0x1A4 0x40C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7
> 0x1A8 0x410 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SAI6_MCLK
> 0x1A8 0x410 0x530 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_TXD7_CORESIGHT_TRACE15
> 0x1A8 0x410 0x000 0x4 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_GPIO4_IO19
> 0x1A8 0x410 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_CCMSRCGPCMIX_BOOT_CFG15
> 0x1A8 0x410 0x000 0x6 0x0
> +#define MX8MQ_IOMUXC_SAI1_TXD7_SIM_M_HBURST2
> 0x1A8 0x410 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK
> 0x1AC 0x414 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI5_MCLK
> 0x1AC 0x414 0x52C 0x1 0x1
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK
> 0x1AC 0x414 0x4C8 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI1_MCLK_GPIO4_IO20
> 0x1AC 0x414 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI1_MCLK_SIM_M_HRESP
> 0x1AC 0x414 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI2_RX_SYNC
> 0x1B0 0x418 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SAI5_TX_SYNC
> 0x1B0 0x418 0x4EC 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_RXFS_GPIO4_IO21
> 0x1B0 0x418 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXFS_SIM_M_HSIZE0
> 0x1B0 0x418 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SAI2_RX_BCLK
> 0x1B4 0x41C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SAI5_TX_BCLK
> 0x1B4 0x41C 0x4E8 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_RXC_GPIO4_IO22
> 0x1B4 0x41C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXC_SIM_M_HSIZE1
> 0x1B4 0x41C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0
> 0x1B8 0x420 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SAI5_TX_DATA0
> 0x1B8 0x420 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_GPIO4_IO23
> 0x1B8 0x420 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_RXD0_SIM_M_HSIZE2
> 0x1B8 0x420 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC
> 0x1BC 0x424 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SAI5_TX_DATA1
> 0x1BC 0x424 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_GPIO4_IO24
> 0x1BC 0x424 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXFS_SIM_M_HWRITE
> 0x1BC 0x424 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK
> 0x1C0 0x428 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SAI5_TX_DATA2
> 0x1C0 0x428 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_GPIO4_IO25
> 0x1C0 0x428 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXC_SIM_M_HREADYOUT
> 0x1C0 0x428 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0
> 0x1C4 0x42C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_SAI5_TX_DATA3
> 0x1C4 0x42C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_GPIO4_IO26
> 0x1C4 0x42C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_TXD0_TPSMP_CLK
> 0x1C4 0x42C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK
> 0x1C8 0x430 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_SAI5_MCLK
> 0x1C8 0x430 0x52C 0x1 0x2
> +#define MX8MQ_IOMUXC_SAI2_MCLK_GPIO4_IO27
> 0x1C8 0x430 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI2_MCLK_TPSMP_HDATA_DIR
> 0x1C8 0x430 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI3_RX_SYNC
> 0x1CC 0x434 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_GPT1_CAPTURE1
> 0x1CC 0x434 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_SAI5_RX_SYNC
> 0x1CC 0x434 0x4E4 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXFS_GPIO4_IO28
> 0x1CC 0x434 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXFS_TPSMP_HTRANS0
> 0x1CC 0x434 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_SAI3_RX_BCLK
> 0x1D0 0x438 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_GPT1_CAPTURE2
> 0x1D0 0x438 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_SAI5_RX_BCLK
> 0x1D0 0x438 0x4D0 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXC_GPIO4_IO29
> 0x1D0 0x438 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXC_TPSMP_HTRANS1
> 0x1D0 0x438 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_SAI3_RX_DATA0
> 0x1D4 0x43C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_GPT1_COMPARE1
> 0x1D4 0x43C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_SAI5_RX_DATA0
> 0x1D4 0x43C 0x4D4 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_RXD_GPIO4_IO30
> 0x1D4 0x43C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_RXD_TPSMP_HDATA0
> 0x1D4 0x43C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC
> 0x1D8 0x440 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_GPT1_CLK
> 0x1D8 0x440 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_SAI5_RX_DATA1
> 0x1D8 0x440 0x4D8 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXFS_GPIO4_IO31
> 0x1D8 0x440 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXFS_TPSMP_HDATA1
> 0x1D8 0x440 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_SAI3_TX_BCLK
> 0x1DC 0x444 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_GPT1_COMPARE2
> 0x1DC 0x444 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_SAI5_RX_DATA2
> 0x1DC 0x444 0x4DC 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXC_GPIO5_IO0
> 0x1DC 0x444 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXC_TPSMP_HDATA2
> 0x1DC 0x444 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_SAI3_TX_DATA0
> 0x1E0 0x448 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_GPT1_COMPARE3
> 0x1E0 0x448 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_SAI5_RX_DATA3
> 0x1E0 0x448 0x4E0 0x2 0x2
> +#define MX8MQ_IOMUXC_SAI3_TXD_GPIO5_IO1
> 0x1E0 0x448 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_TXD_TPSMP_HDATA3
> 0x1E0 0x448 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI3_MCLK
> 0x1E4 0x44C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_PWM4_OUT
> 0x1E4 0x44C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_SAI5_MCLK
> 0x1E4 0x44C 0x52C 0x2 0x3
> +#define MX8MQ_IOMUXC_SAI3_MCLK_GPIO5_IO2
> 0x1E4 0x44C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SAI3_MCLK_TPSMP_HDATA4
> 0x1E4 0x44C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT
> 0x1E8 0x450 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_PWM3_OUT
> 0x1E8 0x450 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_GPIO5_IO3
> 0x1E8 0x450 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_TX_TPSMP_HDATA5
> 0x1E8 0x450 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN
> 0x1EC 0x454 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_PWM2_OUT
> 0x1EC 0x454 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_GPIO5_IO4
> 0x1EC 0x454 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_RX_TPSMP_HDATA6
> 0x1EC 0x454 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_SPDIF1_EXT_CLK
> 0x1F0 0x458 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_PWM1_OUT
> 0x1F0 0x458 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5
> 0x1F0 0x458 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_SPDIF_EXT_CLK_TPSMP_HDATA7
> 0x1F0 0x458 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK
> 0x1F4 0x45C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX
> 0x1F4 0x45C 0x504 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_UART3_DTE_TX
> 0x1F4 0x45C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_GPIO5_IO6
> 0x1F4 0x45C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SCLK_TPSMP_HDATA8
> 0x1F4 0x45C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI
> 0x1F8 0x460 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX
> 0x1F8 0x460 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_UART3_DTE_RX
> 0x1F8 0x460 0x504 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7
> 0x1F8 0x460 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MOSI_TPSMP_HDATA9
> 0x1F8 0x460 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_ECSPI1_MISO
> 0x1FC 0x464 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B
> 0x1FC 0x464 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DTE_RTS_B
> 0x1FC 0x464 0x500 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_GPIO5_IO8
> 0x1FC 0x464 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_MISO_TPSMP_HDATA10
> 0x1FC 0x464 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_ECSPI1_SS0
> 0x200 0x468 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B
> 0x200 0x468 0x500 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DTE_CTS_B
> 0x200 0x468 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_GPIO5_IO9
> 0x200 0x468 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI1_SS0_TPSMP_HDATA11
> 0x200 0x468 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK
> 0x204 0x46C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DCE_RX
> 0x204 0x46C 0x50C 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_UART4_DTE_TX
> 0x204 0x46C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10
> 0x204 0x46C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SCLK_TPSMP_HDATA12
> 0x204 0x46C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI
> 0x208 0x470 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DCE_TX
> 0x208 0x470 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_UART4_DTE_RX
> 0x208 0x470 0x50C 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_GPIO5_IO11
> 0x208 0x470 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MOSI_TPSMP_HDATA13
> 0x208 0x470 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_ECSPI2_MISO
> 0x20C 0x474 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DCE_CTS_B
> 0x20C 0x474 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_UART4_DTE_RTS_B
> 0x20C 0x474 0x508 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12
> 0x20C 0x474 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_MISO_TPSMP_HDATA14
> 0x20C 0x474 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_ECSPI2_SS0
> 0x210 0x478 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DCE_RTS_B
> 0x210 0x478 0x508 0x1 0x1
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_UART4_DTE_CTS_B
> 0x210 0x478 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_GPIO5_IO13
> 0x210 0x478 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_ECSPI2_SS0_TPSMP_HDATA15
> 0x210 0x478 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL
> 0x214 0x47C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_ENET1_MDC
> 0x214 0x47C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_GPIO5_IO14
> 0x214 0x47C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C1_SCL_TPSMP_HDATA16
> 0x214 0x47C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA
> 0x218 0x480 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_ENET1_MDIO
> 0x218 0x480 0x4C0 0x1 0x2
> +#define MX8MQ_IOMUXC_I2C1_SDA_GPIO5_IO15
> 0x218 0x480 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C1_SDA_TPSMP_HDATA17
> 0x218 0x480 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL
> 0x21C 0x484 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_ENET1_1588_EVENT1_IN
> 0x21C 0x484 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_GPIO5_IO16
> 0x21C 0x484 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C2_SCL_TPSMP_HDATA18
> 0x21C 0x484 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA
> 0x220 0x488 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_ENET1_1588_EVENT1_OUT
> 0x220 0x488 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_GPIO5_IO17
> 0x220 0x488 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C2_SDA_TPSMP_HDATA19
> 0x220 0x488 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL
> 0x224 0x48C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_PWM4_OUT
> 0x224 0x48C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_GPT2_CLK
> 0x224 0x48C 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_GPIO5_IO18
> 0x224 0x48C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C3_SCL_TPSMP_HDATA20
> 0x224 0x48C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA
> 0x228 0x490 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_PWM3_OUT
> 0x228 0x490 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_GPT3_CLK
> 0x228 0x490 0x000 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_GPIO5_IO19
> 0x228 0x490 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C3_SDA_TPSMP_HDATA21
> 0x228 0x490 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_I2C4_SCL
> 0x22C 0x494 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_PWM2_OUT
> 0x22C 0x494 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B
> 0x22C 0x494 0x524 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_GPIO5_IO20
> 0x22C 0x494 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C4_SCL_TPSMP_HDATA22
> 0x22C 0x494 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_I2C4_SDA
> 0x230 0x498 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_PWM1_OUT
> 0x230 0x498 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B
> 0x230 0x498 0x528 0x2 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_GPIO5_IO21
> 0x230 0x498 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_I2C4_SDA_TPSMP_HDATA23
> 0x230 0x498 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX
> 0x234 0x49C 0x4F4 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_UART1_DTE_TX
> 0x234 0x49C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_ECSPI3_SCLK
> 0x234 0x49C 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_GPIO5_IO22
> 0x234 0x49C 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART1_RXD_TPSMP_HDATA24
> 0x234 0x49C 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX
> 0x238 0x4A0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_UART1_DTE_RX
> 0x238 0x4A0 0x4F4 0x0 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_ECSPI3_MOSI
> 0x238 0x4A0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_GPIO5_IO23
> 0x238 0x4A0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART1_TXD_TPSMP_HDATA25
> 0x238 0x4A0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX
> 0x23C 0x4A4 0x4FC 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_UART2_DTE_TX
> 0x23C 0x4A4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_ECSPI3_MISO
> 0x23C 0x4A4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_GPIO5_IO24
> 0x23C 0x4A4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART2_RXD_TPSMP_HDATA26
> 0x23C 0x4A4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX
> 0x240 0x4A8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_UART2_DTE_RX
> 0x240 0x4A8 0x4FC 0x0 0x1
> +#define MX8MQ_IOMUXC_UART2_TXD_ECSPI3_SS0
> 0x240 0x4A8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_GPIO5_IO25
> 0x240 0x4A8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART2_TXD_TPSMP_HDATA27
> 0x240 0x4A8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX
> 0x244 0x4AC 0x504 0x0 0x2
> +#define MX8MQ_IOMUXC_UART3_RXD_UART3_DTE_TX
> 0x244 0x4AC 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DCE_CTS_B
> 0x244 0x4AC 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_UART1_DTE_RTS_B
> 0x244 0x4AC 0x4F0 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_GPIO5_IO26
> 0x244 0x4AC 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART3_RXD_TPSMP_HDATA28
> 0x244 0x4AC 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX
> 0x248 0x4B0 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_UART3_DTE_RX
> 0x248 0x4B0 0x504 0x0 0x3
> +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DCE_RTS_B
> 0x248 0x4B0 0x4F0 0x1 0x1
> +#define MX8MQ_IOMUXC_UART3_TXD_UART1_DTE_CTS_B
> 0x248 0x4B0 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_GPIO5_IO27
> 0x248 0x4B0 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART3_TXD_TPSMP_HDATA29
> 0x248 0x4B0 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DCE_RX
> 0x24C 0x4B4 0x50C 0x0 0x2
> +#define MX8MQ_IOMUXC_UART4_RXD_UART4_DTE_TX
> 0x24C 0x4B4 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DCE_CTS_B
> 0x24C 0x4B4 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_UART2_DTE_RTS_B
> 0x24C 0x4B4 0x4F8 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_PCIE1_CLKREQ_B
> 0x24C 0x4B4 0x524 0x2 0x1
> +#define MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28
> 0x24C 0x4B4 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART4_RXD_TPSMP_HDATA30
> 0x24C 0x4B4 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DCE_TX
> 0x250 0x4B8 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_UART4_DTE_RX
> 0x250 0x4B8 0x50C 0x0 0x3
> +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DCE_RTS_B
> 0x250 0x4B8 0x4F8 0x1 0x1
> +#define MX8MQ_IOMUXC_UART4_TXD_UART2_DTE_CTS_B
> 0x250 0x4B8 0x000 0x1 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_PCIE2_CLKREQ_B
> 0x250 0x4B8 0x528 0x2 0x1
> +#define MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29
> 0x250 0x4B8 0x000 0x5 0x0
> +#define MX8MQ_IOMUXC_UART4_TXD_TPSMP_HDATA31
> 0x250 0x4B8 0x000 0x7 0x0
> +#define MX8MQ_IOMUXC_TEST_MODE
> 0x000 0x254 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_BOOT_MODE0
> 0x000 0x258 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_BOOT_MODE1
> 0x000 0x25C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_MOD
> 0x000 0x260 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TRST_B
> 0x000 0x264 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TDI
> 0x000 0x268 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TMS
> 0x000 0x26C 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TCK
> 0x000 0x270 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_JTAG_TDO
> 0x000 0x274 0x000 0x0 0x0
> +#define MX8MQ_IOMUXC_RTC
> 0x000 0x278 0x000 0x0 0x0
> +
> +#endif /* __DTS_IMX8MQ_PINFUNC_H */
> diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> new file mode 100644
> index 000000000000..50ed302d299a
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi
> @@ -0,0 +1,411 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright 2017 NXP
> + * Copyright (C) 2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
> + */
> +
> +#include <dt-bindings/clock/imx8mq-clock.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include "imx8mq-pinfunc.h"
> +
> +/* first 128 KiB of memory are owned by ATF */
> +/memreserve/ 0x40000000 0x00020000;
> +
> +/ {
> +	/* This should really be the GPC, but we need a driver for this first */
> +	interrupt-parent = <&gic>;
> +
> +	#address-cells = <2>;
> +	#size-cells = <2>;
> +
> +	aliases {
> +		i2c0 = &i2c1;
> +		i2c1 = &i2c2;
> +		i2c2 = &i2c3;
> +		i2c3 = &i2c4;
> +		serial0 = &uart1;
> +		serial1 = &uart2;
> +		serial2 = &uart3;
> +		serial3 = &uart4;
> +	};
> +
> +	ckil: clk-ckil {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <32768>;
> +		clock-output-names = "ckil";
> +	};
> +
> +	osc_25m: clk-osc-25m {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <25000000>;
> +		clock-output-names = "osc_25m";
> +	};
> +
> +	osc_27m: clk-osc-27m {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <27000000>;
> +		clock-output-names = "osc_27m";
> +	};
> +
> +	clk_ext1: clk-ext1 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <133000000>;
> +		clock-output-names = "clk_ext1";
> +	};
> +
> +	clk_ext2: clk-ext2 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <133000000>;
> +		clock-output-names = "clk_ext2";
> +	};
> +
> +	clk_ext3: clk-ext3 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency = <133000000>;
> +		clock-output-names = "clk_ext3";
> +	};
> +
> +	clk_ext4: clk-ext4 {
> +		compatible = "fixed-clock";
> +		#clock-cells = <0>;
> +		clock-frequency= <133000000>;
> +		clock-output-names = "clk_ext4";
> +	};
> +
> +	cpus {
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +
> +		idle-states {
> +			entry-method = "psci";
> +
> +			CPU_SLEEP: cpu-sleep {
> +				compatible = "arm,idle-state";
> +				arm,psci-suspend-param = <0x0010033>;
> +				local-timer-stop;
> +				entry-latency-us = <1000>;
> +				exit-latency-us = <700>;
> +				min-residency-us = <2700>;
> +				wakeup-latency-us = <1500>;
> +			};
> +		};
> +
> +		A53_0: cpu at 0 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x0>;
> +			enable-method = "psci";
> +			next-level-cache = <&A53_L2>;
> +			cpu-idle-states = <&CPU_SLEEP>;
> +		};
> +
> +		A53_1: cpu at 1 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x1>;
> +			enable-method = "psci";
> +			next-level-cache = <&A53_L2>;
> +			cpu-idle-states = <&CPU_SLEEP>;
> +		};
> +
> +		A53_2: cpu at 2 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x2>;
> +			enable-method = "psci";
> +			next-level-cache = <&A53_L2>;
> +			cpu-idle-states = <&CPU_SLEEP>;
> +		};
> +
> +		A53_3: cpu at 3 {
> +			device_type = "cpu";
> +			compatible = "arm,cortex-a53";
> +			reg = <0x3>;
> +			enable-method = "psci";
> +			next-level-cache = <&A53_L2>;
> +			cpu-idle-states = <&CPU_SLEEP>;
> +		};
> +
> +		A53_L2: l2-cache0 {
> +			compatible = "cache";
> +		};
> +	};
> +
> +	psci {
> +		compatible = "arm,psci-1.0";
> +		method = "smc";
> +	};
> +
> +	timer {
> +		compatible = "arm,armv8-timer";
> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Secure */
> +		             <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
> +		             <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>, /* Virtual */
> +		             <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) |
> IRQ_TYPE_LEVEL_LOW)>; /* Hypervisor */
> +		clock-frequency = <8333333>;
> +		interrupt-parent = <&gic>;
> +		arm,no-tick-in-suspend;
> +	};
> +
> +	peripherals at 0 {
> +		compatible = "simple-bus";
> +		#address-cells = <1>;
> +		#size-cells = <1>;
> +		ranges = <0x0 0x0 0x0 0x3e000000>;
> +
> +		bus at 30000000 { /* AIPS1 */
> +			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x30000000 0x30000000 0x400000>;
> +
> +			gpio1: gpio at 30200000 {
> +				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg = <0x30200000 0x10000>;
> +				interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>,
> +				             <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio2: gpio at 30210000 {
> +				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg = <0x30210000 0x10000>;
> +				interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
> +				        <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio3: gpio at 30220000 {
> +				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg = <0x30220000 0x10000>;
> +				interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
> +				        <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio4: gpio at 30230000 {
> +				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg = <0x30230000 0x10000>;
> +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
> +				                <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			gpio5: gpio at 30240000 {
> +				compatible = "fsl,imx8mq-gpio", "fsl,imx35-gpio";
> +				reg = <0x30240000 0x10000>;
> +				interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
> +				        <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
> +				gpio-controller;
> +				#gpio-cells = <2>;
> +				interrupt-controller;
> +				#interrupt-cells = <2>;
> +			};
> +
> +			iomuxc: iomuxc at 30330000 {
> +				compatible = "fsl,imx8mq-iomuxc";
> +				reg = <0x30330000 0x10000>;
> +			};
> +
> +			gpr: iomuxc-gpr at 30340000 {
> +				compatible = "fsl,imx8mq-iomuxc-gpr", "syscon";
> +				reg = <0x30340000 0x10000>;
> +			};
> +
> +			anatop: anatop at 30360000 {
> +				compatible = "fsl,imx8mq-anatop", "syscon";
> +				reg = <0x30360000 0x10000>;
> +				interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
> +			clk: clock-controller at 30380000 {
> +				compatible = "fsl,imx8mq-ccm";
> +				reg = <0x30380000 0x10000>;
> +				interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
> +				             <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
> +				#clock-cells = <1>;
> +				clocks = <&ckil>, <&osc_25m>, <&osc_27m>,
> +				         <&clk_ext1>, <&clk_ext2>,
> +				         <&clk_ext3>, <&clk_ext4>;
> +				clock-names = "ckil", "osc_25m", "osc_27m",
> +				              "clk_ext1", "clk_ext2",
> +				              "clk_ext3", "clk_ext4";
> +			};
> +		};
> +
> +		bus at 30400000 { /* AIPS2 */
> +			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x30400000 0x30400000 0x400000>;
> +		};
> +
> +		bus at 30800000 { /* AIPS3 */
> +			compatible = "fsl,imx8mq-aips-bus", "simple-bus";
> +			#address-cells = <1>;
> +			#size-cells = <1>;
> +			ranges = <0x30800000 0x30800000 0x400000>;
> +
> +			uart1: serial at 30860000 {
> +				compatible = "fsl,imx8mq-uart",
> +				             "fsl,imx6q-uart";
> +				reg = <0x30860000 0x10000>;
> +				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_UART1_ROOT>,
> +				         <&clk IMX8MQ_CLK_UART1_ROOT>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
> +			uart3: serial at 30880000 {
> +				compatible = "fsl,imx8mq-uart",
> +				             "fsl,imx6q-uart";
> +				reg = <0x30880000 0x10000>;
> +				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_UART3_ROOT>,
> +				         <&clk IMX8MQ_CLK_UART3_ROOT>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
> +			uart2: serial at 30890000 {
> +				compatible = "fsl,imx8mq-uart",
> +				             "fsl,imx6q-uart";
> +				reg = <0x30890000 0x10000>;
> +				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_UART2_ROOT>,
> +				         <&clk IMX8MQ_CLK_UART2_ROOT>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
> +			i2c1: i2c at 30a20000 {
> +				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> +				reg = <0x30a20000 0x10000>;
> +				interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_I2C1_ROOT>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c2: i2c at 30a30000 {
> +				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> +				reg = <0x30a30000 0x10000>;
> +				interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_I2C2_ROOT>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c3: i2c at 30a40000 {
> +				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> +				reg = <0x30a40000 0x10000>;
> +				interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_I2C3_ROOT>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			i2c4: i2c at 30a50000 {
> +				compatible = "fsl,imx8mq-i2c", "fsl,imx21-i2c";
> +				reg = <0x30a50000 0x10000>;
> +				interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_I2C4_ROOT>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				status = "disabled";
> +			};
> +
> +			uart4: serial at 30a60000 {
> +				compatible = "fsl,imx8mq-uart",
> +				             "fsl,imx6q-uart";
> +				reg = <0x30a60000 0x10000>;
> +				interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_UART4_ROOT>,
> +				         <&clk IMX8MQ_CLK_UART4_ROOT>;
> +				clock-names = "ipg", "per";
> +				status = "disabled";
> +			};
> +
> +			usdhc1: usdhc at 30b40000 {
> +				compatible = "fsl,imx8mq-usdhc",
> +				             "fsl,imx7d-usdhc";
> +				reg = <0x30b40000 0x10000>;
> +				interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_DUMMY>,
> +				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> +				         <&clk IMX8MQ_CLK_USDHC1_ROOT>;
> +				clock-names = "ipg", "ahb", "per";
> +				fsl,tuning-start-tap = <20>;
> +				fsl,tuning-step = <2>;
> +				bus-width = <4>;
> +				status = "disabled";
> +			};
> +
> +			usdhc2: usdhc at 30b50000 {
> +				compatible = "fsl,imx8mq-usdhc",
> +				             "fsl,imx7d-usdhc";
> +				reg = <0x30b50000 0x10000>;
> +				interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_DUMMY>,
> +				         <&clk IMX8MQ_CLK_NAND_USDHC_BUS_DIV>,
> +				         <&clk IMX8MQ_CLK_USDHC2_ROOT>;
> +				clock-names = "ipg", "ahb", "per";
> +				fsl,tuning-start-tap = <20>;
> +				fsl,tuning-step = <2>;
> +				bus-width = <4>;
> +				status = "disabled";
> +			};
> +
> +			fec1: ethernet at 30be0000 {
> +				compatible = "fsl,imx8mq-fec", "fsl,imx6sx-fec";
> +				reg = <0x30be0000 0x10000>;
> +				interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
> +				             <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
> +				             <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
> +				clocks = <&clk IMX8MQ_CLK_ENET1_ROOT>,
> +				         <&clk IMX8MQ_CLK_ENET1_ROOT>,
> +				         <&clk IMX8MQ_CLK_ENET_TIMER_DIV>,
> +				         <&clk IMX8MQ_CLK_ENET_REF_DIV>,
> +				         <&clk IMX8MQ_CLK_ENET_PHY_REF_DIV>;
> +				clock-names = "ipg", "ahb", "ptp",
> +				              "enet_clk_ref", "enet_out";
> +				fsl,num-tx-queues = <3>;
> +				fsl,num-rx-queues = <3>;
> +				status = "disabled";
> +			};
> +		};
> +
> +		gic: interrupt-controller at 38800000 {
> +			compatible = "arm,gic-v3";
> +			reg = <0x38800000 0x10000>, /* GIC Dist */
> +			      <0x38880000 0xc0000>; /* GICR (RD_base + SGI_base)
> */
> +			#interrupt-cells = <3>;
> +			interrupt-controller;
> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-parent = <&gic>;
> +		};
> +	};
> +};
> --
> 2.15.1