From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59B45C433F5 for ; Mon, 18 Oct 2021 03:06:38 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4209761050 for ; Mon, 18 Oct 2021 03:06:33 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4209761050 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id A78E9833CB; Mon, 18 Oct 2021 05:06:30 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Authentication-Results: phobos.denx.de; dkim=pass (2048-bit key; unprotected) header.d=aspeedtech.com header.i=@aspeedtech.com header.b="0qDvg8i/"; dkim-atps=neutral Received: by phobos.denx.de (Postfix, from userid 109) id CD3E08341B; Mon, 18 Oct 2021 05:06:28 +0200 (CEST) Received: from APC01-PU1-obe.outbound.protection.outlook.com (mail-pu1apc01on0702.outbound.protection.outlook.com [IPv6:2a01:111:f400:febe::702]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 71296833CB for ; Mon, 18 Oct 2021 05:06:23 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=aspeedtech.com Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=chiawei_wang@aspeedtech.com ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=ZPySCCctCteougBJ32A4zI14W3pzWBWPDq+oj+jmUCi6yJ6yhFPbo1YMPpb0sggxsyHuKdgoGaBy/JhHR2C6XsfLdfD6ciACtQGEmYTHdjtyNVdQ6wDN2asl9cNl2XtRgvGYlSdTuw9hE0YIjsJQdmI5jihp4MFIO6v+HzxgWiFVdMihjKm4wcS07HftpYDksG8nV+ijmhQSRn0xiTzRIvljLcN0oBufyXdMXNAmT+fVmyBYe4tY4dXkPNavF0CgHTawjUZHVOQ+TOs6gIAicGpuW1sg2FTnL5KHd7Srfqr5SC+Bw2/zj7WNXhicgAlr2SUftBmLOon/N1meD+1eaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=l4u5f6jgyVO9xZD66vYLnCloqDWkSbDRxZkG7W79si0=; b=EkDhkKyqzLMEeIR7UTE0eFX6Cbod7ho/GlETf6MWYPV6CBkNLXfpJvpF0X/tSmVq1TKbb5v73b1sxE+2U+jwAUz1JA4djWrqbK5HDenfb2fLTO+oA0MZrRldzHaL9zYqde481GVOeYCQlK93Zr6PjjQioVQGsINspYsOVYf/ZqehlYZv8QljefM+G85QwEuinsJcUTMjcaSsrsSjxK1IXSdw0HPmr/iVdSxP/MGQfdvAhYoOfm6SqGOHznjcQsImZJlq1MiNKhLYHWvWR+QZKGZzfUocG+ShdzTZvrJYIZaq/qd6KE7o4RqJszhZdJZ/8KgYgyElzJk05hhuTBuExw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass smtp.mailfrom=aspeedtech.com; dmarc=pass action=none header.from=aspeedtech.com; dkim=pass header.d=aspeedtech.com; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=aspeedtech.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=l4u5f6jgyVO9xZD66vYLnCloqDWkSbDRxZkG7W79si0=; b=0qDvg8i/De7KMqna5SF0t0tnMQ3KDk4irqCvieVRvqbFKJiCKk+WKnCKxGI2MghXwZjyxClt+itEC9PERsdD9w9vG0PbFLDwkunE6d/1lkNIx3m4nGeGiJ2uTAjGXU+iau6W94Zq3cC0NKsao98RMMFakPn2J8gfWLbdO7qzPhDxEm6SJdemRyVT9M3Z+U9wTJJNdjRtoVt7TfFfIvQz1OcUbjNnI8mWr44mSqSBP8xNcg6WRJbpoP8788a0gnDz2B/TxHvJQMW6k4vmj51tJBocprRUwOiinC8i5pyD/JxfW6lSLfquOW5xipkzj4obA+714KTXGLz5wCDTqlCnTw== Received: from HK0PR06MB3779.apcprd06.prod.outlook.com (2603:1096:203:b8::10) by HK0PR06MB2690.apcprd06.prod.outlook.com (2603:1096:203:53::11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4608.16; Mon, 18 Oct 2021 03:06:19 +0000 Received: from HK0PR06MB3779.apcprd06.prod.outlook.com ([fe80::f4aa:d005:b469:2a71]) by HK0PR06MB3779.apcprd06.prod.outlook.com ([fe80::f4aa:d005:b469:2a71%6]) with mapi id 15.20.4608.018; Mon, 18 Oct 2021 03:06:18 +0000 From: ChiaWei Wang To: ChiaWei Wang , "lukma@denx.de" , "sjg@chromium.org" , "trini@konsulko.com" , "mr.nuke.me@gmail.com" , "u-boot@lists.denx.de" CC: "joel@jms.id.au" , Ryan Chen , Johnny Huang Subject: RE: [PATCH next v6 07/12] crypto: aspeed: Add AST2600 ACRY support Thread-Topic: [PATCH next v6 07/12] crypto: aspeed: Add AST2600 ACRY support Thread-Index: AQHXwWk7ndiONEWKnkyoCJWc8sgUvavYFk4w Date: Mon, 18 Oct 2021 03:06:18 +0000 Message-ID: References: <20211015020337.1024-1-chiawei_wang@aspeedtech.com> <20211015020337.1024-8-chiawei_wang@aspeedtech.com> In-Reply-To: <20211015020337.1024-8-chiawei_wang@aspeedtech.com> Accept-Language: zh-TW, en-US Content-Language: zh-TW X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: aspeedtech.com; dkim=none (message not signed) header.d=none;aspeedtech.com; dmarc=none action=none header.from=aspeedtech.com; x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 4d1f7efb-64dd-4a09-7790-08d991e44195 x-ms-traffictypediagnostic: HK0PR06MB2690: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:390; x-ms-exchange-senderadcheck: 1 x-ms-exchange-antispam-relay: 0 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: OqYDa34Bz6ti1GOHTBPe9ctO7oSOpbLuFt/vpJEz2NaYJSiCM00JXLb5UhqhUO84UU5x4kBQ/4aEB1EVq/T5AoK4tPtghfAAiUW+HzgQAX3+5fNqZ6o9TZXN0bTkve7COQiArA8Isk3H02ObtXBuN9NuNkmeK0Cy9bAh0NIA2UFGxOsoeqAbQPTmut+KfcwhZrqtzF4XU9nmdvmH0EgX80Ze9y22fzao2TqALVbdLoRwqCMTHfY9+0ynqerwH8VKEnFR/wVk4fw223cq05gU+bjMuqWDNfzJjWap6z0pt6kWXsVLlIgC0R9aKmE2BQtAnckToGzygv0me3/0sJ8ozv+iKXxTSXFIKv5W4iN+YwGVqEixhIm54mJPuklBp7FtM+8MZZfh2+o8nXcihM6onJT6tFy/FCuL9xdV3PIxdxPsVxppS5+VUNMk3cXXDwTfY7w3XlGAxdOUCITLnkKUdk7P/zB4k2mKedXwrfgee+84Gm0Rr/cAkkWrtrQ5GwG5F075Mbl7oYQidRuInolUGUOBzxUklWTI11S2KFBrZx82sP0fsFwm+NKjzxvCC2O1ot3qT9RTwFOHlzVq4EH2nKpRr3qArTm1CgQvrMyxCBvm0/OB+VXZsPign19geuBso+rkc+SUKeDRp1jPLE/5UyGEABa/c+baSrFZaBQ/mSPHsKWy0Q0E2mnB8fpIwFVfNDIe1ZdetJmajHFDBxRSYw== x-forefront-antispam-report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:HK0PR06MB3779.apcprd06.prod.outlook.com; PTR:; CAT:NONE; SFS:(366004)(71200400001)(2906002)(64756008)(186003)(52536014)(26005)(6506007)(83380400001)(7696005)(38100700002)(107886003)(66946007)(110136005)(55016002)(122000001)(4326008)(54906003)(9686003)(33656002)(5660300002)(76116006)(38070700005)(8936002)(508600001)(316002)(8676002)(66476007)(66446008)(86362001)(66556008); DIR:OUT; SFP:1102; x-ms-exchange-antispam-messagedata-chunkcount: 1 x-ms-exchange-antispam-messagedata-0: =?us-ascii?Q?sa9cvbnMj4YwtF5VdIS/x6QzP4ZQf+KCtByCOol3zh+qo5zoUJa63WboXBQ7?= =?us-ascii?Q?s0F1G47XO6oQPT+tZNUACgNOAYDDkSZhHzhKx9an6s237yGIHVhJN5HCEWj5?= =?us-ascii?Q?dB10r2yaz4pgJ4NtagY8BFLNbiXpqTt+27RzmHy206LVZDM0r5mKjXhSDBFO?= =?us-ascii?Q?I9BLQK2tEiaTowhBkkliDTozgvAi90x9+P+I5gKMC3sTRgHUCnjrATiZD7uV?= =?us-ascii?Q?P+d4yYGhxm79X233qicCLU0Q0lmopbhEJmUSgVCJ4P0r06v1T/n0H6GkxtUK?= =?us-ascii?Q?w4+IVqmaJM4MFGNd6QGo4gYxzhaaUyb031GkzTHy4AyiZvxrDBe+IyfwYMOG?= =?us-ascii?Q?LIxYMMOE17e77CpQjDh04tOAHe+bDNJHPd3kXFf/X3fLYDyVh2+tOtXOpZv9?= =?us-ascii?Q?bkexW/Ro97QfcDy/7Oc6NKpQWRky0S2lb6whMY5Zsjw7BNEOVHOIT0I5ybjv?= =?us-ascii?Q?eJrdmk5xN/tCzeNYe800TXiMt83DydYh4oD8vXy6wDthO/CpGhpfDuYodAnf?= =?us-ascii?Q?/DlVGMiSUlKfDv6R9oXTgOsl2c9A9KfLxopJzFOGBnsPLlu9SRR57W0uy89A?= =?us-ascii?Q?mFiE0lnF5C6FS68Urj8bxktu85p6e4kIiA37I/iHz3BKITBIuq3o/iGBxkIR?= =?us-ascii?Q?NkJTHfHp4huWLRGTQeaS7DtXRoZKtmNHmorDjLcOdACpIwREeeKKuCRJQYD/?= =?us-ascii?Q?Yygbs/fSrWr4SJdiLEjJOwgfX+losevepZX8c5kIj/B+e/MA0VLJjOB/Gds3?= =?us-ascii?Q?eiKNjyY1vLmpzIDL8wVYP4Q64Eh1vBjwZEEWmBCarPb2QSqfiroUZOi5j0N/?= =?us-ascii?Q?pIMw1nEKP9rXi+UauIBIn8cdePn8MXClG7hf81VAvW050Xslq9s12B2DG29O?= =?us-ascii?Q?ofeGT6TtDAlCm8cTRQqftfYzJ7vB7nVqqOOgInB/I4vcJVNwYhXAd4YMFv9L?= =?us-ascii?Q?+5kIbDNU3mmq+sjUFqs3ZCNdXkhj9i0NaO0dYibhdwq8YqY9RoAYbtk+nrVo?= =?us-ascii?Q?VkrkQGtZBnqO7P4E2Aqg8D+AOs6GUvWQXqVesfIBq6DTvU+hzVB3ZQUjN95O?= =?us-ascii?Q?UTNNNa6ozxpHe5cVwwqJOdaUetABYImTx0i5PtKnHUItJyEnc2tOFUoA2Nxq?= =?us-ascii?Q?z8gBFTiklEAHS9xOzD0tro3faqDrzGMmsE/Yo+uGvcQz7TEAKcKTIdQ+wOr4?= =?us-ascii?Q?yau7otqTVF6j59AroMZKG4tdYXY8PA57/MaqJI7QfkLBhDBOUgemriPhntjQ?= =?us-ascii?Q?t15nOrSeiwvHz6yn6ROqKLbFL71JOmnxKYIA93FnuLkAwdm+fkfARbQACTyB?= =?us-ascii?Q?X3/6wwHdAbwiMi83klqQ7LH2?= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: HK0PR06MB3779.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4d1f7efb-64dd-4a09-7790-08d991e44195 X-MS-Exchange-CrossTenant-originalarrivaltime: 18 Oct 2021 03:06:18.6192 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 8mem6Lw7S73pgcErB58lo4jWbgTWDOTESIWtc9x/4BXlBlTR4Rpi2lYRAHCzmWO4jFzfn2UNfPZ0Mj7HCMj35OLuB8TUGtGFD5antKj1Src= X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK0PR06MB2690 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean > From: U-Boot On Behalf Of Chia-Wei Wang > Sent: Friday, October 15, 2021 10:04 AM >=20 > ACRY is deisnged to accerlerate ECC/RSA digital signature generation and > verification. >=20 > Signed-off-by: Chia-Wei Wang > --- > drivers/crypto/aspeed/Kconfig | 10 ++ > drivers/crypto/aspeed/Makefile | 1 + > drivers/crypto/aspeed/aspeed_acry.c | 182 > ++++++++++++++++++++++++++++ > lib/rsa/Kconfig | 10 +- > 4 files changed, 202 insertions(+), 1 deletion(-) create mode 100644 > drivers/crypto/aspeed/aspeed_acry.c >=20 > diff --git a/drivers/crypto/aspeed/Kconfig b/drivers/crypto/aspeed/Kconfi= g > index 471c06f986..9bf317177a 100644 > --- a/drivers/crypto/aspeed/Kconfig > +++ b/drivers/crypto/aspeed/Kconfig > @@ -8,3 +8,13 @@ config ASPEED_HACE > Enabling this allows the use of SHA operations in hardware without > requiring the SHA software implementations. It also improves > performance > and saves code size. > + > +config ASPEED_ACRY > + bool "ASPEED RSA and ECC Engine" > + depends on ASPEED_AST2600 > + help > + Select this option to enable a driver for using the RSA/ECC engine in > + the ASPEED BMC SoCs. > + > + Enabling this allows the use of RSA/ECC operations in hardware without > requiring the > + software implementations. It also improves performance and saves code > size. > diff --git a/drivers/crypto/aspeed/Makefile b/drivers/crypto/aspeed/Makef= ile > index 84e6bfe82a..58b55fc46e 100644 > --- a/drivers/crypto/aspeed/Makefile > +++ b/drivers/crypto/aspeed/Makefile > @@ -1 +1,2 @@ > obj-$(CONFIG_ASPEED_HACE) +=3D aspeed_hace.o > +obj-$(CONFIG_ASPEED_ACRY) +=3D aspeed_acry.o > diff --git a/drivers/crypto/aspeed/aspeed_acry.c > b/drivers/crypto/aspeed/aspeed_acry.c > new file mode 100644 > index 0000000000..0b948f828a > --- /dev/null > +++ b/drivers/crypto/aspeed/aspeed_acry.c > @@ -0,0 +1,182 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright 2021 ASPEED Technology Inc. > + */ > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +/* ACRY register offsets */ > +#define ACRY_CTRL1 0x00 > +#define ACRY_CTRL1_RSA_DMA BIT(1) > +#define ACRY_CTRL1_RSA_START BIT(0) > +#define ACRY_CTRL2 0x44 > +#define ACRY_CTRL3 0x48 > +#define ACRY_CTRL3_SRAM_AHB_ACCESS BIT(8) > +#define ACRY_CTRL3_ECC_RSA_MODE_MASK GENMASK(5, 4) > +#define ACRY_CTRL3_ECC_RSA_MODE_SHIFT 4 > +#define ACRY_DMA_DRAM_SADDR 0x4c > +#define ACRY_DMA_DMEM_TADDR 0x50 > +#define ACRY_DMA_DMEM_TADDR_LEN_MASK GENMASK(15, 0) > +#define ACRY_DMA_DMEM_TADDR_LEN_SHIFT 0 > +#define ACRY_RSA_PARAM 0x58 > +#define ACRY_RSA_PARAM_EXP_MASK GENMASK(31, 16) > +#define ACRY_RSA_PARAM_EXP_SHIFT 16 > +#define ACRY_RSA_PARAM_MOD_MASK GENMASK(15, 0) > +#define ACRY_RSA_PARAM_MOD_SHIFT 0 > +#define ACRY_RSA_INT_EN 0x3f8 > +#define ACRY_RSA_INT_EN_RSA_READY BIT(2) > +#define ACRY_RSA_INT_EN_RSA_CMPLT BIT(1) > +#define ACRY_RSA_INT_STS 0x3fc > +#define ACRY_RSA_INT_STS_RSA_READY BIT(2) > +#define ACRY_RSA_INT_STS_RSA_CMPLT BIT(1) > + > +/* misc. constant */ > +#define ACRY_ECC_MODE 2 > +#define ACRY_RSA_MODE 3 > +#define ACRY_CTX_BUFSZ 0x600 > + > +struct aspeed_acry { > + phys_addr_t base; > + phys_addr_t sram_base; /* internal sram */ > + struct clk clk; > +}; > + > +static int aspeed_acry_mod_exp(struct udevice *dev, const uint8_t *sig, > uint32_t sig_len, > + struct key_prop *prop, uint8_t *out) { > + int i, j; > + u8 *ctx; > + u8 *ptr; > + u32 reg; > + struct aspeed_acry *acry =3D dev_get_priv(dev); > + > + ctx =3D memalign(16, ACRY_CTX_BUFSZ); > + if (!ctx) > + return -ENOMEM; > + > + memset(ctx, 0, ACRY_CTX_BUFSZ); > + > + ptr =3D (u8 *)prop->public_exponent; > + for (i =3D prop->exp_len - 1, j =3D 0; i >=3D 0; --i) { > + ctx[j] =3D ptr[i]; > + j++; > + j =3D (j % 16) ? j : j + 32; > + } > + > + ptr =3D (u8 *)prop->modulus; > + for (i =3D (prop->num_bits >> 3) - 1, j =3D 0; i >=3D 0; --i) { > + ctx[j + 16] =3D ptr[i]; > + j++; > + j =3D (j % 16) ? j : j + 32; > + } > + > + ptr =3D (u8 *)sig; > + for (i =3D sig_len - 1, j =3D 0; i >=3D 0; --i) { > + ctx[j + 32] =3D ptr[i]; > + j++; > + j =3D (j % 16) ? j : j + 32; > + } > + > + writel((u32)ctx, acry->base + ACRY_DMA_DRAM_SADDR); > + > + reg =3D (((prop->exp_len << 3) << ACRY_RSA_PARAM_EXP_SHIFT) & > ACRY_RSA_PARAM_EXP_MASK) | > + ((prop->num_bits << ACRY_RSA_PARAM_MOD_SHIFT) & > ACRY_RSA_PARAM_MOD_MASK); > + writel(reg, acry->base + ACRY_RSA_PARAM); > + > + reg =3D (ACRY_CTX_BUFSZ << ACRY_DMA_DMEM_TADDR_LEN_SHIFT) & > ACRY_DMA_DMEM_TADDR_LEN_MASK; > + writel(reg, acry->base + ACRY_DMA_DMEM_TADDR); > + > + reg =3D (ACRY_RSA_MODE << ACRY_CTRL3_ECC_RSA_MODE_SHIFT) & > ACRY_CTRL3_ECC_RSA_MODE_MASK; > + writel(reg, acry->base + ACRY_CTRL3); > + > + writel(ACRY_CTRL1_RSA_DMA | ACRY_CTRL1_RSA_START, acry->base + > +ACRY_CTRL1); > + > + /* polling RSA status */ > + while (1) { > + reg =3D readl(acry->base + ACRY_RSA_INT_STS); > + if ((reg & ACRY_RSA_INT_STS_RSA_READY) && (reg & ACRY_RSA_INT_STS_RSA_= CMPLT)) > + break; Interrupt status clear is missed here. Will prepare v7 patch to fix this. Regards, Chiawei