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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: IA0PR11MB7307.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 15ea0f4d-90e9-4f99-a94a-08dc48965acd X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Mar 2024 04:29:38.5326 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: Y0kc6rTNXeSr0+wdLfne3gbnYowalxvA4FubO5/X5yJuM8ET5Mjqx50Y8f7xcapUoECSQnb1OU51kdqR4xMm1g== X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR11MB5904 X-OriginatorOrg: intel.com X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" > -----Original Message----- > From: Intel-gfx On Behalf Of Mi= tul > Golani > Sent: Monday, March 18, 2024 4:42 PM > To: intel-gfx@lists.freedesktop.org > Cc: Golani, Mitulkumar Ajitkumar > Subject: [PATCH v19 8/9] drm/i915/display: Compute vrr_vsync params >=20 > Compute vrr_vsync_start/end, which sets the position for hardware to send= the > Vsync at a fixed position relative to the end of the Vblank. >=20 > --v2: > - Updated VSYNC_START/END macros to VRR_VSYNC_START/END. (Ankit) > - Updated bit fields of VRR_VSYNC_START/END. (Ankit) >=20 > --v3: > - Add PIPE_CONF_CHECK_I(vrr.vsync_start/end). > - Read/write vrr_vsync params only when we intend to send adaptive_sync s= dp. >=20 > --v4: > - Use VRR_SYNC_START/END macros correctly. >=20 > --v5: > - Send AS SDP only when VRR is enabled. > Signed-off-by: Mitul Golani Reviewed-by: Arun R Murthy Thanks and Regards, Arun R Murthy -------------------- > --- > drivers/gpu/drm/i915/display/intel_display.c | 2 ++ > .../drm/i915/display/intel_display_types.h | 1 + > drivers/gpu/drm/i915/display/intel_vrr.c | 33 +++++++++++++++++-- > drivers/gpu/drm/i915/i915_reg.h | 7 ++++ > 4 files changed, 41 insertions(+), 2 deletions(-) >=20 > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > b/drivers/gpu/drm/i915/display/intel_display.c > index 8f1d948408d3..fed4ed18d53b 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -5377,6 +5377,8 @@ intel_pipe_config_compare(const struct > intel_crtc_state *current_config, > PIPE_CONF_CHECK_I(vrr.flipline); > PIPE_CONF_CHECK_I(vrr.pipeline_full); > PIPE_CONF_CHECK_I(vrr.guardband); > + PIPE_CONF_CHECK_I(vrr.vsync_start); > + PIPE_CONF_CHECK_I(vrr.vsync_end); > } >=20 > #undef PIPE_CONF_CHECK_X > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h > b/drivers/gpu/drm/i915/display/intel_display_types.h > index 8a286751dc39..c2e08f641989 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1430,6 +1430,7 @@ struct intel_crtc_state { > bool enable, in_range; > u8 pipeline_full; > u16 flipline, vmin, vmax, guardband; > + u32 vsync_end, vsync_start; > } vrr; >=20 > /* Stream Splitter for eDP MSO */ > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c > b/drivers/gpu/drm/i915/display/intel_vrr.c > index eb5bd0743902..1d53623e7e0b 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -9,6 +9,7 @@ > #include "intel_de.h" > #include "intel_display_types.h" > #include "intel_vrr.h" > +#include "intel_dp.h" >=20 > bool intel_vrr_is_capable(struct intel_connector *connector) { @@ -113,= 6 > +114,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state, > struct drm_i915_private *i915 =3D to_i915(crtc->base.dev); > struct intel_connector *connector =3D > to_intel_connector(conn_state->connector); > + struct intel_dp *intel_dp =3D intel_attached_dp(connector); > struct drm_display_mode *adjusted_mode =3D &crtc_state- > >hw.adjusted_mode; > const struct drm_display_info *info =3D &connector->base.display_info; > int vmin, vmax; > @@ -165,6 +167,14 @@ intel_vrr_compute_config(struct intel_crtc_state > *crtc_state, > if (crtc_state->uapi.vrr_enabled) { > crtc_state->vrr.enable =3D true; > crtc_state->mode_flags |=3D I915_MODE_FLAG_VRR; > + if (intel_dp_as_sdp_supported(intel_dp)) { > + crtc_state->vrr.vsync_start =3D > + (crtc_state->hw.adjusted_mode.crtc_vtotal - > + crtc_state- > >hw.adjusted_mode.vsync_start); > + crtc_state->vrr.vsync_end =3D > + (crtc_state->hw.adjusted_mode.crtc_vtotal - > + crtc_state- > >hw.adjusted_mode.vsync_end); > + } > } > } >=20 > @@ -242,6 +252,12 @@ void intel_vrr_enable(const struct intel_crtc_state > *crtc_state) > intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), > TRANS_PUSH_EN); > intel_de_write(dev_priv, TRANS_VRR_CTL(cpu_transcoder), > VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); > + > + if (HAS_AS_SDP(dev_priv)) { > + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), > + VRR_VSYNC_END(crtc_state->vrr.vsync_end) | > + VRR_VSYNC_START(crtc_state->vrr.vsync_start)); > + } > } >=20 > void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) @@= - > 258,13 +274,16 @@ void intel_vrr_disable(const struct intel_crtc_state > *old_crtc_state) > intel_de_wait_for_clear(dev_priv, > TRANS_VRR_STATUS(cpu_transcoder), > VRR_STATUS_VRR_EN_LIVE, 1000); > intel_de_write(dev_priv, TRANS_PUSH(cpu_transcoder), 0); > + > + if (HAS_AS_SDP(dev_priv)) > + intel_de_write(dev_priv, TRANS_VRR_VSYNC(cpu_transcoder), > 0); > } >=20 > void intel_vrr_get_config(struct intel_crtc_state *crtc_state) { > struct drm_i915_private *dev_priv =3D to_i915(crtc_state->uapi.crtc- > >dev); > enum transcoder cpu_transcoder =3D crtc_state->cpu_transcoder; > - u32 trans_vrr_ctl; > + u32 trans_vrr_ctl, trans_vrr_vsync; >=20 > trans_vrr_ctl =3D intel_de_read(dev_priv, > TRANS_VRR_CTL(cpu_transcoder)); >=20 > @@ -284,6 +303,16 @@ void intel_vrr_get_config(struct intel_crtc_state > *crtc_state) > crtc_state->vrr.vmin =3D intel_de_read(dev_priv, > TRANS_VRR_VMIN(cpu_transcoder)) + 1; > } >=20 > - if (crtc_state->vrr.enable) > + if (crtc_state->vrr.enable) { > crtc_state->mode_flags |=3D I915_MODE_FLAG_VRR; > + > + if (HAS_AS_SDP(dev_priv)) { > + trans_vrr_vsync =3D > + intel_de_read(dev_priv, > TRANS_VRR_VSYNC(cpu_transcoder)); > + crtc_state->vrr.vsync_start =3D > + REG_FIELD_GET(VRR_VSYNC_START_MASK, > trans_vrr_vsync); > + crtc_state->vrr.vsync_end =3D > + REG_FIELD_GET(VRR_VSYNC_END_MASK, > trans_vrr_vsync); > + } > + } > } > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h index 3ff6a38826cb..2ede6982175c > 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2095,6 +2095,13 @@ > #define TRANS_PUSH_EN REG_BIT(31) > #define TRANS_PUSH_SEND REG_BIT(30) >=20 > +#define _TRANS_VRR_VSYNC_A 0x60078 > +#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, > _TRANS_VRR_VSYNC_A) > +#define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) > +#define VRR_VSYNC_END(vsync_end) > REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) > +#define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) > +#define VRR_VSYNC_START(vsync_start) > REG_FIELD_PREP(VRR_VSYNC_START_MASK, (vsync_start)) > + > /* VGA port control */ > #define ADPA _MMIO(0x61100) > #define PCH_ADPA _MMIO(0xe1100) > -- > 2.25.1