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Albert Ou > ; linux-kernel@vger.kernel.org; Mike Rapoport > ; Christoph Hellwig ; Atish Patra > ; Gary Guo ; Paul Walmsley > ; linux-riscv@lists.infradead.org > Subject: Re: [PATCH v2] RISC-V: Implement ASID allocator >=20 > Hi Anup, >=20 > On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote: > > This patch is tested on QEMU/virt machine and SiFive Unleashed board. > > On QEMU/virt machine, we see 10% (approx) performance improvement > with > > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP > > CSR are not implemented on SiFive Unleashed board so we don't see any > > change in performance. > Can you tell me what is the test case ? I am testing this using hackbench. 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Tue, 9 Apr 2019 03:36:03 +0000 From: Anup Patel To: Guo Ren Subject: RE: [PATCH v2] RISC-V: Implement ASID allocator Thread-Topic: [PATCH v2] RISC-V: Implement ASID allocator Thread-Index: AQHU5TAIKaRDCttA7UazIjpcDaomMKYzNveAgAAJAEA= Date: Tue, 9 Apr 2019 03:36:03 +0000 Message-ID: References: <20190328063211.13052-1-anup.patel@wdc.com> <20190409030231.GA14861@guoren-Inspiron-7460> In-Reply-To: <20190409030231.GA14861@guoren-Inspiron-7460> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Anup.Patel@wdc.com; x-originating-ip: [129.253.179.161] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: 62262d5e-14db-4deb-bba6-08d6bc9c7dfc x-ms-office365-filtering-ht: Tenant x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600139)(711020)(4605104)(4618075)(2017052603328)(7193020); SRVR:MN2PR04MB6271; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+infradead-linux-riscv=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Guo Ren > Sent: Tuesday, April 9, 2019 8:33 AM > To: Anup Patel > Cc: Palmer Dabbelt ; Albert Ou > ; linux-kernel@vger.kernel.org; Mike Rapoport > ; Christoph Hellwig ; Atish Patra > ; Gary Guo ; Paul Walmsley > ; linux-riscv@lists.infradead.org > Subject: Re: [PATCH v2] RISC-V: Implement ASID allocator > > Hi Anup, > > On Thu, Mar 28, 2019 at 06:32:36AM +0000, Anup Patel wrote: > > This patch is tested on QEMU/virt machine and SiFive Unleashed board. > > On QEMU/virt machine, we see 10% (approx) performance improvement > with > > SW emulated TLBs provided by QEMU. Unfortunately, ASID bits of SATP > > CSR are not implemented on SiFive Unleashed board so we don't see any > > change in performance. > Can you tell me what is the test case ? I am testing this using hackbench. Regards, Anup _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv