From mboxrd@z Thu Jan  1 00:00:00 1970
From: Anup Patel <Anup.Patel@wdc.com>
Date: Mon, 11 Mar 2019 16:10:47 +0000
Subject: [U-Boot] [PATCH v2 0/9] SMP support for RISC-V
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 <mhng-944778c9-0d4f-4568-943c-4e59d0c74964@palmer-si-x1c4>
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> -----Original Message-----
> From: Palmer Dabbelt <palmer@sifive.com>
> Sent: Monday, March 11, 2019 5:26 PM
> To: Anup Patel <Anup.Patel@wdc.com>
> Cc: schwab at suse.de; Atish Patra <Atish.Patra@wdc.com>;
> anup at brainfault.org; lukas.auer at aisec.fraunhofer.de; Paul Walmsley
> <paul.walmsley@sifive.com>; agraf at suse.de; u-boot at lists.denx.de;
> baruch at tkos.co.il; daniel.schwierzeck at gmail.com; bmeng.cn at gmail.=
com;
> rick at andestech.com; sr at denx.de
> Subject: RE: [PATCH v2 0/9] SMP support for RISC-V
>=20
> On Thu, 07 Mar 2019 19:37:30 PST (-0800), Anup Patel wrote:
> >
> >
> >> -----Original Message-----
> >> From: Andreas Schwab <schwab@suse.de>
> >> Sent: Thursday, March 7, 2019 2:50 PM
> >> To: Anup Patel <Anup.Patel@wdc.com>
> >> Cc: Atish Patra <Atish.Patra@wdc.com>; Anup Patel
> >> <anup@brainfault.org>; Auer, Lukas <lukas.auer@aisec.fraunhofer.de>;
> >> paul.walmsley at sifive.com; agraf at suse.de; u-boot at lists.denx.de;
> >> baruch at tkos.co.il; daniel.schwierzeck at gmail.com;
> bmeng.cn at gmail.com;
> >> rick at andestech.com; sr at denx.de; palmer at sifive.com
> >> Subject: Re: [PATCH v2 0/9] SMP support for RISC-V
> >>
> >> On M=C3=A4r 07 2019, Anup Patel <Anup.Patel@wdc.com> wrote:
> >>
> >> > Like I mentioned, there is no functional issue with this series.
> >> > The warm-boot issues were fixed in OpenSBI.
> >> >
> >> > @Andreas, please try at your end.
> >>
> >> As long as issue#65 isn't fixed opensbi is mostly a no-go for me.  At
> >> least it gives me more reasons to press the reset button. :-)
> >
> > The reset button works fine for me an Atish. I am sure it works fine
> > for lot of other folks too.
> >
> > BTW, as-per discussion with SiFive folks the reset button on Unleashed
> > Board is not much tested and it can misbehave on certain boards. It is
> > quite possible that you might have a "flaky" board.
>=20
> I don't think the reset button differs between boards.  As far as I know,=
 the
> issues are really just that it doesn't reset everything -- specifically s=
ome of
> the IP on the chip (clock, power, JTAG) isn't reset and nothing on the bo=
ard
> (SD, ethernet, PCIe, etc) is reset.  This frequently results in flakiness=
 when
> debugging drivers, but the cores and memory system should all be OK.
>=20
> Is that issue 65 on github.com/opensbi?  If so it clearly says this isn't=
 a reset
> button issue.

The issue#65 on githuh.com/opensbi is not a clearly defined and it went in
various directions. We tried various things suggested by Andreas and we were
only able to replicate issue with reset-button press. This fixed now and
reset-button press works perfectly fine with OpenSBI.

Apart from reset-button thingy, we tried all other things reported by Andre=
as
but we were not able to reproduce issue at our end.

Regards,
Anup