From mboxrd@z Thu Jan  1 00:00:00 1970
From: Anup Patel <Anup.Patel@wdc.com>
Date: Mon, 11 Feb 2019 04:32:01 +0000
Subject: [U-Boot] [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock
	driver
In-Reply-To: <93bf2da4aedb059f1024576294947fb48286c957.camel@aisec.fraunhofer.de>
References: <20190209063052.29092-1-anup.patel@wdc.com>
 <20190209063052.29092-10-anup.patel@wdc.com>
 <93bf2da4aedb059f1024576294947fb48286c957.camel@aisec.fraunhofer.de>
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> -----Original Message-----
> From: Auer, Lukas [mailto:lukas.auer at aisec.fraunhofer.de]
> Sent: Monday, February 11, 2019 12:10 AM
> To: sjg at chromium.org; michal.simek at xilinx.com; bmeng.cn at gmail.com;
> joe.hershberger at ni.com; rick at andestech.com;
> yamada.masahiro at socionext.com; monstr at monstr.eu; Anup Patel
> <Anup.Patel@wdc.com>
> Cc: paul.walmsley at sifive.com; palmer at sifive.com; u-boot at lists.denx.de;
> agraf at suse.de; Atish Patra <Atish.Patra@wdc.com>
> Subject: Re: [PATCH v6 09/16] clk: Add SiFive FU540 PRCI clock driver
> 
> On Sat, 2019-02-09 at 06:32 +0000, Anup Patel wrote:
> > Add driver code for the SiFive FU540 PRCI IP block.  This IP block
> > handles reset and clock control for the SiFive FU540 device and
> > implements SoC-level clock tree controls and dividers.
> >
> > Based on code written by Wesley Terpstra <wesley@sifive.com> found in
> > commit 999529edf517ed75b56659d456d221b2ee56bb60 of:
> > https://github.com/riscv/riscv-linux
> >
> > Boot and PLL rate change were tested on a SiFive HiFive Unleashed
> > board.
> >
> > Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
> > Signed-off-by: Atish Patra <atish.patra@wdc.com>
> > Signed-off-by: Anup Patel <anup.patel@wdc.com>
> > Reviewed-by: Alexander Graf <agraf@suse.de>
> > ---
> >  drivers/clk/Kconfig                           |   1 +
> >  drivers/clk/Makefile                          |   1 +
> >  drivers/clk/sifive/Kconfig                    |  19 +
> >  drivers/clk/sifive/Makefile                   |   5 +
> >  .../clk/sifive/analogbits-wrpll-cln28hpc.h    | 101 +++
> >  drivers/clk/sifive/fu540-prci.c               | 604
> > ++++++++++++++++++
> >  drivers/clk/sifive/wrpll-cln28hpc.c           | 390 +++++++++++
> >  include/dt-bindings/clk/sifive-fu540-prci.h   |  29 +
> >  8 files changed, 1150 insertions(+)
> >  create mode 100644 drivers/clk/sifive/Kconfig  create mode 100644
> > drivers/clk/sifive/Makefile  create mode 100644
> > drivers/clk/sifive/analogbits-wrpll-cln28hpc.h
> >  create mode 100644 drivers/clk/sifive/fu540-prci.c  create mode
> > 100644 drivers/clk/sifive/wrpll-cln28hpc.c
> >  create mode 100644 include/dt-bindings/clk/sifive-fu540-prci.h
> >
> 
> This patch currently does not apply cleanly on U-Boot master.

The patches are based upon latest RISC-V U-Boot tree
(git://git.denx.de/u-boot-riscv.git) at commit id 91882c472d8c0aef4db699d3f2de55bf43d4ae4b

Do you want me to base this upon U-Boot master ??

Regards,
Anup