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Mon, 15 Mar 2021 06:15:42 +0000 From: Swapnil Kashinath Jakhade To: Kishon Vijay Abraham I , Vinod Koul , Rob Herring , Philipp Zabel CC: "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Lokesh Vutla Subject: RE: [PATCH v6 12/13] phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Thread-Topic: [PATCH v6 12/13] phy: cadence: phy-cadence-sierra: Model PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) Thread-Index: AQHXFcSSbJODXRBadEi41gRIvEsxK6qAJZkQ Date: Mon, 15 Mar 2021 06:15:42 +0000 Message-ID: References: <20210310154558.32078-1-kishon@ti.com> <20210310154558.32078-13-kishon@ti.com> In-Reply-To: <20210310154558.32078-13-kishon@ti.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-dg-ref: PG1ldGE+PGF0IG5tPSJib2R5LnR4dCIgcD0iYzpcdXNlcnNcc2pha2hhZGVcYXBwZGF0YVxyb2FtaW5nXDA5ZDg0OWI2LTMyZDMtNGE0MC04NWVlLTZiODRiYTI5ZTM1Ylxtc2dzXG1zZy1kZDE2MTRjNy04NTU1LTExZWItODU0Ny1jOGY3NTA0NDIyZDhcYW1lLXRlc3RcZGQxNjE0YzgtODU1NS0xMWViLTg1NDctYzhmNzUwNDQyMmQ4Ym9keS50eHQiIHN6PSIxNDI5MCIgdD0iMTMyNjAyNjI1NDAzMjI3MzUwIiBoPSJobjBwRmU2R1BqbUpHT09Vc2VxTHRNKzNXWTA9IiBpZD0iIiBibD0iMCIgYm89IjEiLz48L21ldGE+ x-dg-rorf: true authentication-results: ti.com; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR07MB6160.namprd07.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 52a52dd6-c7a5-4c8f-62c6-08d8e779c358 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Mar 2021 06:15:42.5714 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: DXrqdulq90aEpc9vTXJ1/RKJThkvRCLqMj0WMzeQtTH85FJMP76xLn67Zdl04VWytkbHzyEmUZyrWnnAXnNkQ4YXtlD1BKOVwCn8LAuoNwo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR07MB6416 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.369,18.0.761 definitions=2021-03-15_01:2021-03-15,2021-03-15 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 adultscore=0 priorityscore=1501 bulkscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 spamscore=0 suspectscore=0 impostorscore=0 mlxscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2009150000 definitions=main-2103150043 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Kishon Vijay Abraham I > Sent: Wednesday, March 10, 2021 9:16 PM > To: Kishon Vijay Abraham I ; Vinod Koul > ; Rob Herring ; Philipp Zabel > ; Swapnil Kashinath Jakhade > > Cc: linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Lokesh Vutl= a > > Subject: [PATCH v6 12/13] phy: cadence: phy-cadence-sierra: Model > PLL_CMNLC and PLL_CMNLC1 as clocks (mux clocks) > > EXTERNAL MAIL > > > Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has > two inputs, plllc_refclk (input from pll0_refclk) and refrcv (input from > pll1_refclk). Model PLL_CMNLC and PLL_CMNLC1 as clocks so that it's > possible to select one of these two inputs from device tree. > > Signed-off-by: Kishon Vijay Abraham I > --- > drivers/phy/cadence/Kconfig | 1 + > drivers/phy/cadence/phy-cadence-sierra.c | 267 ++++++++++++++++++++++- > 2 files changed, 265 insertions(+), 3 deletions(-) > Reviewed-by: Swapnil Jakhade Thanks & regards, Swapnil > diff --git a/drivers/phy/cadence/Kconfig b/drivers/phy/cadence/Kconfig > index 27e9d6c377e5..a62910ff5591 100644 > --- a/drivers/phy/cadence/Kconfig > +++ b/drivers/phy/cadence/Kconfig > @@ -25,6 +25,7 @@ config PHY_CADENCE_DPHY > config PHY_CADENCE_SIERRA > tristate "Cadence Sierra PHY Driver" > depends on OF && HAS_IOMEM && RESET_CONTROLLER > + depends on COMMON_CLK > select GENERIC_PHY > help > Enable this to support the Cadence Sierra PHY driver > diff --git a/drivers/phy/cadence/phy-cadence-sierra.c > b/drivers/phy/cadence/phy-cadence-sierra.c > index ac32b7b0289f..039ca10db59d 100644 > --- a/drivers/phy/cadence/phy-cadence-sierra.c > +++ b/drivers/phy/cadence/phy-cadence-sierra.c > @@ -7,6 +7,7 @@ > * > */ > #include > +#include > #include > #include > #include > @@ -20,10 +21,12 @@ > #include > #include > #include > +#include > > /* PHY register offsets */ > #define SIERRA_COMMON_CDB_OFFSET 0x0 > #define SIERRA_MACRO_ID_REG 0x0 > +#define SIERRA_CMN_PLLLC_GEN_PREG 0x42 > #define SIERRA_CMN_PLLLC_MODE_PREG 0x48 > #define SIERRA_CMN_PLLLC_LF_COEFF_MODE1_PREG 0x49 > #define SIERRA_CMN_PLLLC_LF_COEFF_MODE0_PREG 0x4A > @@ -31,6 +34,9 @@ > #define SIERRA_CMN_PLLLC_BWCAL_MODE1_PREG 0x4F > #define SIERRA_CMN_PLLLC_BWCAL_MODE0_PREG 0x50 > #define SIERRA_CMN_PLLLC_SS_TIME_STEPSIZE_MODE_PREG 0x62 > +#define SIERRA_CMN_REFRCV_PREG 0x98 > +#define SIERRA_CMN_REFRCV1_PREG 0xB8 > +#define SIERRA_CMN_PLLLC1_GEN_PREG 0xC2 > > #define SIERRA_LANE_CDB_OFFSET(ln, block_offset, reg_offset) \ > ((0x4000 << (block_offset)) + \ > @@ -144,13 +150,19 @@ > #define SIERRA_MAX_LANES 16 > #define PLL_LOCK_TIME 100000 > > -#define CDNS_SIERRA_INPUT_CLOCKS 3 > +#define CDNS_SIERRA_OUTPUT_CLOCKS 2 > +#define CDNS_SIERRA_INPUT_CLOCKS 5 > enum cdns_sierra_clock_input { > PHY_CLK, > CMN_REFCLK_DIG_DIV, > CMN_REFCLK1_DIG_DIV, > + PLL0_REFCLK, > + PLL1_REFCLK, > }; > > +#define SIERRA_NUM_CMN_PLLC 2 > +#define SIERRA_NUM_CMN_PLLC_PARENTS 2 > + > static const struct reg_field macro_id_type =3D > REG_FIELD(SIERRA_MACRO_ID_REG, 0, 15); > static const struct reg_field phy_pll_cfg_1 =3D > @@ -158,6 +170,53 @@ static const struct reg_field phy_pll_cfg_1 =3D > static const struct reg_field pllctrl_lock =3D > REG_FIELD(SIERRA_PLLCTRL_STATUS_PREG, 0, > 0); > > +static const char * const clk_names[] =3D { > + [CDNS_SIERRA_PLL_CMNLC] =3D "pll_cmnlc", > + [CDNS_SIERRA_PLL_CMNLC1] =3D "pll_cmnlc1", > +}; > + > +enum cdns_sierra_cmn_plllc { > + CMN_PLLLC, > + CMN_PLLLC1, > +}; > + > +struct cdns_sierra_pll_mux_reg_fields { > + struct reg_field pfdclk_sel_preg; > + struct reg_field plllc1en_field; > + struct reg_field termen_field; > +}; > + > +static const struct cdns_sierra_pll_mux_reg_fields > cmn_plllc_pfdclk1_sel_preg[] =3D { > + [CMN_PLLLC] =3D { > + .pfdclk_sel_preg =3D > REG_FIELD(SIERRA_CMN_PLLLC_GEN_PREG, 1, 1), > + .plllc1en_field =3D REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 8, > 8), > + .termen_field =3D REG_FIELD(SIERRA_CMN_REFRCV1_PREG, 0, > 0), > + }, > + [CMN_PLLLC1] =3D { > + .pfdclk_sel_preg =3D > REG_FIELD(SIERRA_CMN_PLLLC1_GEN_PREG, 1, 1), > + .plllc1en_field =3D REG_FIELD(SIERRA_CMN_REFRCV_PREG, 8, > 8), > + .termen_field =3D REG_FIELD(SIERRA_CMN_REFRCV_PREG, 0, 0), > + }, > +}; > + > +struct cdns_sierra_pll_mux { > + struct clk_hw hw; > + struct regmap_field *pfdclk_sel_preg; > + struct regmap_field *plllc1en_field; > + struct regmap_field *termen_field; > + struct clk_init_data clk_data; > +}; > + > +#define to_cdns_sierra_pll_mux(_hw) \ > + container_of(_hw, struct cdns_sierra_pll_mux, hw) > + > +static const int pll_mux_parent_index[][SIERRA_NUM_CMN_PLLC_PARENTS] > =3D { > + [CMN_PLLLC] =3D { PLL0_REFCLK, PLL1_REFCLK }, > + [CMN_PLLLC1] =3D { PLL1_REFCLK, PLL0_REFCLK }, > +}; > + > +static u32 cdns_sierra_pll_mux_table[] =3D { 0, 1 }; > + > struct cdns_sierra_inst { > struct phy *phy; > u32 phy_type; > @@ -204,10 +263,15 @@ struct cdns_sierra_phy { > struct regmap_field *macro_id_type; > struct regmap_field *phy_pll_cfg_1; > struct regmap_field *pllctrl_lock[SIERRA_MAX_LANES]; > + struct regmap_field > *cmn_refrcv_refclk_plllc1en_preg[SIERRA_NUM_CMN_PLLC]; > + struct regmap_field > *cmn_refrcv_refclk_termen_preg[SIERRA_NUM_CMN_PLLC]; > + struct regmap_field > *cmn_plllc_pfdclk1_sel_preg[SIERRA_NUM_CMN_PLLC]; > struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; > int nsubnodes; > u32 num_lanes; > bool autoconf; > + struct clk_onecell_data clk_data; > + struct clk *output_clks[CDNS_SIERRA_OUTPUT_CLOCKS]; > }; > > static int cdns_regmap_write(void *context, unsigned int reg, unsigned i= nt > val) > @@ -369,6 +433,153 @@ static const struct phy_ops ops =3D { > .owner =3D THIS_MODULE, > }; > > +static u8 cdns_sierra_pll_mux_get_parent(struct clk_hw *hw) > +{ > + struct cdns_sierra_pll_mux *mux =3D to_cdns_sierra_pll_mux(hw); > + struct regmap_field *field =3D mux->pfdclk_sel_preg; > + unsigned int val; > + > + regmap_field_read(field, &val); > + return clk_mux_val_to_index(hw, cdns_sierra_pll_mux_table, 0, val); > +} > + > +static int cdns_sierra_pll_mux_set_parent(struct clk_hw *hw, u8 index) > +{ > + struct cdns_sierra_pll_mux *mux =3D to_cdns_sierra_pll_mux(hw); > + struct regmap_field *plllc1en_field =3D mux->plllc1en_field; > + struct regmap_field *termen_field =3D mux->termen_field; > + struct regmap_field *field =3D mux->pfdclk_sel_preg; > + int val, ret; > + > + ret =3D regmap_field_write(plllc1en_field, 0); > + ret |=3D regmap_field_write(termen_field, 0); > + if (index =3D=3D 1) { > + ret |=3D regmap_field_write(plllc1en_field, 1); > + ret |=3D regmap_field_write(termen_field, 1); > + } > + > + val =3D cdns_sierra_pll_mux_table[index]; > + ret |=3D regmap_field_write(field, val); > + > + return ret; > +} > + > +static const struct clk_ops cdns_sierra_pll_mux_ops =3D { > + .set_parent =3D cdns_sierra_pll_mux_set_parent, > + .get_parent =3D cdns_sierra_pll_mux_get_parent, > +}; > + > +static int cdns_sierra_pll_mux_register(struct cdns_sierra_phy *sp, > + struct regmap_field > *pfdclk1_sel_field, > + struct regmap_field *plllc1en_field= , > + struct regmap_field *termen_field, > + int clk_index) > +{ > + struct cdns_sierra_pll_mux *mux; > + struct device *dev =3D sp->dev; > + struct clk_init_data *init; > + const char **parent_names; > + unsigned int num_parents; > + char clk_name[100]; > + struct clk *clk; > + int i; > + > + mux =3D devm_kzalloc(dev, sizeof(*mux), GFP_KERNEL); > + if (!mux) > + return -ENOMEM; > + > + num_parents =3D SIERRA_NUM_CMN_PLLC_PARENTS; > + parent_names =3D devm_kzalloc(dev, (sizeof(char *) * num_parents), > GFP_KERNEL); > + if (!parent_names) > + return -ENOMEM; > + > + for (i =3D 0; i < num_parents; i++) { > + clk =3D sp->input_clks[pll_mux_parent_index[clk_index][i]]; > + if (IS_ERR_OR_NULL(clk)) { > + dev_err(dev, "No parent clock for derived_refclk\n"= ); > + return PTR_ERR(clk); > + } > + parent_names[i] =3D __clk_get_name(clk); > + } > + > + snprintf(clk_name, sizeof(clk_name), "%s_%s", dev_name(dev), > clk_names[clk_index]); > + > + init =3D &mux->clk_data; > + > + init->ops =3D &cdns_sierra_pll_mux_ops; > + init->flags =3D CLK_SET_RATE_NO_REPARENT; > + init->parent_names =3D parent_names; > + init->num_parents =3D num_parents; > + init->name =3D clk_name; > + > + mux->pfdclk_sel_preg =3D pfdclk1_sel_field; > + mux->plllc1en_field =3D plllc1en_field; > + mux->termen_field =3D termen_field; > + mux->hw.init =3D init; > + > + clk =3D devm_clk_register(dev, &mux->hw); > + if (IS_ERR(clk)) > + return PTR_ERR(clk); > + > + sp->output_clks[clk_index] =3D clk; > + > + return 0; > +} > + > +static int cdns_sierra_phy_register_pll_mux(struct cdns_sierra_phy *sp) > +{ > + struct regmap_field *pfdclk1_sel_field; > + struct regmap_field *plllc1en_field; > + struct regmap_field *termen_field; > + struct device *dev =3D sp->dev; > + int ret =3D 0, i, clk_index; > + > + clk_index =3D CDNS_SIERRA_PLL_CMNLC; > + for (i =3D 0; i < SIERRA_NUM_CMN_PLLC; i++, clk_index++) { > + pfdclk1_sel_field =3D sp->cmn_plllc_pfdclk1_sel_preg[i]; > + plllc1en_field =3D sp->cmn_refrcv_refclk_plllc1en_preg[i]; > + termen_field =3D sp->cmn_refrcv_refclk_termen_preg[i]; > + > + ret =3D cdns_sierra_pll_mux_register(sp, pfdclk1_sel_field, > plllc1en_field, > + termen_field, clk_index)= ; > + if (ret) { > + dev_err(dev, "Fail to register cmn plllc mux\n"); > + return ret; > + } > + } > + > + return 0; > +} > + > +static void cdns_sierra_clk_unregister(struct cdns_sierra_phy *sp) > +{ > + struct device *dev =3D sp->dev; > + struct device_node *node =3D dev->of_node; > + > + of_clk_del_provider(node); > +} > + > +static int cdns_sierra_clk_register(struct cdns_sierra_phy *sp) > +{ > + struct device *dev =3D sp->dev; > + struct device_node *node =3D dev->of_node; > + int ret; > + > + ret =3D cdns_sierra_phy_register_pll_mux(sp); > + if (ret) { > + dev_err(dev, "Failed to pll mux clocks\n"); > + return ret; > + } > + > + sp->clk_data.clks =3D sp->output_clks; > + sp->clk_data.clk_num =3D CDNS_SIERRA_OUTPUT_CLOCKS; > + ret =3D of_clk_add_provider(node, of_clk_src_onecell_get, &sp- > >clk_data); > + if (ret) > + dev_err(dev, "Failed to add clock provider: %s\n", node- > >name); > + > + return ret; > +} > + > static int cdns_sierra_get_optional(struct cdns_sierra_inst *inst, > struct device_node *child) > { > @@ -407,6 +618,7 @@ static int cdns_regfield_init(struct cdns_sierra_phy > *sp) > { > struct device *dev =3D sp->dev; > struct regmap_field *field; > + struct reg_field reg_field; > struct regmap *regmap; > int i; > > @@ -418,6 +630,32 @@ static int cdns_regfield_init(struct cdns_sierra_phy > *sp) > } > sp->macro_id_type =3D field; > > + for (i =3D 0; i < SIERRA_NUM_CMN_PLLC; i++) { > + reg_field =3D cmn_plllc_pfdclk1_sel_preg[i].pfdclk_sel_preg= ; > + field =3D devm_regmap_field_alloc(dev, regmap, reg_field); > + if (IS_ERR(field)) { > + dev_err(dev, "PLLLC%d_PFDCLK1_SEL failed\n", i); > + return PTR_ERR(field); > + } > + sp->cmn_plllc_pfdclk1_sel_preg[i] =3D field; > + > + reg_field =3D cmn_plllc_pfdclk1_sel_preg[i].plllc1en_field; > + field =3D devm_regmap_field_alloc(dev, regmap, reg_field); > + if (IS_ERR(field)) { > + dev_err(dev, "REFRCV%d_REFCLK_PLLLC1EN failed\n", > i); > + return PTR_ERR(field); > + } > + sp->cmn_refrcv_refclk_plllc1en_preg[i] =3D field; > + > + reg_field =3D cmn_plllc_pfdclk1_sel_preg[i].termen_field; > + field =3D devm_regmap_field_alloc(dev, regmap, reg_field); > + if (IS_ERR(field)) { > + dev_err(dev, "REFRCV%d_REFCLK_TERMEN failed\n", > i); > + return PTR_ERR(field); > + } > + sp->cmn_refrcv_refclk_termen_preg[i] =3D field; > + } > + > regmap =3D sp->regmap_phy_config_ctrl; > field =3D devm_regmap_field_alloc(dev, regmap, phy_pll_cfg_1); > if (IS_ERR(field)) { > @@ -511,6 +749,22 @@ static int cdns_sierra_phy_get_clocks(struct > cdns_sierra_phy *sp, > } > sp->input_clks[CMN_REFCLK1_DIG_DIV] =3D clk; > > + clk =3D devm_clk_get_optional(dev, "pll0_refclk"); > + if (IS_ERR(clk)) { > + dev_err(dev, "pll0_refclk clock not found\n"); > + ret =3D PTR_ERR(clk); > + return ret; > + } > + sp->input_clks[PLL0_REFCLK] =3D clk; > + > + clk =3D devm_clk_get_optional(dev, "pll1_refclk"); > + if (IS_ERR(clk)) { > + dev_err(dev, "pll1_refclk clock not found\n"); > + ret =3D PTR_ERR(clk); > + return ret; > + } > + sp->input_clks[PLL1_REFCLK] =3D clk; > + > return 0; > } > > @@ -586,13 +840,17 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) > if (ret) > return ret; > > - ret =3D cdns_sierra_phy_get_resets(sp, dev); > + ret =3D cdns_sierra_clk_register(sp); > if (ret) > return ret; > > + ret =3D cdns_sierra_phy_get_resets(sp, dev); > + if (ret) > + goto unregister_clk; > + > ret =3D clk_prepare_enable(sp->input_clks[PHY_CLK]); > if (ret) > - return ret; > + goto unregister_clk; > > /* Enable APB */ > reset_control_deassert(sp->apb_rst); > @@ -669,6 +927,8 @@ static int cdns_sierra_phy_probe(struct > platform_device *pdev) > clk_disable: > clk_disable_unprepare(sp->input_clks[PHY_CLK]); > reset_control_assert(sp->apb_rst); > +unregister_clk: > + cdns_sierra_clk_unregister(sp); > return ret; > } > > @@ -691,6 +951,7 @@ static int cdns_sierra_phy_remove(struct > platform_device *pdev) > } > > clk_disable_unprepare(phy->input_clks[PHY_CLK]); > + cdns_sierra_clk_unregister(phy); > > return 0; > } > -- > 2.17.1