From mboxrd@z Thu Jan 1 00:00:00 1970 From: Tan, Ley Foon Date: Tue, 24 Dec 2019 02:00:59 +0000 Subject: [PATCH] usb: dwc2: Add small delay after reset In-Reply-To: <097cb601-6ff5-0a95-0af0-58998fdaa867@denx.de> References: <1577088452-3684-1-git-send-email-ley.foon.tan@intel.com> <097cb601-6ff5-0a95-0af0-58998fdaa867@denx.de> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de > -----Original Message----- > From: Marek Vasut > Sent: Monday, December 23, 2019 7:59 PM > To: Tan, Ley Foon ; u-boot at lists.denx.de > Cc: Ley Foon Tan ; See, Chin Liang > ; Chee, Tien Fong > Subject: Re: [PATCH] usb: dwc2: Add small delay after reset > > On 12/23/19 9:07 AM, Ley Foon Tan wrote: > > In Cyclone 5 SoC platform, the first USB probing is failed but second > > probing is success. DWC2 driver read gsnpsid register right after > > de-assert reset, but controller is not ready yet and it returns gsnpsid 0. > > Adding small delay after de-assert reset solve the issue. > > > > Retry with this fix more than 10 times without issue. > > > > => usb reset > > resetting USB... > > Bus usb at ffb40000: usb probe > > SNPSID invalid (not DWC2 OTG device): 00000000 Port not available. > > => usb reset > > resetting USB... > > Bus usb at ffb40000: usb probe > > scanning bus usb at ffb40000 for devices... 2 USB Device(s) found > > scanning usb for storage devices... 1 Storage Device(s) found > > Can't you poll for the readiness of the IP somehow instead of using arbitrary > delay ? One way we can do is calling to reset_status() to read back reset status. Will change that. Regards Ley Foon