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boundary="===============0176392829==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============0176392829== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB3296FCACEC21D2A6B3F71FE4A22E0MN2PR12MB3296namp_" --_000_MN2PR12MB3296FCACEC21D2A6B3F71FE4A22E0MN2PR12MB3296namp_ Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable [AMD Official Use Only - Internal Distribution Only] add @Quan, Evan to support arcturus asic. comment inline. ________________________________ From: Zhang, Jack (Jian) Sent: Monday, December 23, 2019 4:42 PM To: Feng, Kenneth ; Wang, Kevin(Yang) ; Tao, Yintian ; amd-gfx@lists.freedesktop.org <= amd-gfx@lists.freedesktop.org>; Deng, Emily Cc: Zhang, Jack (Jian) Subject: RE: [PATCH] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF -----Original Message----- From: Jack Zhang Sent: Monday, December 23, 2019 4:40 PM To: amd-gfx@lists.freedesktop.org Cc: Zhang, Jack (Jian) Subject: [PATCH] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF Before, initialization of smu ip block would be skipped for sriov ASICs. Bu= t if there's only one VF being used, guest driver should be able to dump so= me HW info such as clks, temperature,etc. To solve this, now after onevf mode is enabled, host driver will notify gue= st. If it's onevf mode, guest will do smu hw_init and skip some steps in no= rmal smu hw_init flow because host driver has already done it for smu. With this fix, guest app can talk with smu and dump hw information from smu= . Signed-off-by: Jack Zhang --- drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 3 +- drivers/gpu/drm/amd/amdgpu/soc15.c | 3 +- drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 49 ++++++++++++++++++--------= ---- 3 files changed, 33 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_psp.c index 8469834..08130a6 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c @@ -1448,7 +1448,8 @@ static int psp_np_fw_load(struct psp_context *psp) || ucode->ucode_id =3D=3D AMDGPU_UCODE_ID_RLC_G || ucode->ucode_id =3D=3D AMDGPU_UCODE_ID_RLC_RESTORE_= LIST_CNTL || ucode->ucode_id =3D=3D AMDGPU_UCODE_ID_RLC_RESTORE_= LIST_GPM_MEM - || ucode->ucode_id =3D=3D AMDGPU_UCODE_ID_RLC_RESTORE_L= IST_SRM_MEM)) + || ucode->ucode_id =3D=3D AMDGPU_UCODE_ID_RLC_RESTORE_L= IST_SRM_MEM + || ucode->ucode_id =3D=3D AMDGPU_UCODE_ID_SMC)) /*skip ucode loading in SRIOV VF */ continue; diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgp= u/soc15.c index b53d401..a271496 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -827,8 +827,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev) amdgpu_device_ip_block_add(adev, &dce_virtual_ip_b= lock); amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_block); amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_block); - if (!amdgpu_sriov_vf(adev)) - amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_bloc= k); + amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block); if (amdgpu_sriov_vf(adev)) { if (likely(adev->firmware.load_type =3D=3D AMDGPU_= FW_LOAD_PSP)) diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/dri= vers/gpu/drm/amd/powerplay/amdgpu_smu.c index 936c682..c07fb26 100644 --- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c +++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c @@ -531,10 +531,14 @@ bool is_support_sw_smu(struct amdgpu_device *adev) if (adev->asic_type =3D=3D CHIP_VEGA20) return (amdgpu_dpm =3D=3D 2) ? true : false; else if (adev->asic_type >=3D CHIP_ARCTURUS) { - if (amdgpu_sriov_vf(adev)) - return false; - else + if (amdgpu_sriov_vf(adev)) { + if(amdgpu_sriov_is_pp_one_vf(adev)) + return true; + else + return false; + } else { return true; + } } else return false; } @@ -1062,20 +1066,19 @@ static int smu_smc_table_hw_init(struct smu_context= *smu, } /* smu_dump_pptable(smu); */ + if(amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)){ + /* + * Copy pptable bo in the vram to smc with SMU MSGs such as + * SetDriverDramAddr and TransferTableDram2Smu. + */ [kevin]: this comment is not neccessary in smu module. and could you describe the function of pp_one_vf and sriov_vf ? it is useful to help us understand your patch. thanks. + ret =3D smu_write_pptable(smu); + if (ret) + return ret; - /* - * Copy pptable bo in the vram to smc with SMU MSGs such as - * SetDriverDramAddr and TransferTableDram2Smu. - */ - ret =3D smu_write_pptable(smu); - if (ret) - return ret; - - /* issue Run*Btc msg */ - ret =3D smu_run_btc(smu); - if (ret) - return ret; - + /* issue Run*Btc msg */ + ret =3D smu_run_btc(smu); + if (ret) + return ret; ret =3D smu_feature_set_allowed_mask(smu); if (ret) return ret; @@ -1083,7 +1086,7 @@ static int smu_smc_table_hw_init(struct smu_context *= smu, ret =3D smu_system_features_control(smu, true); if (ret) return ret; - + } if (adev->asic_type !=3D CHIP_ARCTURUS) { ret =3D smu_notify_display_change(smu); if (ret) @@ -1136,8 +1139,9 @@ static int smu_smc_table_hw_init(struct smu_context *= smu, /* * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for = tools. */ - ret =3D smu_set_tool_table_location(smu); - + if(amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)){ + ret =3D smu_set_tool_table_location(smu); + } if (!smu_is_dpm_running(smu)) pr_info("dpm has been disabled\n"); @@ -1249,6 +1253,13 @@ static int smu_hw_init(void *handle) smu_set_gfx_cgpg(&adev->smu, true); } + if (amdgpu_sriov_vf(adev)) { + if(amdgpu_sriov_is_pp_one_vf(adev)) + smu->pm_enabled =3D true; + else + smu->pm_enabled =3D false; + } + [kevin]: the variable of "smu->pm_enabeld" is initialize in smu_eary_init(), it is o= nly depend on module param amdgpu_dpm. after initialized, this variable should not be changed arbitrarily. so i hope you can refine the above code logic. if (!smu->pm_enabled) return 0; -- 2.7.4 --_000_MN2PR12MB3296FCACEC21D2A6B3F71FE4A22E0MN2PR12MB3296namp_ Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable

[AMD Official Use Only - Internal Distribution Only]


add @Quan, Evan to support arcturus asic.
comment inline.
From: Zhang, Jack (Jian) &l= t;Jack.Zhang1@amd.com>
Sent: Monday, December 23, 2019 4:42 PM
To: Feng, Kenneth <Kenneth.Feng@amd.com>; Wang, Kevin(Yang) &l= t;Kevin1.Wang@amd.com>; Tao, Yintian <Yintian.Tao@amd.com>; amd-gf= x@lists.freedesktop.org <amd-gfx@lists.freedesktop.org>; Deng, Emily = <Emily.Deng@amd.com>
Cc: Zhang, Jack (Jian) <Jack.Zhang1@amd.com>
Subject: RE: [PATCH] amd/amdgpu/sriov enable onevf mode for ARCTURUS= VF
 


-----Original Message-----
From: Jack Zhang <Jack.Zhang1@amd.com>
Sent: Monday, December 23, 2019 4:40 PM
To: amd-gfx@lists.freedesktop.org
Cc: Zhang, Jack (Jian) <Jack.Zhang1@amd.com>
Subject: [PATCH] amd/amdgpu/sriov enable onevf mode for ARCTURUS VF

Before, initialization of smu ip block would be skipped for sriov ASICs. Bu= t if there's only one VF being used, guest driver should be able to dump so= me HW info such as clks, temperature,etc.

To solve this, now after onevf mode is enabled, host driver will notify gue= st. If it's onevf mode, guest will do smu hw_init and skip some steps in no= rmal smu hw_init flow because host driver has already done it for smu.

With this fix, guest app can talk with smu and dump hw information from smu= .

Signed-off-by: Jack Zhang <Jack.Zhang1@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c    |  3 &= #43;-
 drivers/gpu/drm/amd/amdgpu/soc15.c      = ;   |  3 +-
 drivers/gpu/drm/amd/powerplay/amdgpu_smu.c | 49 ++++&= #43;+++++++++++++------= ------
 3 files changed, 33 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/= amdgpu/amdgpu_psp.c
index 8469834..08130a6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1448,7 +1448,8 @@ static int psp_np_fw_load(struct psp_context *psp= )
            &nb= sp;        || ucode->ucode_id =3D=3D = AMDGPU_UCODE_ID_RLC_G
            &nb= sp;        || ucode->ucode_id =3D=3D = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL
            &nb= sp;        || ucode->ucode_id =3D=3D = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM
-            &n= bsp;      || ucode->ucode_id =3D=3D AMDGPU_UCOD= E_ID_RLC_RESTORE_LIST_SRM_MEM))
+           &nbs= p;       || ucode->ucode_id =3D=3D AMDGPU_= UCODE_ID_RLC_RESTORE_LIST_SRM_MEM
+           &nbs= p;       || ucode->ucode_id =3D=3D AMDGPU_= UCODE_ID_SMC))
            &nb= sp;            /*ski= p ucode loading in SRIOV VF */
            &nb= sp;            conti= nue;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgp= u/soc15.c
index b53d401..a271496 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -827,8 +827,7 @@ int soc15_set_ip_blocks(struct amdgpu_device *adev)=
            &nb= sp;            amdgp= u_device_ip_block_add(adev, &dce_virtual_ip_block);
            &nb= sp;    amdgpu_device_ip_block_add(adev, &gfx_v9_0_ip_blo= ck);
            &nb= sp;    amdgpu_device_ip_block_add(adev, &sdma_v4_0_ip_bl= ock);
-            &n= bsp;  if (!amdgpu_sriov_vf(adev))
-            &n= bsp;          amdgpu_device_ip= _block_add(adev, &smu_v11_0_ip_block);
+           &nbs= p;   amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);  
            &nb= sp;    if (amdgpu_sriov_vf(adev)) {
            &nb= sp;            if (l= ikely(adev->firmware.load_type =3D=3D AMDGPU_FW_LOAD_PSP)) diff --git a/= drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/= amdgpu_smu.c
index 936c682..c07fb26 100644
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -531,10 +531,14 @@ bool is_support_sw_smu(struct amdgpu_device *adev= )
         if (adev->asic_type =3D= =3D CHIP_VEGA20)
            &nb= sp;    return (amdgpu_dpm =3D=3D 2) ? true : false;
         else if (adev->asic_typ= e >=3D CHIP_ARCTURUS) {
-            &n= bsp;  if (amdgpu_sriov_vf(adev))
-            &n= bsp;          return false; -            &n= bsp;  else
+           &nbs= p;   if (amdgpu_sriov_vf(adev)) {
+           &nbs= p;           if(amdgpu_sr= iov_is_pp_one_vf(adev))
+           &nbs= p;            &= nbsp;      return true;
+           &nbs= p;           else
+           &nbs= p;            &= nbsp;      return false;
+           &nbs= p;   } else {
            &nb= sp;            retur= n true;
+           &nbs= p;   }
         } else
            &nb= sp;    return false;
 }
@@ -1062,20 +1066,19 @@ static int smu_smc_table_hw_init(struct smu_con= text *smu,
         }
 
         /* smu_dump_pptable(smu); = */
+       if(amdgpu_sriov_vf(adev) &&am= p; !amdgpu_sriov_is_pp_one_vf(adev)){
+           &nbs= p;   /*
+           &nbs= p;    * Copy pptable bo in the vram to smc with SMU MSGs suc= h as
+           &nbs= p;    * SetDriverDramAddr and TransferTableDram2Smu.
+           &nbs= p;    */
[kevin]: this comment is not neccessary in smu mod= ule.
and could you describe the function of pp_on= e_vf and sriov_vf ?
it is useful to help us understand your patc= h. 
thanks.

+       &nb= sp;       ret =3D smu_write_pptable(smu);
+           &nbs= p;   if (ret)
+           &nbs= p;           return ret;<= br>  
-       /*
-        * Copy pptable bo in the vram t= o smc with SMU MSGs such as
-        * SetDriverDramAddr and Transfe= rTableDram2Smu.
-        */
-       ret =3D smu_write_pptable(smu);
-       if (ret)
-            &n= bsp;  return ret;
-
-       /* issue Run*Btc msg */
-       ret =3D smu_run_btc(smu);
-       if (ret)
-            &n= bsp;  return ret;
-
+           &nbs= p;   /* issue Run*Btc msg */
+           &nbs= p;   ret =3D smu_run_btc(smu);
+           &nbs= p;   if (ret)
+           &nbs= p;           return ret;<= br>          ret =3D smu_feature_set_al= lowed_mask(smu);
         if (ret)
            &nb= sp;    return ret;
@@ -1083,7 +1086,7 @@ static int smu_smc_table_hw_init(struct smu_conte= xt *smu,
         ret =3D smu_system_feature= s_control(smu, true);
         if (ret)
            &nb= sp;    return ret;
-
+       }
         if (adev->asic_type != =3D CHIP_ARCTURUS) {
            &nb= sp;    ret =3D smu_notify_display_change(smu);
            &nb= sp;    if (ret)
@@ -1136,8 +1139,9 @@ static int smu_smc_table_hw_init(struct smu_conte= xt *smu,
         /*
          * Set PMSTATUSLOG ta= ble bo address with SetToolsDramAddr MSG for tools.
          */
-       ret =3D smu_set_tool_table_location(s= mu);
-
+       if(amdgpu_sriov_vf(adev) &&am= p; !amdgpu_sriov_is_pp_one_vf(adev)){
+           &nbs= p;   ret =3D smu_set_tool_table_location(smu);
+       }
         if (!smu_is_dpm_running(sm= u))
            &nb= sp;    pr_info("dpm has been disabled\n");
 
@@ -1249,6 +1253,13 @@ static int smu_hw_init(void *handle)
            &nb= sp;    smu_set_gfx_cgpg(&adev->smu, true);
         }
 
+       if (amdgpu_sriov_vf(adev)) {
+           &nbs= p;   if(amdgpu_sriov_is_pp_one_vf(adev))
+           &nbs= p;           smu->pm_e= nabled =3D true;
+           &nbs= p;   else
+           &nbs= p;           smu->pm_e= nabled =3D false;
+       }
+

[kevin]:
the variable of "smu->pm_enabeld" is = initialize in smu_eary_init(), it is only depend on module param amdgpu_dpm= .
after initialized, this variable should not be changed arbitrarily.
so i hope you can refine the above code logic.<= /div>

         i= f (!smu->pm_enabled)
            &nb= sp;    return 0;
 
--
2.7.4

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