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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MN2PR12MB3949.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f18c2143-78d2-4e1d-c18c-08da174e2817 X-MS-Exchange-CrossTenant-originalarrivaltime: 05 Apr 2022 21:49:27.2005 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NSxvgBPVJ9CoWzd7nvCo+p/07nk8H5E8AbiNIOSUZ/ozlAc8b1ygnI2tS4Y1j01IEbrDJrwd7EjynDh6fjCOiw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB3777 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org [Public] > -----Original Message----- > From: Borislav Petkov > Sent: Tuesday, April 5, 2022 4:39 PM > To: Carroll, Lewis > Cc: linux-kernel@vger.kernel.org; peterz@infradead.org; > dave.hansen@linux.intel.com; Karny, Wyes ; Limonciell= o, > Mario ; Shenoy, Gautham Ranjal > ; Narayan, Ananth ; Rao, > Bharata Bhasker ; len.brown@intel.com; x86@kernel.org; > tglx@linutronix.de; mingo@redhat.com; hpa@zytor.com; > chang.seok.bae@intel.com; keescook@chromium.org; metze@samba.org; > zhengqi.arch@bytedance.com; mark.rutland@arm.com > Subject: Re: [PATCH] x86: Prefer MWAIT over HALT on AMD processors >=20 > [CAUTION: External Email] >=20 > On Tue, Apr 05, 2022 at 08:26:53PM +0000, Carroll, Lewis wrote: > > This happens when: > > * User disables global C-states in BIOS > > * User disables cpuidle (e.g. idle=3Doff or processor.max_cstate=3D0) > > * Kernel does not have CONFIG_ACPI_PROCESSOR_IDLE >=20 > All three or any one of those? Just when I thought I was being thorough. Any of the above will block the cpuidle driver from loading. As will absence of _CST ACPI methods (add that as a fourth cause). Brings back memories of code comments about a certain idle driver being created to work around broken BIOSes... >=20 > > Genesis of this patch is customer performance observations. >=20 > Please add that explanation to the changelog - it is important when looki= ng > back, trying to figure out why this was done. We will have to see what we can sanitize. The original performance observat= ion (packet loss in a networking application) led to discovery of lots of cycle= s in the various go-to-sleep-via-halt and wake-from-halt-via-IPI functions. W= yes collected the raw data on the relative idle+wake-up latency and included th= at in the commit msg. Think of that delta as the root cause of the performance regression in this case. >=20 > > Yes. We felt the code more readable with the prefer_mwait_c1_over_halt = fn. > > Hygon CPU init indeed sets X86_FEATURE ZEN. > > AMD CPU init sets X86_FEATURE_ZEN for family >=3D 17h (not only 17h). >=20 > Yes, but this new logic you're adding, basically says, use MWAIT on all Z= en > uarch CPUs, right? Yes we are saying use MWAIT instead of HLT on all known (as of today) Zen uarch CPUs (AMD >=3D 17h and Hygon). >=20 > So why not write exactly that? >=20 > The simpler the logic and the clearer the code, the better. >=20 > > Cleanest solution might be a new CPU feature (e.g. > > X86_PREFER_MWAIT_IDLE) that gets set appropriately, but that would > > require touching more files. >=20 > Yes, I thought about it too. >=20 > Not really necessary if what I wrote above fits. >=20 > And while you're touching files, pls add that change too: >=20 > --- > diff --git a/arch/x86/include/asm/cpufeatures.h > b/arch/x86/include/asm/cpufeatures.h > index 73e643ae94b6..c1091f78f104 100644 > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -219,7 +219,7 @@ > #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch > Restricted Speculation */ > #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch > Prediction Barrier */ > #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indir= ect > Branch Predictors */ > -#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is A= MD > family 0x17 or above (Zen) */ > +#define X86_FEATURE_ZEN ( 7*32+28) /* "" Set on C= PUs > of the Zen uarch */ > #define X86_FEATURE_L1TF_PTEINV ( 7*32+29) /* "" L1TF > workaround PTE inversion */ > #define X86_FEATURE_IBRS_ENHANCED ( 7*32+30) /* Enhanced IBRS */ > #define X86_FEATURE_MSR_IA32_FEAT_CTL ( 7*32+31) /* "" MSR IA32_FEAT_CT= L > configured */ >=20 > so that dhansen and peterz are not confused anymore. :-) =20 Ack. >=20 > Thx. >=20 > -- > Regards/Gruss, > Boris.