From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Ma, Le" Subject: RE: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgmi/ras case Date: Wed, 27 Nov 2019 12:35:57 +0000 Message-ID: References: <1574846129-4826-1-git-send-email-le.ma@amd.com> <1574846129-4826-5-git-send-email-le.ma@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============1598236071==" Return-path: In-Reply-To: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "Zhang, Hawking" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" Cc: "Deucher, Alexander" , "Zhou1, Tao" , "Li, Dennis" , "Chen, Guchun" --===============1598236071== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB4285E37DF7D44270D5CAD0E5F6440MN2PR12MB4285namp_" --_000_MN2PR12MB4285E37DF7D44270D5CAD0E5F6440MN2PR12MB4285namp_ Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Agree with your thoughts that we drop amdgpu_ras_enable=3D2 condition. The = only concern in my side is that besides fatal_error, another result may hap= pen that atombios_init timeout on xgmi by baco (not sure psp mode1 reset ca= uses this as well). Assuming no amdgpu_ras_enable=3D2 check, if PMFW > 40.52, the use cases as= my understanding includes: 1. sGPU without RAS: * new: baco * old: baco 2. sGPU with RAS: * new: baco * old: psp mode1 chain reset and legacy fatal_error handling 1. XGMI with RAS: baco * new: baco * old: psp mode1 chain reset and legacy fatal_error handling 2. XGMI without RAS: baco * new: baco * old: psp mode1 chain reset That is to say, all uses cases go on baco road when PMFW > 40.52. Regards, Ma Le -----Original Message----- From: Zhang, Hawking Sent: Wednesday, November 27, 2019 7:28 PM To: Ma, Le ; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Chen, Guchun ; Zhou1, Tao ; Li,= Dennis ; Deucher, Alexander = ; Ma, Le Subject: RE: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgm= i/ras case [AMD Public Use] After thinking it a bit, I think we can just rely on PMFW version to decide= to go RAS recovery or legacy fatal_error handling for the platforms that s= upport RAS. Leveraging amdgpu_ras_enable as a temporary solution seems not = necessary? Even baco ras recovery not stable, it is the same result as lega= cy fatal_error handling that user has to reboot the node manually. So the new soc reset use cases are: XGMI (without RAS): use PSP mode1 based chain reset, RAS enabled (with PMFW= 40.52 and onwards): use BACO based RAS recovery, RAS enabled (with PMFW pr= ior to 40.52): use legacy fatal_error handling. Anything else? Regards, Hawking -----Original Message----- From: Le Ma > Sent: 2019=1B$BG/=1B(B11=1B$B7n=1B(B27=1B$BF|=1B(B 17:15 To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Zhang, Hawking >; C= hen, Guchun >; Zhou1, Tao <= Tao.Zhou1-5C7GfCeVMHo@public.gmane.org>; Li, Dennis >; Deucher, Alexander >; Ma, Le > Subject: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgmi/ra= s case Avoid to change default reset behavior for production card by checking amdg= pu_ras_enable equal to 2. And only new enough smu ucode can support baco fo= r xgmi/ras case. Change-Id: I07c3e6862be03e068745c73db8ea71f428ecba6b Signed-off-by: Le Ma > --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgp= u/soc15.c index 951327f..6202333 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -577,7 +577,9 @@ soc15_asic_reset_method(struct amdgpu_device *adev) struct amdgpu_hive_info *hive =3D amdgpu= _get_xgmi_hive(adev, 0); struct amdgpu_ras *ras =3D amdgpu_ras_ge= t_context(adev); - if (hive || (ras && ras->supported)) + if ((hive || (ras && ras->supported)) && + (amdgpu_ras_enable !=3D 2 || + adev->pm.fw_version <=3D 0x283400)) baco_reset =3D false; } break; -- 2.7.4 --_000_MN2PR12MB4285E37DF7D44270D5CAD0E5F6440MN2PR12MB4285namp_ Content-Type: text/html; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable

Agree with your thoughts that we drop amdgpu_ras_= enable=3D2 condition. The only concern in my side is that besides fatal_err= or, another result may happen that atombios_init timeout on xgmi by baco (n= ot sure psp mode1 reset causes this as well).

 

Assuming no amdgpu_ras_enable=3D2 check, if PMFW = > 40.52,  the use cases as my understanding includes:

  1. sGPU without RAS:
    • new: baco
    • old: baco
  2. sGPU with RAS:
  • new: baco
  • old: psp mode1 chain reset and legacy fa= tal_error handling
  1. XGMI with RAS: baco
    • new: baco
    • old: psp mode1 chain reset and legacy fata= l_error handling
  2. XGMI without RAS: baco
    • new: baco
    • old: psp mode1 chain reset
      • =

 

That is to say, all uses cases go on baco road wh= en PMFW > 40.52.

 

Regards,

Ma Le

 

-----Original Message-----
From: Zhang, Hawking <Hawking.Zhang-5C7GfCeVMHo@public.gmane.org>
Sent: Wednesday, November 27, 2019 7:28 PM
To: Ma, Le <Le.Ma-5C7GfCeVMHo@public.gmane.org>; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Chen, Guchun <Guchun.Chen-5C7GfCeVMHo@public.gmane.org>; Zhou1, Tao <Tao.Zhou1@amd.= com>; Li, Dennis <Dennis.Li-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexa= nder.Deucher-5C7GfCeVMHo@public.gmane.org>; Ma, Le <Le.Ma-5C7GfCeVMHo@public.gmane.org>
Subject: RE: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgm= i/ras case

 

[AMD Public Use]

 

After thinking it a bit, I think we can just rely= on PMFW version to decide to go RAS recovery or legacy fatal_error handlin= g for the platforms that support RAS. Leveraging amdgpu_ras_enable as a tem= porary solution seems not necessary? Even baco ras recovery not stable, it is the same result as legacy fatal_e= rror handling that user has to reboot the node manually.

 

So the new soc reset use cases are:

XGMI (without RAS): use PSP mode1 based chain res= et, RAS enabled (with PMFW 40.52 and onwards): use BACO based RAS recovery,= RAS enabled (with PMFW prior to 40.52): use legacy fatal_error handling.

Anything else?

 

Regards,

Hawking

-----Original Message-----

From: Le Ma <= le.ma-5C7GfCeVMHo@public.gmane.org<= /a>>

Sent: 2019=1B$BG/=1B(B11=1B= $B7n=1B(B27=1B$BF|=1B(B 17:15

To: amd-gfx-PD4FTy7X32mzQB+pC5nmwQ@public.gmane.org= edesktop.org

Cc: Zhang, Hawking <Hawkin= g.Zhang-5C7GfCeVMHo@public.gmane.org>; Chen, Guchun <Guchun.C= hen-5C7GfCeVMHo@public.gmane.org>; Zhou1, Tao <Tao.Zhou1-5C7GfCeVMHo@public.gmane.org>; Li, Denni= s <Dennis.Li-5C7GfCeVMHo@public.gmane.org>; Deucher, Alexander <Alexander.Deucher-5C7GfCeVMHo@public.gmane.org>; Ma, Le <Le.Ma-5C7GfCeVMHo@public.gmane.org>

Subject: [PATCH 06/10] drm/amdgpu: add condition = to enable baco for xgmi/ras case

 

Avoid to change default reset behavior for produc= tion card by checking amdgpu_ras_enable equal to 2. And only new enough smu= ucode can support baco for xgmi/ras case.

 

Change-Id: I07c3e6862be03e068745c73db8ea71f428ecb= a6b

Signed-off-by: Le Ma <le.ma-urvtwAKJhsc@public.gmane.org= m>

---

drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++= +-

1 file changed, 3 insertions(+), 1 deletion(-= )

 

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b= /drivers/gpu/drm/amd/amdgpu/soc15.c

index 951327f..6202333 100644

--- a/drivers/gpu/drm/amd/amdgpu/soc15.c

+++ b/drivers/gpu/drm/amd/amdgpu/soc1= 5.c

@@ -577,7 +577,9 @@ soc15_asic_reset_method(s= truct amdgpu_device *adev)

        &= nbsp;           &nbs= p;            &= nbsp; struct amdgpu_hive_info *hive =3D amdgpu_get_xgmi_hive(adev, 0);=

        &= nbsp;           &nbs= p;            &= nbsp; struct amdgpu_ras *ras =3D amdgpu_ras_get_context(adev);

-        =             &nb= sp;            =   if (hive || (ras && ras->supported))

+       &n= bsp;            = ;            &n= bsp; if ((hive || (ras && ras->supported)) &&=

+       &n= bsp;            = ;            &n= bsp;     (amdgpu_ras_enable !=3D 2 ||

+       &n= bsp;            = ;            &n= bsp;     adev->pm.fw_version <=3D 0x283400))

        &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p; baco_reset =3D false;

        &= nbsp;           &nbs= p;  }

        &= nbsp;           &nbs= p;  break;

--

2.7.4

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Wed, 27 Nov 2019 12:35:57 +0000 From: "Ma, Le" To: "Zhang, Hawking" , "amd-gfx@lists.freedesktop.org" Subject: RE: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgmi/ras case Thread-Topic: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgmi/ras case Thread-Index: AQHVpQNF8p3JP+rj2kWZAyQf5kXx/6ee4XoAgAAFO3A= Date: Wed, 27 Nov 2019 12:35:57 +0000 Message-ID: References: <1574846129-4826-1-git-send-email-le.ma@amd.com> <1574846129-4826-5-git-send-email-le.ma@amd.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_Enabled=true; MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_SetDate=2019-11-27T11:03:26Z; MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_Method=Privileged; MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_Name=Public_0; MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_SiteId=3dd8961f-e488-4e60-8e11-a82d994e183d; MSIP_Label_0d814d60-469d-470c-8cb0-58434e2bf457_ActionId=1deaade1-8d67-4c40-8ee3-0000834588a2; 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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hKrf0++O3nnlDlOG4RAX8SuNzEKQkmv8nmL9q88OC7s=; b=If/xYTY/hQ9D3ZJIFPIEZNHliyYmcoFnIynP52omZqkKD4or2Io2jfz9jb8ED4l/Pfs9QY3cNOpivFJdH8PlYQQ28KzvfldpiTha9y8kqkxrvrOCMgEi7yiYJjM0yWVla+IyHWSI5H+2lX5TrnpB5L+13oUC0IE1tOddxl9tdQE= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Le.Ma@amd.com; X-BeenThere: amd-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Deucher, Alexander" , "Zhou1, Tao" , "Li, Dennis" , "Chen, Guchun" Content-Type: multipart/mixed; boundary="===============1598236071==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" Message-ID: <20191127123557.t6hdpWeERzLydbQCd-cmZ8Ezdf-AUrbq-85n6WHKSbQ@z> --===============1598236071== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MN2PR12MB4285E37DF7D44270D5CAD0E5F6440MN2PR12MB4285namp_" --_000_MN2PR12MB4285E37DF7D44270D5CAD0E5F6440MN2PR12MB4285namp_ Content-Type: text/plain; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Agree with your thoughts that we drop amdgpu_ras_enable=3D2 condition. The = only concern in my side is that besides fatal_error, another result may hap= pen that atombios_init timeout on xgmi by baco (not sure psp mode1 reset ca= uses this as well). Assuming no amdgpu_ras_enable=3D2 check, if PMFW > 40.52, the use cases as= my understanding includes: 1. sGPU without RAS: * new: baco * old: baco 2. sGPU with RAS: * new: baco * old: psp mode1 chain reset and legacy fatal_error handling 1. XGMI with RAS: baco * new: baco * old: psp mode1 chain reset and legacy fatal_error handling 2. XGMI without RAS: baco * new: baco * old: psp mode1 chain reset That is to say, all uses cases go on baco road when PMFW > 40.52. Regards, Ma Le -----Original Message----- From: Zhang, Hawking Sent: Wednesday, November 27, 2019 7:28 PM To: Ma, Le ; amd-gfx@lists.freedesktop.org Cc: Chen, Guchun ; Zhou1, Tao ; Li,= Dennis ; Deucher, Alexander = ; Ma, Le Subject: RE: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgm= i/ras case [AMD Public Use] After thinking it a bit, I think we can just rely on PMFW version to decide= to go RAS recovery or legacy fatal_error handling for the platforms that s= upport RAS. Leveraging amdgpu_ras_enable as a temporary solution seems not = necessary? Even baco ras recovery not stable, it is the same result as lega= cy fatal_error handling that user has to reboot the node manually. So the new soc reset use cases are: XGMI (without RAS): use PSP mode1 based chain reset, RAS enabled (with PMFW= 40.52 and onwards): use BACO based RAS recovery, RAS enabled (with PMFW pr= ior to 40.52): use legacy fatal_error handling. Anything else? Regards, Hawking -----Original Message----- From: Le Ma > Sent: 2019=1B$BG/=1B(B11=1B$B7n=1B(B27=1B$BF|=1B(B 17:15 To: amd-gfx@lists.freedesktop.org Cc: Zhang, Hawking >; C= hen, Guchun >; Zhou1, Tao <= Tao.Zhou1@amd.com>; Li, Dennis >; Deucher, Alexander >; Ma, Le > Subject: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgmi/ra= s case Avoid to change default reset behavior for production card by checking amdg= pu_ras_enable equal to 2. And only new enough smu ucode can support baco fo= r xgmi/ras case. Change-Id: I07c3e6862be03e068745c73db8ea71f428ecba6b Signed-off-by: Le Ma > --- drivers/gpu/drm/amd/amdgpu/soc15.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgp= u/soc15.c index 951327f..6202333 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -577,7 +577,9 @@ soc15_asic_reset_method(struct amdgpu_device *adev) struct amdgpu_hive_info *hive =3D amdgpu= _get_xgmi_hive(adev, 0); struct amdgpu_ras *ras =3D amdgpu_ras_ge= t_context(adev); - if (hive || (ras && ras->supported)) + if ((hive || (ras && ras->supported)) && + (amdgpu_ras_enable !=3D 2 || + adev->pm.fw_version <=3D 0x283400)) baco_reset =3D false; } break; -- 2.7.4 --_000_MN2PR12MB4285E37DF7D44270D5CAD0E5F6440MN2PR12MB4285namp_ Content-Type: text/html; charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable

Agree with your thoughts that we drop amdgpu_ras_= enable=3D2 condition. The only concern in my side is that besides fatal_err= or, another result may happen that atombios_init timeout on xgmi by baco (n= ot sure psp mode1 reset causes this as well).

 

Assuming no amdgpu_ras_enable=3D2 check, if PMFW = > 40.52,  the use cases as my understanding includes:

  1. sGPU without RAS:
    • new: baco
    • old: baco
  2. sGPU with RAS:
  • new: baco
  • old: psp mode1 chain reset and legacy fa= tal_error handling
  1. XGMI with RAS: baco
    • new: baco
    • old: psp mode1 chain reset and legacy fata= l_error handling
  2. XGMI without RAS: baco
    • new: baco
    • old: psp mode1 chain reset
      • =

 

That is to say, all uses cases go on baco road wh= en PMFW > 40.52.

 

Regards,

Ma Le

 

-----Original Message-----
From: Zhang, Hawking <Hawking.Zhang@amd.com>
Sent: Wednesday, November 27, 2019 7:28 PM
To: Ma, Le <Le.Ma@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Chen, Guchun <Guchun.Chen@amd.com>; Zhou1, Tao <Tao.Zhou1@amd.= com>; Li, Dennis <Dennis.Li@amd.com>; Deucher, Alexander <Alexa= nder.Deucher@amd.com>; Ma, Le <Le.Ma@amd.com>
Subject: RE: [PATCH 06/10] drm/amdgpu: add condition to enable baco for xgm= i/ras case

 

[AMD Public Use]

 

After thinking it a bit, I think we can just rely= on PMFW version to decide to go RAS recovery or legacy fatal_error handlin= g for the platforms that support RAS. Leveraging amdgpu_ras_enable as a tem= porary solution seems not necessary? Even baco ras recovery not stable, it is the same result as legacy fatal_e= rror handling that user has to reboot the node manually.

 

So the new soc reset use cases are:

XGMI (without RAS): use PSP mode1 based chain res= et, RAS enabled (with PMFW 40.52 and onwards): use BACO based RAS recovery,= RAS enabled (with PMFW prior to 40.52): use legacy fatal_error handling.

Anything else?

 

Regards,

Hawking

-----Original Message-----

From: Le Ma <= le.ma@amd.com<= /a>>

Sent: 2019=1B$BG/=1B(B11=1B= $B7n=1B(B27=1B$BF|=1B(B 17:15

To: amd-gfx@lists.fre= edesktop.org

Cc: Zhang, Hawking <Hawkin= g.Zhang@amd.com>; Chen, Guchun <Guchun.C= hen@amd.com>; Zhou1, Tao <Tao.Zhou1@amd.com>; Li, Denni= s <Dennis.Li@amd.com>; Deucher, Alexander <Alexander.Deucher@amd.com>; Ma, Le <Le.Ma@amd.com>

Subject: [PATCH 06/10] drm/amdgpu: add condition = to enable baco for xgmi/ras case

 

Avoid to change default reset behavior for produc= tion card by checking amdgpu_ras_enable equal to 2. And only new enough smu= ucode can support baco for xgmi/ras case.

 

Change-Id: I07c3e6862be03e068745c73db8ea71f428ecb= a6b

Signed-off-by: Le Ma <le.ma@amd.co= m>

---

drivers/gpu/drm/amd/amdgpu/soc15.c | 4 ++= +-

1 file changed, 3 insertions(+), 1 deletion(-= )

 

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b= /drivers/gpu/drm/amd/amdgpu/soc15.c

index 951327f..6202333 100644

--- a/drivers/gpu/drm/amd/amdgpu/soc15.c

+++ b/drivers/gpu/drm/amd/amdgpu/soc1= 5.c

@@ -577,7 +577,9 @@ soc15_asic_reset_method(s= truct amdgpu_device *adev)

        &= nbsp;           &nbs= p;            &= nbsp; struct amdgpu_hive_info *hive =3D amdgpu_get_xgmi_hive(adev, 0);=

        &= nbsp;           &nbs= p;            &= nbsp; struct amdgpu_ras *ras =3D amdgpu_ras_get_context(adev);

-        =             &nb= sp;            =   if (hive || (ras && ras->supported))

+       &n= bsp;            = ;            &n= bsp; if ((hive || (ras && ras->supported)) &&=

+       &n= bsp;            = ;            &n= bsp;     (amdgpu_ras_enable !=3D 2 ||

+       &n= bsp;            = ;            &n= bsp;     adev->pm.fw_version <=3D 0x283400))

        &= nbsp;           &nbs= p;            &= nbsp;           &nbs= p; baco_reset =3D false;

        &= nbsp;           &nbs= p;  }

        &= nbsp;           &nbs= p;  break;

--

2.7.4

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