From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pragnesh Patel Date: Mon, 6 Jan 2020 09:07:17 +0000 Subject: [PATCH 1/3] riscv: Add place-holder for FU540 clk and gpio In-Reply-To: References: <20191231063055.19412-1-pragnesh.patel@sifive.com> <20191231063055.19412-2-pragnesh.patel@sifive.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de >-----Original Message----- >From: Bin Meng >Sent: 03 January 2020 20:18 >To: Pragnesh Patel >Cc: U-Boot Mailing List ; Rick Chen >; Paul Walmsley ( Sifive) ; >Palmer Dabbelt ( Sifive) ; Anup Patel >; Atish Patra ; Sagar Kadam > >Subject: Re: [PATCH 1/3] riscv: Add place-holder for FU540 clk and gpio > >Hi Pragnesh, > >On Tue, Dec 31, 2019 at 2:31 PM Pragnesh Patel >wrote: >> >> Added FU540 place-holder so that SoC specific values will be kept >> here. > >It looks only clk.h is the placer-holder. gpio.h is not. > >Can you please split the gpio.h changes to another patch? Sure, I will do this in v2 patch. > >> >> Signed-off-by: Pragnesh Patel >> --- >> arch/riscv/include/asm/arch-fu540/clk.h | 14 ++++++++ >> arch/riscv/include/asm/arch-fu540/gpio.h | 42 ++++++++++++++++++++++ >> arch/riscv/include/asm/arch-generic/gpio.h | 32 ++--------------- >> board/sifive/fu540/Kconfig | 3 ++ >> 4 files changed, 62 insertions(+), 29 deletions(-) create mode >> 100644 arch/riscv/include/asm/arch-fu540/clk.h >> create mode 100644 arch/riscv/include/asm/arch-fu540/gpio.h >> >> diff --git a/arch/riscv/include/asm/arch-fu540/clk.h >> b/arch/riscv/include/asm/arch-fu540/clk.h >> new file mode 100644 >> index 0000000000..b39f5b55c9 >> --- /dev/null >> +++ b/arch/riscv/include/asm/arch-fu540/clk.h >> @@ -0,0 +1,14 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * Copyright (c) 2019 SiFive, Inc. >> + * >> + * Authors: >> + * Pragnesh Patel >> + */ >> + >> +#ifndef _CLK_FU540_H >> +#define _CLK_FU540_H >> + >> +/* Note: This is a placeholder header for driver compilation. */ >> + >> +#endif >> diff --git a/arch/riscv/include/asm/arch-fu540/gpio.h >> b/arch/riscv/include/asm/arch-fu540/gpio.h > >It looks this file is a copy of >arch/riscv/include/asm/arch-generic/gpio.h. Can you explain this a little bit? arch-generic/gpio.h contains register information which is specific for FU540, so I moved the gpio.h from "arch-generic" to "arch-fu540". I have added arch/riscv/include/asm/arch-fu540/ directory that will contain FU540 related header files and arch/riscv/include/asm/arch-generic/ will contain generic riscv header files. Earlier SYS_SOC for FU540 was not defined, so drivers used "arch-generic" header files which I feel can be changed to "arch-fu540". > >> new file mode 100644 >> index 0000000000..f8ddd75852 >> --- /dev/null >> +++ b/arch/riscv/include/asm/arch-fu540/gpio.h >> @@ -0,0 +1,42 @@ >> +/* SPDX-License-Identifier: GPL-2.0+ */ >> +/* >> + * Copyright (C) 2019 SiFive, Inc. >> + * >> + * Authors: >> + * Sagar Shrikant Kadam >> + */ >> + >> +#ifndef _GPIO_FU540_H >> +#define _GPIO_FU540_H >> + >> +#define GPIO_INPUT_VAL (0x00) >> +#define GPIO_INPUT_EN (0x04) >> +#define GPIO_OUTPUT_EN (0x08) >> +#define GPIO_OUTPUT_VAL (0x0C) >> +#define GPIO_PULLUP_EN (0x10) >> +#define GPIO_DRIVE (0x14) >> +#define GPIO_RISE_IE (0x18) >> +#define GPIO_RISE_IP (0x1C) >> +#define GPIO_FALL_IE (0x20) >> +#define GPIO_FALL_IP (0x24) >> +#define GPIO_HIGH_IE (0x28) >> +#define GPIO_HIGH_IP (0x2C) >> +#define GPIO_LOW_IE (0x30) >> +#define GPIO_LOW_IP (0x34) >> +#define GPIO_IOF_EN (0x38) >> +#define GPIO_IOF_SEL (0x3C) >> +#define GPIO_OUTPUT_XOR (0x40) >> + >> +#define NR_GPIOS 16 >> + >> +enum gpio_state { >> + LOW, >> + HIGH >> +}; >> + >> +/* Details about a GPIO bank */ >> +struct sifive_gpio_platdata { >> + void *base; /* address of registers in physical memory */ >> +}; >> + >> +#endif /* _GPIO_FU540_H */ >> diff --git a/arch/riscv/include/asm/arch-generic/gpio.h >> b/arch/riscv/include/asm/arch-generic/gpio.h >> index dfcb753051..5f0dc0a801 100644 >> --- a/arch/riscv/include/asm/arch-generic/gpio.h >> +++ b/arch/riscv/include/asm/arch-generic/gpio.h >> @@ -3,33 +3,7 @@ >> * Copyright (C) 2019 SiFive, Inc. >> */ >> >> -#ifndef _GPIO_SIFIVE_H >> -#define _GPIO_SIFIVE_H >> +#ifndef __ASM_RISCV_ARCH_GPIO_H >> +#define __ASM_RISCV_ARCH_GPIO_H >> >> -#define GPIO_INPUT_VAL 0x00 >> -#define GPIO_INPUT_EN 0x04 >> -#define GPIO_OUTPUT_EN 0x08 >> -#define GPIO_OUTPUT_VAL 0x0C >> -#define GPIO_RISE_IE 0x18 >> -#define GPIO_RISE_IP 0x1C >> -#define GPIO_FALL_IE 0x20 >> -#define GPIO_FALL_IP 0x24 >> -#define GPIO_HIGH_IE 0x28 >> -#define GPIO_HIGH_IP 0x2C >> -#define GPIO_LOW_IE 0x30 >> -#define GPIO_LOW_IP 0x34 >> -#define GPIO_OUTPUT_XOR 0x40 >> - >> -#define NR_GPIOS 16 >> - >> -enum gpio_state { >> - LOW, >> - HIGH >> -}; >> - >> -/* Details about a GPIO bank */ >> -struct sifive_gpio_platdata { >> - void *base; /* address of registers in physical memory */ >> -}; >> - >> -#endif /* _GPIO_SIFIVE_H */ >> +#endif /* __ASM_RISCV_ARCH_GPIO_H */ >> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig >> index 5ca21474de..816a135b21 100644 >> --- a/board/sifive/fu540/Kconfig >> +++ b/board/sifive/fu540/Kconfig >> @@ -12,6 +12,9 @@ config SYS_CPU >> config SYS_CONFIG_NAME >> default "sifive-fu540" >> >> +config SYS_SOC >> + default "fu540" > >What about SYS_CPU? > >Shouldn't we just rename SYS_CPU to SYS_SOC in this file and assign "fu540" >to it? No, I am not planning to change SYS_CPU to "fu540" because Same discussion happened earlier, you can check here http://u-boot.10912.n7.nabble.com/PATCH-sifive-riscv-streamline-HiFive-Unleashed-configuration-infrastructure-td379038.html I have added SYS_SOC to "fu540" because arch-generic should not include FU540 specific headers. > >> + >> config SYS_TEXT_BASE >> default 0x80000000 if !RISCV_SMODE >> default 0x80200000 if RISCV_SMODE >> -- > >Regards, >Bin