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boundary="===============1814472293==" Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" --===============1814472293== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MW2PR12MB4684ECE117B6D8CB2FEA84F2FD2B9MW2PR12MB4684namp_" --_000_MW2PR12MB4684ECE117B6D8CB2FEA84F2FD2B9MW2PR12MB4684namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable [Public] Hi Alex, This is the issue exposed by Nirmoy's patch that provided better load balan= cing across queues. BR, Changfeng. From: Deucher, Alexander Sent: Wednesday, May 19, 2021 10:53 AM To: Zhu, Changfeng ; Alex Deucher ; Das, Nirmoy Cc: Huang, Ray ; amd-gfx list Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid = compute hang [Public] + Nirmoy I thought we disabled all but one of the compute queues on raven due to thi= s issue. Maybe that patch never landed? Wasn't this the same issue that w= as exposed by Nirmoy's patch that provided better load balancing across que= ues? Alex ________________________________ From: amd-gfx > on behalf of Zhu, Changfeng > Sent: Tuesday, May 18, 2021 10:28 PM To: Alex Deucher > Cc: Huang, Ray >; amd-gfx list = > Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid = compute hang [AMD Official Use Only - Internal Distribution Only] Hi Alex. I have submitted the patch: drm/amdgpu: disable 3DCGCG on picasso/raven1 to= avoid compute hang Do you mean we have something else to do for re-enabling the extra compute = queues? BR, Changfeng. -----Original Message----- From: Alex Deucher > Sent: Wednesday, May 19, 2021 10:20 AM To: Zhu, Changfeng > Cc: Huang, Ray >; amd-gfx list = > Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid = compute hang Care to submit a patch to re-enable the extra compute queues? Alex On Mon, May 17, 2021 at 4:09 AM Zhu, Changfeng > wrote: > > [AMD Official Use Only - Internal Distribution Only] > > Hi Ray and Alex, > > I have confirmed it can enable the additional compute queues with this pa= tch: > > [ 41.823013] This is ring mec 1, pipe 0, queue 0, value 1 > [ 41.823028] This is ring mec 1, pipe 1, queue 0, value 1 > [ 41.823042] This is ring mec 1, pipe 2, queue 0, value 1 > [ 41.823057] This is ring mec 1, pipe 3, queue 0, value 1 > [ 41.823071] This is ring mec 1, pipe 0, queue 1, value 1 > [ 41.823086] This is ring mec 1, pipe 1, queue 1, value 1 > [ 41.823101] This is ring mec 1, pipe 2, queue 1, value 1 > [ 41.823115] This is ring mec 1, pipe 3, queue 1, value 1 > > BR, > Changfeng. > > > -----Original Message----- > From: Huang, Ray > > Sent: Monday, May 17, 2021 2:27 PM > To: Alex Deucher >; Z= hu, Changfeng > > > Cc: amd-gfx list > > Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to > avoid compute hang > > On Fri, May 14, 2021 at 10:13:55PM +0800, Alex Deucher wrote: > > On Fri, May 14, 2021 at 4:20 AM > wrote: > > > > > > From: changzhu > > > > > > > From: Changfeng > > > > > > > There is problem with 3DCGCG firmware and it will cause compute > > > test hang on picasso/raven1. It needs to disable 3DCGCG in driver > > > to avoid compute hang. > > > > > > Change-Id: Ic7d3c7922b2b32f7ac5193d6a4869cbc5b3baa87 > > > Signed-off-by: Changfeng > > > > > Reviewed-by: Alex Deucher > > > > > WIth this applied, can we re-enable the additional compute queues? > > > > I think so. > > Changfeng, could you please confirm this on all raven series? > > Patch is Reviewed-by: Huang Rui > > > > Alex > > > > > --- > > > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++++--- > > > drivers/gpu/drm/amd/amdgpu/soc15.c | 2 -- > > > 2 files changed, 7 insertions(+), 5 deletions(-) > > > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > index 22608c45f07c..feaa5e4a5538 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > > > @@ -4947,7 +4947,7 @@ static void gfx_v9_0_update_3d_clock_gating(str= uct amdgpu_device *adev, > > > amdgpu_gfx_rlc_enter_safe_mode(adev); > > > > > > /* Enable 3D CGCG/CGLS */ > > > - if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) = { > > > + if (enable) { > > > /* write cmd to clear cgcg/cgls ov */ > > > def =3D data =3D RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_= OVERRIDE); > > > /* unset CGCG override */ @@ -4959,8 +4959,12 @@ > > > static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *ade= v, > > > /* enable 3Dcgcg FSM(0x0000363f) */ > > > def =3D RREG32_SOC15(GC, 0, > > > mmRLC_CGCG_CGLS_CTRL_3D); > > > > > > - data =3D (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDL= E_THRESHOLD__SHIFT) | > > > - RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; > > > + if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) > > > + data =3D (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG= _GFX_IDLE_THRESHOLD__SHIFT) | > > > + RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK; > > > + else > > > + data =3D 0x0 << > > > + RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT; > > > + > > > if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) > > > data |=3D (0x000F << RLC_CGCG_CGLS_CTRL_3D__C= GLS_REP_COMPANSAT_DELAY__SHIFT) | > > > > > > RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK; > > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c > > > b/drivers/gpu/drm/amd/amdgpu/soc15.c > > > index 4b660b2d1c22..080e715799d4 100644 > > > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c > > > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c > > > @@ -1393,7 +1393,6 @@ static int soc15_common_early_init(void *handle= ) > > > adev->cg_flags =3D AMD_CG_SUPPORT_GFX_MGCG | > > > AMD_CG_SUPPORT_GFX_MGLS | > > > AMD_CG_SUPPORT_GFX_CP_LS | > > > - AMD_CG_SUPPORT_GFX_3D_CGCG | > > > AMD_CG_SUPPORT_GFX_3D_CGLS | > > > AMD_CG_SUPPORT_GFX_CGCG | > > > AMD_CG_SUPPORT_GFX_CGLS | @@ > > > -1413,7 > > > +1412,6 @@ static int soc15_common_early_init(void *handle) > > > AMD_CG_SUPPORT_GFX_MGLS | > > > AMD_CG_SUPPORT_GFX_RLC_LS | > > > AMD_CG_SUPPORT_GFX_CP_LS | > > > - AMD_CG_SUPPORT_GFX_3D_CGCG | > > > AMD_CG_SUPPORT_GFX_3D_CGLS | > > > AMD_CG_SUPPORT_GFX_CGCG | > > > AMD_CG_SUPPORT_GFX_CGLS | > > > -- > > > 2.17.1 > > > > > > _______________________________________________ > > > amd-gfx mailing list > > > amd-gfx@lists.freedesktop.org > > > https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2F > > > li > > > sts.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D04%7C0 > > > 1% > > > 7CRay.Huang%40amd.com%7C0e273856253d4b3efd0b08d916e2892a%7C3dd8961 > > > fe > > > 4884e608e11a82d994e183d%7C0%7C0%7C637565984495414849%7CUnknown%7CT > > > WF > > > pbGZsb3d8eyJWIjoiMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXV > > > CI > > > 6Mn0%3D%7C1000&sdata=3DlBzswAPBguL0mWFglEk%2Bg2eDCEuhir7JfFjov%2 > > > BV > > > 7pSY%3D&reserved=3D0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flists.f= reedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D04%7C01%7Calexande= r.deucher%40amd.com%7C6d2cfe6e59f54875f6fa08d91a6dd27f%7C3dd8961fe4884e608e= 11a82d994e183d%7C0%7C0%7C637569881259273626%7CUnknown%7CTWFpbGZsb3d8eyJWIjo= iMC4wLjAwMDAiLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C1000&sdat= a=3D33Is2P3sqdabI7PPuHFOmzuvXyFId%2BOTAMyJ8G5PhzI%3D&reserved=3D0 --_000_MW2PR12MB4684ECE117B6D8CB2FEA84F2FD2B9MW2PR12MB4684namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

[Public]


Hi Alex,

 

This is the issue exposed by Nirmoy's patch that provided better load balancing across queues.

&n= bsp;

BR,

Changfe= ng.

 

From: Deucher, Alexander <Alexander.Deuche= r@amd.com>
Sent: Wednesday, May 19, 2021 10:53 AM
To: Zhu, Changfeng <Changfeng.Zhu@amd.com>; Alex Deucher <a= lexdeucher@gmail.com>; Das, Nirmoy <Nirmoy.Das@amd.com>
Cc: Huang, Ray <Ray.Huang@amd.com>; amd-gfx list <amd-gfx@l= ists.freedesktop.org>
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to= avoid compute hang

 

[Public]

 

+ Nirmo= y

&n= bsp;

I thoug= ht we disabled all but one of the compute queues on raven due to this issue= .  Maybe that patch never landed?  Wasn't this the same issue tha= t was exposed by Nirmoy's patch that provided better load balancing across queues?

&n= bsp;

Alex

&n= bsp;

From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> on behalf o= f Zhu, Changfeng <Changfeng.Zhu= @amd.com>
Sent: Tuesday, May 18, 2021 10:28 PM
To: Alex Deucher <alexde= ucher@gmail.com>
Cc: Huang, Ray <Ray.Huang@am= d.com>; amd-gfx list <amd-gfx@lists.freedesktop.org>
Subject: RE: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to= avoid compute hang

 

[AMD Official Use Only - Internal Distribution Only]=

Hi Alex.

I have submitted the patch: drm/amdgpu: disable 3DCGCG on picasso/raven1 to= avoid compute hang

Do you mean we have something else to do for re-enabling the extra compute = queues?

BR,
Changfeng.

-----Original Message-----
From: Alex Deucher <alexdeucher= @gmail.com>
Sent: Wednesday, May 19, 2021 10:20 AM
To: Zhu, Changfeng <Changfeng.Z= hu@amd.com>
Cc: Huang, Ray <Ray.Huang@amd.com>; amd-gfx list <a= md-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid = compute hang

Care to submit a patch to re-enable the extra compute queues?

Alex

On Mon, May 17, 2021 at 4:09 AM Zhu, Changfeng <Changfeng.Zhu@amd.com> wrote:
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Hi Ray and Alex,
>
> I have confirmed it can enable the additional compute queues with this= patch:
>
> [   41.823013] This is ring mec 1, pipe 0, queue 0, value 1<= br> > [   41.823028] This is ring mec 1, pipe 1, queue 0, value 1<= br> > [   41.823042] This is ring mec 1, pipe 2, queue 0, value 1<= br> > [   41.823057] This is ring mec 1, pipe 3, queue 0, value 1<= br> > [   41.823071] This is ring mec 1, pipe 0, queue 1, value 1<= br> > [   41.823086] This is ring mec 1, pipe 1, queue 1, value 1<= br> > [   41.823101] This is ring mec 1, pipe 2, queue 1, value 1<= br> > [   41.823115] This is ring mec 1, pipe 3, queue 1, value 1<= br> >
> BR,
> Changfeng.
>
>
> -----Original Message-----
> From: Huang, Ray <Ray.Huang@am= d.com>
> Sent: Monday, May 17, 2021 2:27 PM
> To: Alex Deucher <alexdeuc= her@gmail.com>; Zhu, Changfeng
> <Changfeng.Zhu@amd.com= >
> Cc: amd-gfx list <= amd-gfx@lists.freedesktop.org>
> Subject: Re: [PATCH] drm/amdgpu: disable 3DCGCG on picasso/raven1 to <= br> > avoid compute hang
>
> On Fri, May 14, 2021 at 10:13:55PM +0800, Alex Deucher wrote:
> > On Fri, May 14, 2021 at 4:20 AM <changfeng.zhu@amd.com> wrote:
> > >
> > > From: changzhu <= Changfeng.Zhu@amd.com>
> > >
> > > From: Changfeng <Changfeng.Zhu@amd.com>
> > >
> > > There is problem with 3DCGCG firmware and it will cause comp= ute
> > > test hang on picasso/raven1. It needs to disable 3DCGCG in d= river
> > > to avoid compute hang.
> > >
> > > Change-Id: Ic7d3c7922b2b32f7ac5193d6a4869cbc5b3baa87
> > > Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
> >
> > Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> >
> > WIth this applied, can we re-enable the additional compute queues= ?
> >
>
> I think so.
>
> Changfeng, could you please confirm this on all raven series?
>
> Patch is Reviewed-by: Huang Rui <ray.huang@amd.com>
>
> > Alex
> >
> > > ---
> > >  drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 10 +++++++---<= br> > > >  drivers/gpu/drm/amd/amdgpu/soc15.c    |=   2 --
> > >  2 files changed, 7 insertions(+), 5 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > index 22608c45f07c..feaa5e4a5538 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> > > @@ -4947,7 +4947,7 @@ static void gfx_v9_0_update_3d_clock_g= ating(struct amdgpu_device *adev,
> > >         amdgpu_gfx_r= lc_enter_safe_mode(adev);
> > >
> > >         /* Enable 3D= CGCG/CGLS */
> > > -       if (enable && = (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
> > > +       if (enable) {
> > >          &= nbsp;      /* write cmd to clear cgcg/cgls ov */ > > >          &= nbsp;      def =3D data =3D RREG32_SOC15(GC, 0, mm= RLC_CGTT_MGCG_OVERRIDE);
> > >          &= nbsp;      /* unset CGCG override */ @@ -4959,8 +4= 959,12 @@
> > > static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_de= vice *adev,
> > >          &= nbsp;      /* enable 3Dcgcg FSM(0x0000363f) */
> > >          &= nbsp;      def =3D RREG32_SOC15(GC, 0,
> > > mmRLC_CGCG_CGLS_CTRL_3D);
> > >
> > > -          = ;     data =3D (0x36 << RLC_CGCG_CGLS_CTRL_3D__CG= CG_GFX_IDLE_THRESHOLD__SHIFT) |
> > > -          = ;             R= LC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
> > > +          = ;     if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D= _CGCG)
> > > +          = ;             d= ata =3D (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIF= T) |
> > > +          = ;            &n= bsp;        RLC_CGCG_CGLS_CTRL_3D__CGCG_= EN_MASK;
> > > +          = ;     else
> > > +          = ;             d= ata =3D 0x0 <<
> > > + RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT;
> > > +
> > >          &= nbsp;      if (adev->cg_flags & AMD_CG_SUPP= ORT_GFX_3D_CGLS)
> > >          &= nbsp;           &nbs= p;  data |=3D (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANS= AT_DELAY__SHIFT) |
> > >          &= nbsp;           &nbs= p;         
> > > RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > index 4b660b2d1c22..080e715799d4 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
> > > @@ -1393,7 +1393,6 @@ static int soc15_common_early_init(voi= d *handle)
> > >          &= nbsp;           &nbs= p;  adev->cg_flags =3D AMD_CG_SUPPORT_GFX_MGCG |
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _MGLS |
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _CP_LS |
> > > -          = ;            &n= bsp;        AMD_CG_SUPPORT_GFX_3D_CGCG |=
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _3D_CGLS |
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _CGCG |
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _CGLS | @@
> > > -1413,7
> > > +1412,6 @@ static int soc15_common_early_init(void *handle)<= br> > > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _MGLS |
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _RLC_LS |
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _CP_LS |
> > > -          = ;            &n= bsp;        AMD_CG_SUPPORT_GFX_3D_CGCG |=
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _3D_CGLS |
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _CGCG |
> > >          &= nbsp;           &nbs= p;          AMD_CG_SUPPORT_GFX= _CGLS |
> > > --
> > > 2.17.1
> > >
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