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Wed, 3 Feb 2021 09:26:46 +0000 From: Nava kishore Manne To: Moritz Fischer , Michal Simek CC: "trix@redhat.com" , "robh+dt@kernel.org" , "linux-fpga@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , git , "chinnikishore369@gmail.com" , Appana Durga Kedareswara Rao Subject: RE: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver Thread-Topic: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver Thread-Index: AQHW7USLyeY5b3FOfkKTbQUTtVqUFaouGt0AgAVRbYCAAnmHgIAFUX3ggAAIXQCAANEDgIAKLgJQ Date: Wed, 3 Feb 2021 09:26:46 +0000 Message-ID: References: <20210118024318.9530-1-nava.manne@xilinx.com> <20210118024318.9530-3-nava.manne@xilinx.com> <5ae6d181-3258-a877-23c5-6ba81c40b10a@xilinx.com> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: kernel.org; dkim=none (message not signed) header.d=none;kernel.org; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: MWHPR02MB2623.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: f29d4c19-9a7a-411c-8b2c-08d8c825d411 X-MS-Exchange-CrossTenant-originalarrivaltime: 03 Feb 2021 09:26:46.8145 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 9lmW/QU3XA2yCAq9qZh4CRMqlcV94nFndZzzwS+PG99EmOWJkUamsAjIHQccqyzSQJ9VLehqTlem1yFDbnk5jQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CO6PR02MB7540 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, > -----Original Message----- > From: Moritz Fischer > Sent: Thursday, January 28, 2021 3:15 AM > To: Michal Simek > Cc: Nava kishore Manne ; Moritz Fischer > ; trix@redhat.com; robh+dt@kernel.org; linux- > fpga@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; git > ; chinnikishore369@gmail.com; Appana Durga Kedareswara > Rao > Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager drive= r >=20 > On Wed, Jan 27, 2021 at 10:16:32AM +0100, Michal Simek wrote: > > Hi > > > > On 1/27/21 9:57 AM, Nava kishore Manne wrote: > > > Hi Moritz, > > > > > > Please find my response inline. > > > > > >> -----Original Message----- > > >> From: Moritz Fischer > > >> Sent: Sunday, January 24, 2021 5:04 AM > > >> To: Nava kishore Manne > > >> Cc: Moritz Fischer ; trix@redhat.com; > > >> robh+dt@kernel.org; Michal Simek ; linux- > > >> fpga@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > > >> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; git > > >> ; chinnikishore369@gmail.com; Appana Durga > > >> Kedareswara Rao > > >> Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager > > >> driver > > >> > > >> Hi Nava, > > >> > > >> On Fri, Jan 22, 2021 at 10:34:15AM +0000, Nava kishore Manne wrote: > > >>> Hi Moritz, > > >>> > > >>> Thanks for the review. > > >>> Please find my response inline. > > >>> > > >>>> -----Original Message----- > > >>>> From: Moritz Fischer > > >>>> Sent: Tuesday, January 19, 2021 6:03 AM > > >>>> To: Nava kishore Manne > > >>>> Cc: mdf@kernel.org; trix@redhat.com; robh+dt@kernel.org; Michal > > >>>> Simek ; linux-fpga@vger.kernel.org; > > >>>> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > >>>> linux- kernel@vger.kernel.org; git ; > > >>>> chinnikishore369@gmail.com; Appana Durga Kedareswara Rao > > >>>> > > >>>> Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga > > >>>> manager driver > > >>>> > > >>>> Hi Nava, > > >>>> > > >>>> On Mon, Jan 18, 2021 at 08:13:18AM +0530, Nava kishore Manne > wrote: > > >>>>> This patch adds driver for versal fpga manager. > > >>>> Nit: Add support for Xilinx Versal FPGA manager > > >>> > > >>> Will fix in v2. > > >>> > > >>>>> > > >>>>> PDI source type can be DDR, OCM, QSPI flash etc.. > > >>>> No idea what PDI is :) > > >>> > > >>> Programmable device image (PDI). > > >>> This file is generated by Xilinx Vivado tool and it contains > > >>> configuration data > > >> objects. > > >>> > > >>>>> But driver allocates memory always from DDR, Since driver > > >>>>> supports only DDR source type. > > >>>>> > > >>>>> Signed-off-by: Appana Durga Kedareswara rao > > >>>>> > > >>>>> Signed-off-by: Nava kishore Manne > > >>>>> --- > > >>>>> drivers/fpga/Kconfig | 8 ++ > > >>>>> drivers/fpga/Makefile | 1 + > > >>>>> drivers/fpga/versal-fpga.c | 149 > > >>>>> +++++++++++++++++++++++++++++++++++++ > > >>>>> 3 files changed, 158 insertions(+) create mode 100644 > > >>>>> drivers/fpga/versal-fpga.c > > >>>>> > > >>>>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > >>>>> 5645226ca3ce..9f779c3a6739 100644 > > >>>>> --- a/drivers/fpga/Kconfig > > >>>>> +++ b/drivers/fpga/Kconfig > > >>>>> @@ -216,4 +216,12 @@ config FPGA_MGR_ZYNQMP_FPGA > > >>>>> to configure the programmable logic(PL) through PS > > >>>>> on ZynqMP SoC. > > >>>>> > > >>>>> +config FPGA_MGR_VERSAL_FPGA > > >>>>> + tristate "Xilinx Versal FPGA" > > >>>>> + depends on ARCH_ZYNQMP || COMPILE_TEST > > >>>>> + help > > >>>>> + Select this option to enable FPGA manager driver suppo= rt for > > >>>>> + Xilinx Versal SOC. This driver uses the versal soc fir= mware > > >>>>> + interface to load programmable logic(PL) images > > >>>>> + on versal soc. > > >>>>> endif # FPGA > > >>>>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > >>>>> d8e21dfc6778..40c9adb6a644 100644 > > >>>>> --- a/drivers/fpga/Makefile > > >>>>> +++ b/drivers/fpga/Makefile > > >>>>> @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) > +=3D > > >>>> ts73xx-fpga.o > > >>>>> obj-$(CONFIG_FPGA_MGR_XILINX_SPI) +=3D xilinx-spi.o > > >>>>> obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) +=3D zynq-fpga.o > > >>>>> obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) +=3D zynqmp-fpga.o > > >>>>> +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) +=3D versal-fpga.o > > >>>>> obj-$(CONFIG_ALTERA_PR_IP_CORE) +=3D altera-pr-ip-core.o > > >>>>> obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) +=3D altera-pr-ip-core- > plat.o > > >>>>> > > >>>>> diff --git a/drivers/fpga/versal-fpga.c > > >>>>> b/drivers/fpga/versal-fpga.c new file mode 100644 index > > >>>>> 000000000000..2a42aa78b182 > > >>>>> --- /dev/null > > >>>>> +++ b/drivers/fpga/versal-fpga.c > > >>>>> @@ -0,0 +1,149 @@ > > >>>>> +// SPDX-License-Identifier: GPL-2.0+ > > >>>>> +/* > > >>>>> + * Copyright (C) 2021 Xilinx, Inc. > > >>>>> + */ > > >>>>> + > > >>>>> +#include > > >>>>> +#include #include #include > > >>>>> + #include #include > > >>>>> + #include #include > > >>>>> + > > >>>>> + > > >>>>> +/* Constant Definitions */ > > >>>>> +#define PDI_SOURCE_TYPE 0xF > > >>>>> + > > >>>>> +/** > > >>>>> + * struct versal_fpga_priv - Private data structure > > >>>>> + * @dev: Device data structure > > >>>>> + * @flags: flags which is used to identify the PL Image type > > >>>>> + */ > > >>>>> +struct versal_fpga_priv { > > >>>>> + struct device *dev; > > >>>>> + u32 flags; > > >>>> This seems unused ... please introduce them when/if you start > > >>>> using > > >> them. > > >>> > > >>> Will fix in v2. > > >>> > > >>>>> +}; > > >>>>> + > > >>>>> +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, > > >>>>> + struct fpga_image_info *info, > > >>>>> + const char *buf, size_t size) { > > >>>>> + struct versal_fpga_priv *priv; > > >>>>> + > > >>>>> + priv =3D mgr->priv; > > >>>>> + priv->flags =3D info->flags; > > >>>> ? What uses this ? It seems this function could just be 'return 0'= right > now. > > >>> > > >>> Will fix in v2. > > >>> > > >>>>> + > > >>>>> + return 0; > > >>>>> +} > > >>>>> + > > >>>>> +static int versal_fpga_ops_write(struct fpga_manager *mgr, > > >>>>> + const char *buf, size_t size) { > > >>>>> + struct versal_fpga_priv *priv; > > >>>>> + dma_addr_t dma_addr =3D 0; > > >>>>> + char *kbuf; > > >>>>> + int ret; > > >>>>> + > > >>>>> + priv =3D mgr->priv; > > >>>>> + > > >>>>> + kbuf =3D dma_alloc_coherent(priv->dev, size, &dma_addr, > > >>>> GFP_KERNEL); > > >>>>> + if (!kbuf) > > >>>>> + return -ENOMEM; > > >>>>> + > > >>>>> + memcpy(kbuf, buf, size); > > >>>>> + > > >>>>> + wmb(); /* ensure all writes are done before initiate FW call > > >>>>> +*/ > > >>>>> + > > >>>>> + ret =3D zynqmp_pm_load_pdi(PDI_SOURCE_TYPE, dma_addr); > > >>>>> + > > >>>>> + dma_free_coherent(priv->dev, size, kbuf, dma_addr); > > >>>>> + > > >>>>> + return ret; > > >>>>> +} > > >>>>> + > > >>>>> +static int versal_fpga_ops_write_complete(struct fpga_manager > *mgr, > > >>>>> + struct fpga_image_info > *info) { > > >>>>> + return 0; > > >>>>> +} > > >>>>> + > > >>>>> +static enum fpga_mgr_states versal_fpga_ops_state(struct > > >>>>> +fpga_manager > > >>>>> +*mgr) { > > >>>>> + return FPGA_MGR_STATE_OPERATING; > > >>>> Is that always the case? Shouldn't that be > > >> FPGA_MGR_STATE_UNKNOWN? > > >>> > > >>> For Versal SoC base PDI is always configured prior to Linux boot > > >>> up. So I > > >> make the fpga state as OPERATING. > > >>> Please let know if it is not a proper implementation will think > > >>> about the > > >> alternate solution. > > >> > > >> So you're saying I can't boot a Versal SoC without a PDI / Bitstream > loaded? > > >> Interesting :) > > >>> > > > > > > For Versal SoC Vivado generated base PDI is always needed to bring-up > the board. > > > > Look at PDI as ps7_init/psu_init file but in different format. And > > bitstream is optional part of it (like a one partition). >=20 > So at that point I could still have no bitstream loaded (optional), and m= y > status would be 'unknown' not 'operating' if I cannot tell the two cases = apart. > What am I missing? :) >=20 Agree, In few cases Bitstream partition is optional, So we can't say exactl= y whether the PL is having Bitstream or Not . So here the ideal default PL = state should be Unknown. Will fix in v2. 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, > -----Original Message----- > From: Moritz Fischer > Sent: Thursday, January 28, 2021 3:15 AM > To: Michal Simek > Cc: Nava kishore Manne ; Moritz Fischer > ; trix@redhat.com; robh+dt@kernel.org; linux- > fpga@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org; git > ; chinnikishore369@gmail.com; Appana Durga Kedareswara > Rao > Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager driver > > On Wed, Jan 27, 2021 at 10:16:32AM +0100, Michal Simek wrote: > > Hi > > > > On 1/27/21 9:57 AM, Nava kishore Manne wrote: > > > Hi Moritz, > > > > > > Please find my response inline. > > > > > >> -----Original Message----- > > >> From: Moritz Fischer > > >> Sent: Sunday, January 24, 2021 5:04 AM > > >> To: Nava kishore Manne > > >> Cc: Moritz Fischer ; trix@redhat.com; > > >> robh+dt@kernel.org; Michal Simek ; linux- > > >> fpga@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > > >> kernel@lists.infradead.org; linux-kernel@vger.kernel.org; git > > >> ; chinnikishore369@gmail.com; Appana Durga > > >> Kedareswara Rao > > >> Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga manager > > >> driver > > >> > > >> Hi Nava, > > >> > > >> On Fri, Jan 22, 2021 at 10:34:15AM +0000, Nava kishore Manne wrote: > > >>> Hi Moritz, > > >>> > > >>> Thanks for the review. > > >>> Please find my response inline. > > >>> > > >>>> -----Original Message----- > > >>>> From: Moritz Fischer > > >>>> Sent: Tuesday, January 19, 2021 6:03 AM > > >>>> To: Nava kishore Manne > > >>>> Cc: mdf@kernel.org; trix@redhat.com; robh+dt@kernel.org; Michal > > >>>> Simek ; linux-fpga@vger.kernel.org; > > >>>> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org; > > >>>> linux- kernel@vger.kernel.org; git ; > > >>>> chinnikishore369@gmail.com; Appana Durga Kedareswara Rao > > >>>> > > >>>> Subject: Re: [PATCH 3/3] fpga: versal-fpga: Add versal fpga > > >>>> manager driver > > >>>> > > >>>> Hi Nava, > > >>>> > > >>>> On Mon, Jan 18, 2021 at 08:13:18AM +0530, Nava kishore Manne > wrote: > > >>>>> This patch adds driver for versal fpga manager. > > >>>> Nit: Add support for Xilinx Versal FPGA manager > > >>> > > >>> Will fix in v2. > > >>> > > >>>>> > > >>>>> PDI source type can be DDR, OCM, QSPI flash etc.. > > >>>> No idea what PDI is :) > > >>> > > >>> Programmable device image (PDI). > > >>> This file is generated by Xilinx Vivado tool and it contains > > >>> configuration data > > >> objects. > > >>> > > >>>>> But driver allocates memory always from DDR, Since driver > > >>>>> supports only DDR source type. > > >>>>> > > >>>>> Signed-off-by: Appana Durga Kedareswara rao > > >>>>> > > >>>>> Signed-off-by: Nava kishore Manne > > >>>>> --- > > >>>>> drivers/fpga/Kconfig | 8 ++ > > >>>>> drivers/fpga/Makefile | 1 + > > >>>>> drivers/fpga/versal-fpga.c | 149 > > >>>>> +++++++++++++++++++++++++++++++++++++ > > >>>>> 3 files changed, 158 insertions(+) create mode 100644 > > >>>>> drivers/fpga/versal-fpga.c > > >>>>> > > >>>>> diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index > > >>>>> 5645226ca3ce..9f779c3a6739 100644 > > >>>>> --- a/drivers/fpga/Kconfig > > >>>>> +++ b/drivers/fpga/Kconfig > > >>>>> @@ -216,4 +216,12 @@ config FPGA_MGR_ZYNQMP_FPGA > > >>>>> to configure the programmable logic(PL) through PS > > >>>>> on ZynqMP SoC. > > >>>>> > > >>>>> +config FPGA_MGR_VERSAL_FPGA > > >>>>> + tristate "Xilinx Versal FPGA" > > >>>>> + depends on ARCH_ZYNQMP || COMPILE_TEST > > >>>>> + help > > >>>>> + Select this option to enable FPGA manager driver support for > > >>>>> + Xilinx Versal SOC. This driver uses the versal soc firmware > > >>>>> + interface to load programmable logic(PL) images > > >>>>> + on versal soc. > > >>>>> endif # FPGA > > >>>>> diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index > > >>>>> d8e21dfc6778..40c9adb6a644 100644 > > >>>>> --- a/drivers/fpga/Makefile > > >>>>> +++ b/drivers/fpga/Makefile > > >>>>> @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) > += > > >>>> ts73xx-fpga.o > > >>>>> obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > >>>>> obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > >>>>> obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > >>>>> +obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > >>>>> obj-$(CONFIG_ALTERA_PR_IP_CORE) += altera-pr-ip-core.o > > >>>>> obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT) += altera-pr-ip-core- > plat.o > > >>>>> > > >>>>> diff --git a/drivers/fpga/versal-fpga.c > > >>>>> b/drivers/fpga/versal-fpga.c new file mode 100644 index > > >>>>> 000000000000..2a42aa78b182 > > >>>>> --- /dev/null > > >>>>> +++ b/drivers/fpga/versal-fpga.c > > >>>>> @@ -0,0 +1,149 @@ > > >>>>> +// SPDX-License-Identifier: GPL-2.0+ > > >>>>> +/* > > >>>>> + * Copyright (C) 2021 Xilinx, Inc. > > >>>>> + */ > > >>>>> + > > >>>>> +#include > > >>>>> +#include #include #include > > >>>>> + #include #include > > >>>>> + #include #include > > >>>>> + > > >>>>> + > > >>>>> +/* Constant Definitions */ > > >>>>> +#define PDI_SOURCE_TYPE 0xF > > >>>>> + > > >>>>> +/** > > >>>>> + * struct versal_fpga_priv - Private data structure > > >>>>> + * @dev: Device data structure > > >>>>> + * @flags: flags which is used to identify the PL Image type > > >>>>> + */ > > >>>>> +struct versal_fpga_priv { > > >>>>> + struct device *dev; > > >>>>> + u32 flags; > > >>>> This seems unused ... please introduce them when/if you start > > >>>> using > > >> them. > > >>> > > >>> Will fix in v2. > > >>> > > >>>>> +}; > > >>>>> + > > >>>>> +static int versal_fpga_ops_write_init(struct fpga_manager *mgr, > > >>>>> + struct fpga_image_info *info, > > >>>>> + const char *buf, size_t size) { > > >>>>> + struct versal_fpga_priv *priv; > > >>>>> + > > >>>>> + priv = mgr->priv; > > >>>>> + priv->flags = info->flags; > > >>>> ? What uses this ? It seems this function could just be 'return 0' right > now. > > >>> > > >>> Will fix in v2. > > >>> > > >>>>> + > > >>>>> + return 0; > > >>>>> +} > > >>>>> + > > >>>>> +static int versal_fpga_ops_write(struct fpga_manager *mgr, > > >>>>> + const char *buf, size_t size) { > > >>>>> + struct versal_fpga_priv *priv; > > >>>>> + dma_addr_t dma_addr = 0; > > >>>>> + char *kbuf; > > >>>>> + int ret; > > >>>>> + > > >>>>> + priv = mgr->priv; > > >>>>> + > > >>>>> + kbuf = dma_alloc_coherent(priv->dev, size, &dma_addr, > > >>>> GFP_KERNEL); > > >>>>> + if (!kbuf) > > >>>>> + return -ENOMEM; > > >>>>> + > > >>>>> + memcpy(kbuf, buf, size); > > >>>>> + > > >>>>> + wmb(); /* ensure all writes are done before initiate FW call > > >>>>> +*/ > > >>>>> + > > >>>>> + ret = zynqmp_pm_load_pdi(PDI_SOURCE_TYPE, dma_addr); > > >>>>> + > > >>>>> + dma_free_coherent(priv->dev, size, kbuf, dma_addr); > > >>>>> + > > >>>>> + return ret; > > >>>>> +} > > >>>>> + > > >>>>> +static int versal_fpga_ops_write_complete(struct fpga_manager > *mgr, > > >>>>> + struct fpga_image_info > *info) { > > >>>>> + return 0; > > >>>>> +} > > >>>>> + > > >>>>> +static enum fpga_mgr_states versal_fpga_ops_state(struct > > >>>>> +fpga_manager > > >>>>> +*mgr) { > > >>>>> + return FPGA_MGR_STATE_OPERATING; > > >>>> Is that always the case? Shouldn't that be > > >> FPGA_MGR_STATE_UNKNOWN? > > >>> > > >>> For Versal SoC base PDI is always configured prior to Linux boot > > >>> up. So I > > >> make the fpga state as OPERATING. > > >>> Please let know if it is not a proper implementation will think > > >>> about the > > >> alternate solution. > > >> > > >> So you're saying I can't boot a Versal SoC without a PDI / Bitstream > loaded? > > >> Interesting :) > > >>> > > > > > > For Versal SoC Vivado generated base PDI is always needed to bring-up > the board. > > > > Look at PDI as ps7_init/psu_init file but in different format. And > > bitstream is optional part of it (like a one partition). > > So at that point I could still have no bitstream loaded (optional), and my > status would be 'unknown' not 'operating' if I cannot tell the two cases apart. > What am I missing? :) > Agree, In few cases Bitstream partition is optional, So we can't say exactly whether the PL is having Bitstream or Not . So here the ideal default PL state should be Unknown. Will fix in v2. Regards, Navakishore. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel