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Mon, 15 Jun 2020 01:22:37 +0000 From: "Tian, Kevin" To: "Liu, Yi L" , Alex Williamson CC: "eric.auger@redhat.com" , "baolu.lu@linux.intel.com" , "joro@8bytes.org" , "jacob.jun.pan@linux.intel.com" , "Raj, Ashok" , "Tian, Jun J" , "Sun, Yi Y" , "jean-philippe@linaro.org" , "peterx@redhat.com" , "Wu, Hao" , "iommu@lists.linux-foundation.org" , "kvm@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v2 02/15] iommu: Report domain nesting info Thread-Topic: [PATCH v2 02/15] iommu: Report domain nesting info Thread-Index: AQHWP+lAh6LCFwZsRk6rW47Mu2S6h6jTzaSAgADjv4CABDOwQA== Date: Mon, 15 Jun 2020 01:22:37 +0000 Message-ID: References: <1591877734-66527-1-git-send-email-yi.l.liu@intel.com> <1591877734-66527-3-git-send-email-yi.l.liu@intel.com> <20200611133015.1418097f@x1.home> In-Reply-To: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: dlp-version: 11.2.0.6 dlp-product: dlpe-windows dlp-reaction: no-action authentication-results: intel.com; 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x-ms-exchange-antispam-messagedata: dLqypIN2zn3cmuK9rT1twCa5/InKnha1h+vnNBAIgUpDh9vxXENcwQUVYon27rdipjl4AyzowoiOexqtjRmf9+V/xVdpyoAsuQQryGQGF1+GGtTW+E/aG2AClTOj+Rdnxgg25iIfI207+Ey4d1VxKJ595Fuqerzkp5BR/tNvvxwF06BS2/xhO2PIv8ysGDT796wcn4qbDUyB+aIXAaFyabJcK3kHVXR5fWDU5z57pqwEx2GDNVhVEt36zPaF/MRTOEUvtX2KKiueU7RatgTItebG/y1Qyh07fn6L+C8jHzAeh0a4h+o7gc0g6cTWvvY+kTmzy0xa/Y3DDxQBgiSPPekv1PjdxGBtlQonNYQcoPyKeJ7LRhW5kzBWxhf76m/kRLenQXoIb5Lnw2YuBMFQWrmYLwCeC0s1LaOI9jLm5Dd9Et9UCfqCTjCtXLp5U1pvX5CDQZ9kjVrv5CeDTiwkOR/MqN1ZvpIAb+THfobuJ5U= Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 82000480-8ea1-4b14-7ead-08d810ca96c4 X-MS-Exchange-CrossTenant-originalarrivaltime: 15 Jun 2020 01:22:37.0483 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vFMDjdpZxwijQ/eSzCgnOc2VgXwMjxBFo3L7Ftczk7pjF20NSCqRiYU64w/kykTWENk4okRSHgIxKspqQgMczA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MWHPR11MB0014 X-OriginatorOrg: intel.com Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > From: Liu, Yi L > Sent: Friday, June 12, 2020 5:05 PM >=20 > Hi Alex, >=20 > > From: Alex Williamson > > Sent: Friday, June 12, 2020 3:30 AM > > > > On Thu, 11 Jun 2020 05:15:21 -0700 > > Liu Yi L wrote: > > > > > IOMMUs that support nesting translation needs report the capability > > > info to userspace, e.g. the format of first level/stage paging struct= ures. > > > > > > Cc: Kevin Tian > > > CC: Jacob Pan > > > Cc: Alex Williamson > > > Cc: Eric Auger > > > Cc: Jean-Philippe Brucker > > > Cc: Joerg Roedel > > > Cc: Lu Baolu > > > Signed-off-by: Liu Yi L > > > Signed-off-by: Jacob Pan > > > --- > > > @Jean, Eric: as nesting was introduced for ARM, but looks like no > > > actual user of it. right? So I'm wondering if we can reuse > > > DOMAIN_ATTR_NESTING to retrieve nesting info? how about your > opinions? > > > > > > include/linux/iommu.h | 1 + > > > include/uapi/linux/iommu.h | 34 > ++++++++++++++++++++++++++++++++++ > > > 2 files changed, 35 insertions(+) > > > > > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h index > > > 78a26ae..f6e4b49 100644 > > > --- a/include/linux/iommu.h > > > +++ b/include/linux/iommu.h > > > @@ -126,6 +126,7 @@ enum iommu_attr { > > > DOMAIN_ATTR_FSL_PAMUV1, > > > DOMAIN_ATTR_NESTING, /* two stages of translation */ > > > DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, > > > + DOMAIN_ATTR_NESTING_INFO, > > > DOMAIN_ATTR_MAX, > > > }; > > > > > > diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h > > > index 303f148..02eac73 100644 > > > --- a/include/uapi/linux/iommu.h > > > +++ b/include/uapi/linux/iommu.h > > > @@ -332,4 +332,38 @@ struct iommu_gpasid_bind_data { > > > }; > > > }; > > > > > > +struct iommu_nesting_info { > > > + __u32 size; > > > + __u32 format; > > > + __u32 features; > > > +#define IOMMU_NESTING_FEAT_SYSWIDE_PASID (1 << 0) > > > +#define IOMMU_NESTING_FEAT_BIND_PGTBL (1 << 1) > > > +#define IOMMU_NESTING_FEAT_CACHE_INVLD (1 << 2) > > > + __u32 flags; > > > + __u8 data[]; > > > +}; > > > + > > > +/* > > > + * @flags: VT-d specific flags. Currently reserved for future > > > + * extension. > > > + * @addr_width: The output addr width of first level/stage translati= on > > > + * @pasid_bits: Maximum supported PASID bits, 0 represents no > PASID > > > + * support. > > > + * @cap_reg: Describe basic capabilities as defined in VT-d > capability > > > + * register. > > > + * @cap_mask: Mark valid capability bits in @cap_reg. > > > + * @ecap_reg: Describe the extended capabilities as defined in VT-d > > > + * extended capability register. > > > + * @ecap_mask: Mark the valid capability bits in @ecap_reg. > > > > Please explain this a little further, why do we need to tell userspace = about > > cap/ecap register bits that aren't valid through this interface? > > Thanks, >=20 > we only want to tell userspace about the bits marked in the cap/ecap_mask= . > cap/ecap_mask is kind of white-list of the cap/ecap register. userspace > should > only care about the bits in the white-list, for other bits, it should ign= ore. >=20 > Regards, > Yi Liu For invalid bits if kernel just clears them then do we still need additiona= l mask bits to explicitly mark them out? I guess this might be the point that= =20 Alex asked... >=20 > > Alex > > > > > > > + */ > > > +struct iommu_nesting_info_vtd { > > > + __u32 flags; > > > + __u16 addr_width; > > > + __u16 pasid_bits; > > > + __u64 cap_reg; > > > + __u64 cap_mask; > > > + __u64 ecap_reg; > > > + __u64 ecap_mask; > > > +}; > > > + > > > #endif /* _UAPI_IOMMU_H */ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD847C433E0 for ; Mon, 15 Jun 2020 01:22:44 +0000 (UTC) Received: from silver.osuosl.org (smtp3.osuosl.org [140.211.166.136]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4981920775 for ; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: iommu-bounces@lists.linux-foundation.org Sender: "iommu" > From: Liu, Yi L > Sent: Friday, June 12, 2020 5:05 PM > > Hi Alex, > > > From: Alex Williamson > > Sent: Friday, June 12, 2020 3:30 AM > > > > On Thu, 11 Jun 2020 05:15:21 -0700 > > Liu Yi L wrote: > > > > > IOMMUs that support nesting translation needs report the capability > > > info to userspace, e.g. the format of first level/stage paging structures. > > > > > > Cc: Kevin Tian > > > CC: Jacob Pan > > > Cc: Alex Williamson > > > Cc: Eric Auger > > > Cc: Jean-Philippe Brucker > > > Cc: Joerg Roedel > > > Cc: Lu Baolu > > > Signed-off-by: Liu Yi L > > > Signed-off-by: Jacob Pan > > > --- > > > @Jean, Eric: as nesting was introduced for ARM, but looks like no > > > actual user of it. right? So I'm wondering if we can reuse > > > DOMAIN_ATTR_NESTING to retrieve nesting info? how about your > opinions? > > > > > > include/linux/iommu.h | 1 + > > > include/uapi/linux/iommu.h | 34 > ++++++++++++++++++++++++++++++++++ > > > 2 files changed, 35 insertions(+) > > > > > > diff --git a/include/linux/iommu.h b/include/linux/iommu.h index > > > 78a26ae..f6e4b49 100644 > > > --- a/include/linux/iommu.h > > > +++ b/include/linux/iommu.h > > > @@ -126,6 +126,7 @@ enum iommu_attr { > > > DOMAIN_ATTR_FSL_PAMUV1, > > > DOMAIN_ATTR_NESTING, /* two stages of translation */ > > > DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE, > > > + DOMAIN_ATTR_NESTING_INFO, > > > DOMAIN_ATTR_MAX, > > > }; > > > > > > diff --git a/include/uapi/linux/iommu.h b/include/uapi/linux/iommu.h > > > index 303f148..02eac73 100644 > > > --- a/include/uapi/linux/iommu.h > > > +++ b/include/uapi/linux/iommu.h > > > @@ -332,4 +332,38 @@ struct iommu_gpasid_bind_data { > > > }; > > > }; > > > > > > +struct iommu_nesting_info { > > > + __u32 size; > > > + __u32 format; > > > + __u32 features; > > > +#define IOMMU_NESTING_FEAT_SYSWIDE_PASID (1 << 0) > > > +#define IOMMU_NESTING_FEAT_BIND_PGTBL (1 << 1) > > > +#define IOMMU_NESTING_FEAT_CACHE_INVLD (1 << 2) > > > + __u32 flags; > > > + __u8 data[]; > > > +}; > > > + > > > +/* > > > + * @flags: VT-d specific flags. Currently reserved for future > > > + * extension. > > > + * @addr_width: The output addr width of first level/stage translation > > > + * @pasid_bits: Maximum supported PASID bits, 0 represents no > PASID > > > + * support. > > > + * @cap_reg: Describe basic capabilities as defined in VT-d > capability > > > + * register. > > > + * @cap_mask: Mark valid capability bits in @cap_reg. > > > + * @ecap_reg: Describe the extended capabilities as defined in VT-d > > > + * extended capability register. > > > + * @ecap_mask: Mark the valid capability bits in @ecap_reg. > > > > Please explain this a little further, why do we need to tell userspace about > > cap/ecap register bits that aren't valid through this interface? > > Thanks, > > we only want to tell userspace about the bits marked in the cap/ecap_mask. > cap/ecap_mask is kind of white-list of the cap/ecap register. userspace > should > only care about the bits in the white-list, for other bits, it should ignore. > > Regards, > Yi Liu For invalid bits if kernel just clears them then do we still need additional mask bits to explicitly mark them out? I guess this might be the point that Alex asked... > > > Alex > > > > > > > + */ > > > +struct iommu_nesting_info_vtd { > > > + __u32 flags; > > > + __u16 addr_width; > > > + __u16 pasid_bits; > > > + __u64 cap_reg; > > > + __u64 cap_mask; > > > + __u64 ecap_reg; > > > + __u64 ecap_mask; > > > +}; > > > + > > > #endif /* _UAPI_IOMMU_H */ _______________________________________________ iommu mailing list iommu@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/iommu