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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Errors-To: amd-gfx-bounces@lists.freedesktop.org Sender: "amd-gfx" [AMD Official Use Only - Internal Distribution Only] Christian is right here, that will cause many problems for simply using VMI= D in kernel. We already have an pair interface for RGP, I think you can use it instead o= f involving additional kernel change. amdgpu_vm_reserve_vmid/ amdgpu_vm_unreserve_vmid. -David -----Original Message----- From: amd-gfx On Behalf Of Christia= n K=F6nig Sent: Wednesday, February 19, 2020 7:03 PM To: He, Jacob ; amd-gfx@lists.freedesktop.org Subject: Re: [PATCH] drm/amdgpu: Add a chunk ID for spm trace Am 19.02.20 um 11:15 schrieb Jacob He: > [WHY] > When SPM trace enabled, SPM_VMID should be updated with the current = > vmid. > > [HOW] > Add a chunk id, AMDGPU_CHUNK_ID_SPM_TRACE, so that UMD can tell us = > which job should update SPM_VMID. > Right before a job is submitted to GPU, set the SPM_VMID accordingly. > > [Limitation] > Running more than one SPM trace enabled processes simultaneously is = > not supported. Well there are multiple problems with that patch. First of all you need to better describe what SPM tracing is in the commit = message. Then the updating of mmRLC_SPM_MC_CNTL must be executed asynchronously on t= he ring. Otherwise we might corrupt an already executing SPM trace. And you also need to make sure to disable the tracing again or otherwise we= run into a bunch of trouble when the VMID is reused. You also need to make sure that IBs using the SPM trace are serialized with= each other, e.g. hack into amdgpu_ids.c file and make sure that only one V= MID at a time can have that attribute. Regards, Christian. > > Change-Id: Ic932ef6ac9dbf244f03aaee90550e8ff3a675666 > Signed-off-by: Jacob He > --- > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 7 +++++++ > drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c | 10 +++++++--- > drivers/gpu/drm/amd/amdgpu/amdgpu_job.h | 1 + > drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h | 1 + > drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 15 ++++++++++++++- > drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 3 ++- > drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 15 ++++++++++++++- > 8 files changed, 48 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c = > b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c > index f9fa6e104fef..3f32c4db5232 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c > @@ -113,6 +113,7 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_par= ser *p, union drm_amdgpu_cs > uint32_t uf_offset =3D 0; > int i; > int ret; > + bool update_spm_vmid =3D false; > = > if (cs->in.num_chunks =3D=3D 0) > return 0; > @@ -221,6 +222,10 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_pa= rser *p, union drm_amdgpu_cs > case AMDGPU_CHUNK_ID_SYNCOBJ_TIMELINE_SIGNAL: > break; > = > + case AMDGPU_CHUNK_ID_SPM_TRACE: > + update_spm_vmid =3D true; > + break; > + > default: > ret =3D -EINVAL; > goto free_partial_kdata; > @@ -231,6 +236,8 @@ static int amdgpu_cs_parser_init(struct amdgpu_cs_par= ser *p, union drm_amdgpu_cs > if (ret) > goto free_all_kdata; > = > + p->job->need_update_spm_vmid =3D update_spm_vmid; > + > if (p->ctx->vram_lost_counter !=3D p->job->vram_lost_counter) { > ret =3D -ECANCELED; > goto free_all_kdata; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c = > b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > index cae81914c821..36faab12b585 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c > @@ -156,9 +156,13 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, uns= igned num_ibs, > return -EINVAL; > } > = > - if (vm && !job->vmid) { > - dev_err(adev->dev, "VM IB without ID\n"); > - return -EINVAL; > + if (vm) { > + if (!job->vmid) { > + dev_err(adev->dev, "VM IB without ID\n"); > + return -EINVAL; > + } else if (adev->gfx.rlc.funcs->update_spm_vmid && job->need_update_sp= m_vmid) { > + adev->gfx.rlc.funcs->update_spm_vmid(adev, job->vmid); > + } > } > = > alloc_size =3D ring->funcs->emit_frame_size + num_ibs * diff --git = > a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h = > b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h > index 2e2110dddb76..4582536961c7 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.h > @@ -52,6 +52,7 @@ struct amdgpu_job { > bool vm_needs_flush; > uint64_t vm_pd_addr; > unsigned vmid; > + bool need_update_spm_vmid; > unsigned pasid; > uint32_t gds_base, gds_size; > uint32_t gws_base, gws_size; > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h = > b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h > index d3d4707f2168..52509c254cbd 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.h > @@ -126,6 +126,7 @@ struct amdgpu_rlc_funcs { > void (*stop)(struct amdgpu_device *adev); > void (*reset)(struct amdgpu_device *adev); > void (*start)(struct amdgpu_device *adev); > + void (*update_spm_vmid)(struct amdgpu_device *adev, unsigned vmid); > }; > = > struct amdgpu_rlc { > diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c = > b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > index 5e9fb0976c6c..91eb788d6229 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c > @@ -4214,6 +4214,18 @@ static int gfx_v10_0_update_gfx_clock_gating(struc= t amdgpu_device *adev, > return 0; > } > = > +static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, = > +unsigned vmid) { > + u32 data; > + > + data =3D RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); > + > + data &=3D ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; > + data |=3D (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << = > +RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; > + > + WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); } > + > static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs =3D { > .is_rlc_enabled =3D gfx_v10_0_is_rlc_enabled, > .set_safe_mode =3D gfx_v10_0_set_safe_mode, @@ -4224,7 +4236,8 @@ = > static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs =3D { > .resume =3D gfx_v10_0_rlc_resume, > .stop =3D gfx_v10_0_rlc_stop, > .reset =3D gfx_v10_0_rlc_reset, > - .start =3D gfx_v10_0_rlc_start > + .start =3D gfx_v10_0_rlc_start, > + .update_spm_vmid =3D gfx_v10_0_update_spm_vmid > }; > = > static int gfx_v10_0_set_powergating_state(void *handle, diff --git = > a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c = > b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > index 8f20a5dd44fe..b24fc55cf13a 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c > @@ -4221,7 +4221,8 @@ static const struct amdgpu_rlc_funcs gfx_v7_0_rlc_f= uncs =3D { > .resume =3D gfx_v7_0_rlc_resume, > .stop =3D gfx_v7_0_rlc_stop, > .reset =3D gfx_v7_0_rlc_reset, > - .start =3D gfx_v7_0_rlc_start > + .start =3D gfx_v7_0_rlc_start, > + .update_spm_vmid =3D NULL > }; > = > static int gfx_v7_0_early_init(void *handle) diff --git = > a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c = > b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > index fa245973de12..66640d2b6b37 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c > @@ -5600,7 +5600,8 @@ static const struct amdgpu_rlc_funcs iceland_rlc_fu= ncs =3D { > .resume =3D gfx_v8_0_rlc_resume, > .stop =3D gfx_v8_0_rlc_stop, > .reset =3D gfx_v8_0_rlc_reset, > - .start =3D gfx_v8_0_rlc_start > + .start =3D gfx_v8_0_rlc_start, > + .update_spm_vmid =3D NULL > }; > = > static void gfx_v8_0_update_medium_grain_clock_gating(struct = > amdgpu_device *adev, diff --git = > a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c = > b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > index 9b7ff783e9a5..df872f949f68 100644 > --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c > @@ -4704,6 +4704,18 @@ static int gfx_v9_0_update_gfx_clock_gating(struct= amdgpu_device *adev, > return 0; > } > = > +static void gfx_v9_0_update_spm_vmid(struct amdgpu_device *adev, = > +unsigned vmid) { > + u32 data; > + > + data =3D RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); > + > + data &=3D ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; > + data |=3D (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << = > +RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; > + > + WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); } > + > static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs =3D { > .is_rlc_enabled =3D gfx_v9_0_is_rlc_enabled, > .set_safe_mode =3D gfx_v9_0_set_safe_mode, @@ -4715,7 +4727,8 @@ = > static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs =3D { > .resume =3D gfx_v9_0_rlc_resume, > .stop =3D gfx_v9_0_rlc_stop, > .reset =3D gfx_v9_0_rlc_reset, > - .start =3D gfx_v9_0_rlc_start > + .start =3D gfx_v9_0_rlc_start, > + .update_spm_vmid =3D gfx_v9_0_update_spm_vmid > }; > = > static int gfx_v9_0_set_powergating_state(void *handle, _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://nam11.safelinks.protection.outlook.com/?url=3Dhttps%3A%2F%2Flists.f= reedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=3D02%7C01%7Cdavid1.z= hou%40amd.com%7C354be34ff18e4f424f6708d7b52b43b0%7C3dd8961fe4884e608e11a82d= 994e183d%7C0%7C0%7C637177069753914395&sdata=3D9rSL4kgPJweuZ4EJpdqtqTxyC= VGEkmsg6aUzbtvGFrs%3D&reserved=3D0 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx