From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Deucher, Alexander" Subject: RE: [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is needed Date: Wed, 28 Sep 2016 15:27:34 +0000 Message-ID: References: <1475051780-21634-1-git-send-email-Monk.Liu@amd.com>, <1475051780-21634-8-git-send-email-Monk.Liu@amd.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="===============0760195326==" Return-path: In-Reply-To: Content-Language: en-US List-Id: Discussion list for AMD gfx List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Sender: "amd-gfx" To: "StDenis, Tom" , "Liu, Monk" , "amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org" Cc: "Min, Frank" --===============0760195326== Content-Language: en-US Content-Type: multipart/alternative; boundary="_000_MWHPR12MB169469DF6CB1A70E185D0563F7CF0MWHPR12MB1694namp_" --_000_MWHPR12MB169469DF6CB1A70E185D0563F7CF0MWHPR12MB1694namp_ Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Worth a shot, but I doubt it. Wptr polling is only enabled if explicitly r= equested. I'm not sure if CP PG will work without doorbells since the door= bells are handled by the BIF and forwarded to the CP which should wake it i= f it's gated. Wptr polling may require CP PG be disabled or prevent it fro= m kicking in. Probably want to ask the CP team. Alex From: amd-gfx [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of S= tDenis, Tom Sent: Wednesday, September 28, 2016 9:41 AM To: Liu, Monk; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Min, Frank Subject: Re: [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is needed Hmm, I wonder if this fix CP power gating issues ... on Carrizo/Stoney... ________________________________ From: amd-gfx > on behalf of Monk Liu > Sent: Wednesday, September 28, 2016 04:36 To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org Cc: Min, Frank Subject: [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is needed From: Frank Min > for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling. Change-Id: I14477577ef50d1ac90ccc32d41819276811732b7 Signed-off-by: Frank Min > --- drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/am= dgpu/gfx_v8_0.c index 097108a..98ef1fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -4338,7 +4338,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_devic= e *adev) struct amdgpu_ring *ring; u32 tmp; u32 rb_bufsz; - u64 rb_addr, rptr_addr; + u64 rb_addr, rptr_addr, wptr_gpu_addr; int r; /* Set the write pointer delay */ @@ -4369,6 +4369,9 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_devic= e *adev) WREG32(mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr)); WREG32(mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & 0xFF); + wptr_gpu_addr =3D adev->wb.gpu_addr + (ring->wptr_offs * 4); + WREG32(mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr)); + WREG32(mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr)); mdelay(1); WREG32(mmCP_RB0_CNTL, tmp); -- 1.9.1 _______________________________________________ amd-gfx mailing list amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx amd-gfx Info Page - lists.freedesktop.org lists.freedesktop.org To see the collection of prior postings to the list, visit the amd-gfx Arch= ives. Using amd-gfx: To post a message to all the list members, send email = ... --_000_MWHPR12MB169469DF6CB1A70E185D0563F7CF0MWHPR12MB1694namp_ Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable

Worth a shot, but I doubt= it.  Wptr polling is only enabled if explicitly requested.  I'm = not sure if CP PG will work without doorbells since the doorbells are handled by the BIF and forwarded to the CP which should wake it if it'= s gated.  Wptr polling may require CP PG be disabled or prevent it fro= m kicking in.  Probably want to ask the CP team.

 <= /p>

Alex

 <= /p>

From: amd-gfx = [mailto:amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org] On Behalf Of StDenis, Tom
Sent: Wednesday, September 28, 2016 9:41 AM
To: Liu, Monk; amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: Min, Frank
Subject: Re: [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is nee= ded

 

Hmm, I wonder if this fix CP power gating issues ... on Carrizo/= Stoney...

 

From: amd-gfx <amd-gfx-bounces-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org> on behalf of Monk Liu <Monk.Liu@amd= .com>
Sent: Wednesday, September 28, 2016 04:36
To: amd-gfx@lists.f= reedesktop.org
Cc: Min, Frank
Subject: [PATCH 8/9] drm/amdgpu:wptr poll address of gfx8 is needed<= /span>

 

From: Frank Min <Frank.Min-5C7GfCeVMHo@public.gmane.org>

for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling.

Change-Id: I14477577ef50d1ac90ccc32d41819276811732b7
Signed-off-by: Frank Min <Frank.Min= @amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/am= dgpu/gfx_v8_0.c
index 097108a..98ef1fe 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4338,7 +4338,7 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_d= evice *adev)
         struct amdgpu_ring *ring;<= br>          u32 tmp;
         u32 rb_bufsz;
-       u64 rb_addr, rptr_addr;
+       u64 rb_addr, rptr_addr, wptr_gpu_= addr;
         int r;
 
         /* Set the write pointer d= elay */
@@ -4369,6 +4369,9 @@ static int gfx_v8_0_cp_gfx_resume(struct amdgpu_d= evice *adev)
         WREG32(mmCP_RB0_RPTR_ADDR,= lower_32_bits(rptr_addr));
         WREG32(mmCP_RB0_RPTR_ADDR_= HI, upper_32_bits(rptr_addr) & 0xFF);
 
+       wptr_gpu_addr =3D adev->wb.gpu= _addr + (ring->wptr_offs * 4);
+       WREG32(mmCP_RB_WPTR_POLL_ADDR_LO,= lower_32_bits(wptr_gpu_addr));
+       WREG32(mmCP_RB_WPTR_POLL_ADDR_HI,= upper_32_bits(wptr_gpu_addr));
         mdelay(1);
         WREG32(mmCP_RB0_CNTL, tmp)= ;
 
--
1.9.1

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To see the collection of prior postings to the list,= visit the amd-gfx Archives. Using amd-gfx: To post a message to all the list members, send email ...

 

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