From mboxrd@z Thu Jan  1 00:00:00 1970
From: Pragnesh Patel <pragnesh.patel@sifive.com>
Date: Mon, 11 May 2020 06:06:46 +0000
Subject: [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
In-Reply-To: <CAMty3ZAp8aCHXocq_vP9b=_xsHJEPrfHZwwOr1m-dYyvYWOB2w@mail.gmail.com>
References: <20200509143037.26009-1-pragnesh.patel@sifive.com>
 <20200509143037.26009-20-pragnesh.patel@sifive.com>
 <CAMty3ZAp8aCHXocq_vP9b=_xsHJEPrfHZwwOr1m-dYyvYWOB2w@mail.gmail.com>
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>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 10 May 2020 20:44
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin
>Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>Troy Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel
><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick Chen
><rick@andestech.com>
>Subject: Re: [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot
>
>[External Email] Do not click links or attachments unless you recognize the
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>
>On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com>
>wrote:
>>
>> Add L2 cache node to enable cache ways from U-Boot
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
>> ---
>>  arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++
>>  1 file changed, 4 insertions(+)
>>
>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-
>c000-u-boot.dtsi
>> index fc91a7c987..42e43522ed 100644
>> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> @@ -82,3 +82,7 @@
>>  &qspi2 {
>>         u-boot,dm-spl;
>>  };
>> +
>> +&l2cache {
>> +       status = "okay";
>> +};
>
>Squash with next commit.

Will update in v9.