From mboxrd@z Thu Jan 1 00:00:00 1970 From: Pragnesh Patel Date: Sun, 10 May 2020 06:35:20 +0000 Subject: [PATCH v8 06/21] sifive: fu540: add ddr driver In-Reply-To: References: <20200509143037.26009-1-pragnesh.patel@sifive.com> <20200509143037.26009-7-pragnesh.patel@sifive.com> Message-ID: List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi Giulio, >-----Original Message----- >From: Giulio Benetti >Sent: 10 May 2020 01:18 >To: Pragnesh Patel ; u-boot at lists.denx.de >Cc: atish.patra at wdc.com; palmerdabbelt at google.com; >bmeng.cn at gmail.com; Paul Walmsley ; >jagan at amarulasolutions.com; Troy Benjegerdes >; anup.patel at wdc.com; Sagar Kadam >; rick at andestech.com; Palmer Dabbelt >; Kever Yang ; Lokesh >Vutla ; YouMin Chen ; Kevin >Scholz >Subject: Re: [PATCH v8 06/21] sifive: fu540: add ddr driver > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >Hi Pragnesh, > >On 5/9/20 4:30 PM, Pragnesh Patel wrote: >> Add driver for fu540 to support ddr initialization in SPL. >> This driver is based on FSBL >> (https://github.com/sifive/freedom-u540-c000-bootloader.git) >> >> Signed-off-by: Pragnesh Patel >> Reviewed-by: Jagan Teki >> Reviewed-by: Bin Meng >> Tested-by: Bin Meng >> --- >> board/sifive/fu540/Kconfig | 2 + >> drivers/ram/Kconfig | 1 + >> drivers/ram/Makefile | 2 + >> drivers/ram/sifive/Kconfig | 13 + >> drivers/ram/sifive/Makefile | 6 + >> drivers/ram/sifive/sdram_fu540.c | 416 >+++++++++++++++++++++++++++++++ >> 6 files changed, 440 insertions(+) >> create mode 100644 drivers/ram/sifive/Kconfig >> create mode 100644 drivers/ram/sifive/Makefile >> create mode 100644 drivers/ram/sifive/sdram_fu540.c >> >> diff --git a/board/sifive/fu540/Kconfig b/board/sifive/fu540/Kconfig >> index 4330ac4491..d41c305227 100644 >> --- a/board/sifive/fu540/Kconfig >> +++ b/board/sifive/fu540/Kconfig >> @@ -19,6 +19,8 @@ config SYS_TEXT_BASE >> config BOARD_SPECIFIC_OPTIONS # dummy >> def_bool y >> select GENERIC_RISCV >> + select RAM >> + select SPL_RAM if SPL >> imply CMD_DHCP >> imply CMD_EXT2 >> imply CMD_EXT4 >> diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index >> 56fea7c94c..66074d1feb 100644 >> --- a/drivers/ram/Kconfig >> +++ b/drivers/ram/Kconfig >> @@ -75,3 +75,4 @@ config IMXRT_SDRAM >> >> source "drivers/ram/rockchip/Kconfig" >> source "drivers/ram/stm32mp1/Kconfig" >> +source "drivers/ram/sifive/Kconfig" >> diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile index >> 5c897410c6..769c9d6218 100644 >> --- a/drivers/ram/Makefile >> +++ b/drivers/ram/Makefile >> @@ -17,3 +17,5 @@ obj-$(CONFIG_ARCH_MEDIATEK) += mediatek/ >> obj-$(CONFIG_K3_J721E_DDRSS) += k3-j721e/ >> >> obj-$(CONFIG_IMXRT_SDRAM) += imxrt_sdram.o >> + >> +obj-$(CONFIG_RAM_SIFIVE) += sifive/ >> diff --git a/drivers/ram/sifive/Kconfig b/drivers/ram/sifive/Kconfig >> new file mode 100644 index 0000000000..6aca22ab2a >> --- /dev/null >> +++ b/drivers/ram/sifive/Kconfig >> @@ -0,0 +1,13 @@ >> +config RAM_SIFIVE >> + bool "Ram drivers support for SiFive SoCs" >> + depends on RAM && RISCV >> + default y >> + help >> + This enables support for ram drivers of SiFive SoCs. >> + >> +config SIFIVE_FU540_DDR >> + bool "SiFive FU540 DDR driver" >> + depends on RAM_SIFIVE >> + default y if TARGET_SIFIVE_FU540 >> + help >> + This enables DDR support for the platforms based on SiFive FU540 SoC. >> diff --git a/drivers/ram/sifive/Makefile b/drivers/ram/sifive/Makefile >> new file mode 100644 index 0000000000..0187805199 >> --- /dev/null >> +++ b/drivers/ram/sifive/Makefile >> @@ -0,0 +1,6 @@ >> +# SPDX-License-Identifier: GPL-2.0+ >> +# >> +# Copyright (c) 2020 SiFive, Inc >> +# >> + >> +obj-$(CONFIG_SIFIVE_FU540_DDR) += sdram_fu540.o > >if this is a ddr-only driver I would change the name to: >fu540_ddr.o (keeping fu540 as prefix like the others). > >> diff --git a/drivers/ram/sifive/sdram_fu540.c >> b/drivers/ram/sifive/sdram_fu540.c >> new file mode 100644 >> index 0000000000..419359ff3b >> --- /dev/null >> +++ b/drivers/ram/sifive/sdram_fu540.c >> @@ -0,0 +1,416 @@ >> +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause >> +/* >> + * (C) Copyright 2020 SiFive, Inc. >> + * >> + * Authors: >> + * Pragnesh Patel >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#define DENALI_CTL_0 0 >> +#define DENALI_CTL_21 21 >> +#define DENALI_CTL_120 120 >> +#define DENALI_CTL_132 132 >> +#define DENALI_CTL_136 136 >> +#define DENALI_CTL_170 170 >> +#define DENALI_CTL_181 181 >> +#define DENALI_CTL_182 182 >> +#define DENALI_CTL_184 184 >> +#define DENALI_CTL_208 208 >> +#define DENALI_CTL_209 209 >> +#define DENALI_CTL_210 210 >> +#define DENALI_CTL_212 212 >> +#define DENALI_CTL_214 214 >> +#define DENALI_CTL_216 216 >> +#define DENALI_CTL_224 224 >> +#define DENALI_CTL_225 225 >> +#define DENALI_CTL_260 260 >> + >> +#define DENALI_PHY_1152 1152 >> +#define DENALI_PHY_1214 1214 >> + >> +#define PAYLOAD_DEST 0x80000000 >> +#define DDR_MEM_SIZE (8UL * 1024UL * 1024UL * 1024UL) >> + >> +#define DRAM_CLASS_OFFSET 8 >> +#define DRAM_CLASS_DDR4 0xA >> +#define OPTIMAL_RMODW_EN_OFFSET 0 >> +#define DISABLE_RD_INTERLEAVE_OFFSET 16 >> +#define OUT_OF_RANGE_OFFSET 1 >> +#define MULTIPLE_OUT_OF_RANGE_OFFSET 2 >> +#define PORT_COMMAND_CHANNEL_ERROR_OFFSET 7 >> +#define MC_INIT_COMPLETE_OFFSET 8 >> +#define LEVELING_OPERATION_COMPLETED_OFFSET 22 >> +#define DFI_PHY_WRLELV_MODE_OFFSET 24 >> +#define DFI_PHY_RDLVL_MODE_OFFSET 24 >> +#define DFI_PHY_RDLVL_GATE_MODE_OFFSET 0 >> +#define VREF_EN_OFFSET 24 >> +#define PORT_ADDR_PROTECTION_EN_OFFSET 0 >> +#define AXI0_ADDRESS_RANGE_ENABLE 8 >> +#define AXI0_RANGE_PROT_BITS_0_OFFSET 24 >> +#define RDLVL_EN_OFFSET 16 >> +#define RDLVL_GATE_EN_OFFSET 24 >> +#define WRLVL_EN_OFFSET 0 >> + >> +#define PHY_RX_CAL_DQ0_0_OFFSET 0 >> +#define PHY_RX_CAL_DQ1_0_OFFSET 16 >> + >> +struct fu540_ddrctl { >> + volatile u32 denali_ctl[265]; >> +}; >> + >> +struct fu540_ddrphy { >> + volatile u32 denali_phy[1215]; >> +}; >> + >> +/** >> + * struct ddr_info >> + * >> + * @dev : pointer for the device >> + * @info : UCLASS RAM information >> + * @ctl : DDR controller base address >> + * @phy : DDR PHY base address >> + * @ctrl : DDR control base address >> + * @physical_filter_ctrl : DDR physical filter control base address >> + */ >> +struct ddr_info { > >this should be 'struct fu540_ddr_info' > >> + struct udevice *dev; >> + struct ram_info info; >> + struct fu540_ddrctl *ctl; >> + struct fu540_ddrphy *phy; >> + struct clk ddr_clk; >> + u32 *physical_filter_ctrl; >> +}; >> + >> +#if defined(CONFIG_TPL_BUILD) || \ >> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) >> + >> +struct fu540_sdram_params { > >this should be fu540_ddr_params > >> + struct fu540_ddrctl pctl_regs; >> + struct fu540_ddrphy phy_regs; >> +}; >> + >> +struct sifive_dmc_plat { >> +#if CONFIG_IS_ENABLED(OF_PLATDATA) >> + struct dtd_sifive_fu540_dmc dtplat; #else >> + struct fu540_sdram_params sdram_params; #endif }; >> + >> +/* >> + * TODO : It can be possible to use common sdram_copy_to_reg() API >> + * n: Unit bytes >> + */ >> +static void sdram_copy_to_reg(volatile u32 *dest, >> + volatile u32 *src, u32 n) > >if you mean to use local function then think about changing its name to: >fu540_ddr_sdram_copy_to_reg(...) > >> +{ >> + int i; >> + >> + for (i = 0; i < n / sizeof(u32); i++) { >> + writel(*src, dest); >> + src++; >> + dest++; >> + } >> +} >> + >> +static void ddr_setuprangeprotection(volatile u32 *ctl, u64 end_addr) > >this should be 'fu540_ddr_setup_range_protection(...)' > >> +{ >> + u32 end_addr_16kblocks = ((end_addr >> 14) & 0x7FFFFF) - 1; >> + >> + writel(0x0, DENALI_CTL_209 + ctl); >> + writel(end_addr_16kblocks, DENALI_CTL_210 + ctl); >> + writel(0x0, DENALI_CTL_212 + ctl); >> + writel(0x0, DENALI_CTL_214 + ctl); >> + writel(0x0, DENALI_CTL_216 + ctl); >> + setbits_le32(DENALI_CTL_224 + ctl, >> + 0x3 << AXI0_RANGE_PROT_BITS_0_OFFSET); >> + writel(0xFFFFFFFF, DENALI_CTL_225 + ctl); >> + setbits_le32(DENALI_CTL_208 + ctl, 0x1 << >AXI0_ADDRESS_RANGE_ENABLE); >> + setbits_le32(DENALI_CTL_208 + ctl, >> + 0x1 << PORT_ADDR_PROTECTION_EN_OFFSET); } >> + >> +static void ddr_start(volatile u32 *ctl, u32 *physical_filter_ctrl, >> +u64 ddr_end) > >fu540_ddr_start(...) > >> +{ >> + volatile u64 *filterreg = (volatile u64 *)physical_filter_ctrl; >> + >> + setbits_le32(DENALI_CTL_0 + ctl, 0x1); >> + >> + wait_for_bit_le32((void *)ctl + DENALI_CTL_132, >> + BIT(MC_INIT_COMPLETE_OFFSET), false, 100, >> + false); >> + >> + /* Disable the BusBlocker in front of the controller AXI slave ports */ >> + filterreg[0] = 0x0f00000000000000UL | (ddr_end >> 2); } >> + >> +static void check_errata(u32 regbase, u32 updownreg) > >fu540_ddr_check_errata(...) > >> +{ >> + u64 fails = 0; >> + u32 dq = 0; >> + u32 down, up; >> + u8 failc0, failc1; >> + u32 phy_rx_cal_dqn_0_offset; >> + >> + for (u32 bit = 0; bit < 2; bit++) { >> + if (bit == 0) { >> + phy_rx_cal_dqn_0_offset = >> + PHY_RX_CAL_DQ0_0_OFFSET; >> + } else { >> + phy_rx_cal_dqn_0_offset = >> + PHY_RX_CAL_DQ1_0_OFFSET; >> + } >> + >> + down = (updownreg >> >> + phy_rx_cal_dqn_0_offset) & 0x3F; >> + up = (updownreg >> >> + (phy_rx_cal_dqn_0_offset + 6)) & >> + 0x3F; >> + >> + failc0 = ((down == 0) && (up == 0x3F)); >> + failc1 = ((up == 0) && (down == 0x3F)); >> + >> + /* print error message on failure */ >> + if (failc0 || failc1) { >> + if (fails == 0) >> + printf("DDR error in fixing up\n"); >> + >> + fails |= (1 << dq); >> + >> + char slicelsc = '0'; >> + char slicemsc = '0'; >> + >> + slicelsc += (dq % 10); >> + slicemsc += (dq / 10); >> + printf("S "); >> + printf("%c", slicemsc); >> + printf("%c", slicelsc); >> + >> + if (failc0) >> + printf("U"); >> + else >> + printf("D"); >> + >> + printf("\n"); >> + } >> + dq++; >> + } >> +} >> + >> +static u64 ddr_phy_fixup(volatile u32 *ddrphyreg) > >fu540_ddr_fixup(...) > >> +{ >> + u32 slicebase = 0; >> + >> + /* check errata condition */ >> + for (u32 slice = 0; slice < 8; slice++) { >> + u32 regbase = slicebase + 34; >> + >> + for (u32 reg = 0; reg < 4; reg++) { >> + u32 updownreg = readl(regbase + reg + >> + ddrphyreg); >> + >> + check_errata(regbase, updownreg); >> + } >> + slicebase += 128; >> + } >> + >> + return(0); >> +} >> + >> +static u32 ddr_getdramclass(volatile u32 *ctl) > >fu540_ddr_get_dram_class(...) > >> +{ >> + u32 reg = readl(DENALI_CTL_0 + ctl); >> + >> + return ((reg >> DRAM_CLASS_OFFSET) & 0xF); } >> + >> +static int fu540_ddr_setup(struct udevice *dev) { >> + struct ddr_info *priv = dev_get_priv(dev); >> + struct sifive_dmc_plat *plat = dev_get_platdata(dev); >> + struct fu540_sdram_params *params = &plat->sdram_params; >> + int ret, i; >> + u32 physet; >> + const u64 ddr_size = DDR_MEM_SIZE; >> + const u64 ddr_end = PAYLOAD_DEST + ddr_size; >> + volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0]; >> + volatile u32 *denali_phy = &priv->phy->denali_phy[0]; > >would this 2 last be ok with: >volatile u32 *denali_ctl = priv->ctl->denali_ctl; volatile u32 *denali_phy = >priv->phy->denali_phy; ? > >an maybe leaving shorter declarations as last ones i.e.: > struct ddr_info *priv = dev_get_priv(dev); > struct sifive_dmc_plat *plat = dev_get_platdata(dev); > struct fu540_sdram_params *params = &plat->sdram_params; > volatile u32 *denali_ctl = &priv->ctl->denali_ctl[0]; > volatile u32 *denali_phy = &priv->phy->denali_phy[0]; > const u64 ddr_size = DDR_MEM_SIZE; > const u64 ddr_end = PAYLOAD_DEST + ddr_size; > int ret, i; > u32 physet; Will update in v9. > >> + >> + ret = dev_read_u32_array(dev, "sifive,sdram-params", >> + (u32 *)&plat->sdram_params, >> + sizeof(plat->sdram_params) / sizeof(u32)); >> + if (ret) { >> + printf("%s: Cannot read sifive,sdram-params %d\n", >> + __func__, ret); >> + return ret; >> + } >> + >> + sdram_copy_to_reg(&priv->ctl->denali_ctl[0], >> + ¶ms->pctl_regs.denali_ctl[0], >> + sizeof(struct fu540_ddrctl)); >> + >> + /* phy reset */ >> + for (i = DENALI_PHY_1152; i <= DENALI_PHY_1214; i++) { >> + physet = params->phy_regs.denali_phy[i]; >> + priv->phy->denali_phy[i] = physet; >> + } >> + >> + for (i = 0; i < DENALI_PHY_1152; i++) { >> + physet = params->phy_regs.denali_phy[i]; >> + priv->phy->denali_phy[i] = physet; >> + } >> + >> + /* Disable read interleave DENALI_CTL_120 */ >> + setbits_le32(DENALI_CTL_120 + denali_ctl, >> + 1 << DISABLE_RD_INTERLEAVE_OFFSET); >> + >> + /* Disable optimal read/modify/write logic DENALI_CTL_21 */ >> + clrbits_le32(DENALI_CTL_21 + denali_ctl, 1 << >> + OPTIMAL_RMODW_EN_OFFSET); >> + >> + /* Enable write Leveling DENALI_CTL_170 */ >> + setbits_le32(DENALI_CTL_170 + denali_ctl, (1 << WRLVL_EN_OFFSET) >> + | (1 << DFI_PHY_WRLELV_MODE_OFFSET)); >> + >> + /* Enable read leveling DENALI_CTL_181 and DENALI_CTL_260 */ >> + setbits_le32(DENALI_CTL_181 + denali_ctl, >> + 1 << DFI_PHY_RDLVL_MODE_OFFSET); >> + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << RDLVL_EN_OFFSET); >> + >> + /* Enable read leveling gate DENALI_CTL_260 and DENALI_CTL_182 */ >> + setbits_le32(DENALI_CTL_260 + denali_ctl, 1 << >RDLVL_GATE_EN_OFFSET); >> + setbits_le32(DENALI_CTL_182 + denali_ctl, >> + 1 << DFI_PHY_RDLVL_GATE_MODE_OFFSET); >> + >> + if (ddr_getdramclass(denali_ctl) == DRAM_CLASS_DDR4) { >> + /* Enable vref training DENALI_CTL_184 */ >> + setbits_le32(DENALI_CTL_184 + denali_ctl, 1 << VREF_EN_OFFSET); >> + } >> + >> + /* Mask off leveling completion interrupt DENALI_CTL_136 */ >> + setbits_le32(DENALI_CTL_136 + denali_ctl, >> + 1 << LEVELING_OPERATION_COMPLETED_OFFSET); >> + >> + /* Mask off MC init complete interrupt DENALI_CTL_136 */ >> + setbits_le32(DENALI_CTL_136 + denali_ctl, 1 << >> + MC_INIT_COMPLETE_OFFSET); >> + >> + /* Mask off out of range interrupts DENALI_CTL_136 */ >> + setbits_le32(DENALI_CTL_136 + denali_ctl, (1 << >OUT_OF_RANGE_OFFSET) >> + | (1 << MULTIPLE_OUT_OF_RANGE_OFFSET)); >> + >> + /* set up range protection */ >> + ddr_setuprangeprotection(denali_ctl, DDR_MEM_SIZE); >> + >> + /* Mask off port command error interrupt DENALI_CTL_136 */ >> + setbits_le32(DENALI_CTL_136 + denali_ctl, >> + 1 << PORT_COMMAND_CHANNEL_ERROR_OFFSET); >> + >> + ddr_start(denali_ctl, priv->physical_filter_ctrl, ddr_end); >> + >> + ddr_phy_fixup(denali_phy); >> + >> + /* check size */ >> + priv->info.size = get_ram_size((long *)priv->info.base, >> + DDR_MEM_SIZE); >> + >> + debug("%s : %lx\n", __func__, priv->info.size); >> + >> + /* check memory access for all memory */ >> + if (priv->info.size != DDR_MEM_SIZE) { >> + printf("DDR invalid size : 0x%lx, expected 0x%lx\n", >> + priv->info.size, DDR_MEM_SIZE); >> + return -EINVAL; >> + } >> + >> + return 0; >> +} >> +#endif >> + >> +static int fu540_ddr_probe(struct udevice *dev) { >> + struct ddr_info *priv = dev_get_priv(dev); >> + >> +#if defined(CONFIG_TPL_BUILD) || \ >> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) >> + struct regmap *map; >> + int ret; >> + u32 clock = 0; >> + >> + debug("FU540 DDR probe\n"); >> + priv->dev = dev; >> + >> + ret = regmap_init_mem(dev_ofnode(dev), &map); >> + if (ret) >> + return ret; >> + >> + ret = clk_get_by_index(dev, 0, &priv->ddr_clk); >> + if (ret) { >> + debug("clk get failed %d\n", ret); >> + return ret; >> + } >> + >> + ret = dev_read_u32(dev, "clock-frequency", &clock); >> + if (ret) { >> + debug("clock-frequency not found in dt %d\n", ret); >> + return ret; >> + } else { >> + ret = clk_set_rate(&priv->ddr_clk, clock); >> + if (ret < 0) { >> + debug("Could not set DDR clock\n"); >> + return ret; >> + } >> + } >> + >> + ret = clk_enable(&priv->ddr_clk); >> + priv->ctl = regmap_get_range(map, 0); >> + priv->phy = regmap_get_range(map, 1); >> + priv->physical_filter_ctrl = regmap_get_range(map, 2); >> + >> + priv->info.base = CONFIG_SYS_SDRAM_BASE; >> + >> + priv->info.size = 0; >> + return fu540_ddr_setup(dev); >> +#else >> + priv->info.base = CONFIG_SYS_SDRAM_BASE; >> + priv->info.size = DDR_MEM_SIZE; >> +#endif >> + return 0; >> +} >> + >> +static int fu540_ddr_get_info(struct udevice *dev, struct ram_info >> +*info) { >> + struct ddr_info *priv = dev_get_priv(dev); >> + >> + *info = priv->info; >> + >> + return 0; >> +} >> + >> +static struct ram_ops fu540_ddr_ops = { >> + .get_info = fu540_ddr_get_info, >> +}; >> + >> +static const struct udevice_id fu540_ddr_ids[] = { >> + { .compatible = "sifive,fu540-c000-ddr" }, >> + { } >> +}; >> + >> +U_BOOT_DRIVER(fu540_ddr) = { >> + .name = "fu540_ddr", >> + .id = UCLASS_RAM, >> + .of_match = fu540_ddr_ids, >> + .ops = &fu540_ddr_ops, >> + .probe = fu540_ddr_probe, >> + .priv_auto_alloc_size = sizeof(struct ddr_info), #if >> +defined(CONFIG_TPL_BUILD) || \ >> + (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD)) >> + .platdata_auto_alloc_size = sizeof(struct sifive_dmc_plat), >> +#endif }; >> > >Best regards >-- >Giulio Benetti >Benetti Engineering sas