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From: Pragnesh Patel <pragnesh.patel@sifive.com>
To: u-boot@lists.denx.de
Subject: [PATCH v5 02/14] riscv: sifive: fu540: Use OTP DM driver for serial environment variable
Date: Tue, 17 Mar 2020 17:36:18 +0000	[thread overview]
Message-ID: <MWHPR13MB09449657FF3D59E008D3DCFBE5F60@MWHPR13MB0944.namprd13.prod.outlook.com> (raw)
In-Reply-To: <CAEUhbmUMS4+SkSf6a18_BQyDN9=kruwZeoLtEkWs5M78ZKE_UQ@mail.gmail.com>

Hi Bin,

>-----Original Message-----
>From: Bin Meng <bmeng.cn@gmail.com>
>Sent: 11 March 2020 20:30
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot Mailing List <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Paul
>Walmsley <paul.walmsley@sifive.com>; Jagan Teki
><jagan@amarulasolutions.com>; Troy Benjegerdes
><troy.benjegerdes@sifive.com>; Anup Patel <anup.patel@wdc.com>; Sagar
>Kadam <sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Palmer
>Dabbelt <palmer@dabbelt.com>
>Subject: Re: [PATCH v5 02/14] riscv: sifive: fu540: Use OTP DM driver for serial
>environment variable
>
>On Wed, Mar 11, 2020 at 3:03 PM Pragnesh Patel
><pragnesh.patel@sifive.com> wrote:
>>
>> Use the OTP DM driver to set the serial environment variable.
>>
>> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com>
>> ---
>>  arch/riscv/dts/fu540-c000-u-boot.dtsi         |  14 +++
>>  .../dts/hifive-unleashed-a00-u-boot.dtsi      |   6 +
>>  board/sifive/fu540/Kconfig                    |   2 +
>>  board/sifive/fu540/fu540.c                    | 113 +++++++-----------
>>  4 files changed, 62 insertions(+), 73 deletions(-)  create mode
>> 100644 arch/riscv/dts/fu540-c000-u-boot.dtsi
>>  create mode 100644 arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>>
>> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..31fd113c7d
>> --- /dev/null
>> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi
>> @@ -0,0 +1,14 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>
>Missed one thing:
>
>I believe this file should be dual-licensed, like fu540-c000.dtsi

Yes, will update in v6.

>
>> +/*
>> + * (C) Copyright 2019 SiFive, Inc
>> + */
>> +
>> +/ {
>> +       soc {
>> +               otp: otp at 10070000 {
>> +                       compatible = "sifive,fu540-otp";
>> +                       reg = <0x0 0x10070000 0x0 0x0FFF>;
>> +                       fuse-count = <0x1000>;
>> +               };
>> +       };
>> +};
>> diff --git a/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> new file mode 100644
>> index 0000000000..bec0d19134
>> --- /dev/null
>> +++ b/arch/riscv/dts/hifive-unleashed-a00-u-boot.dtsi
>> @@ -0,0 +1,6 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>
>And this one dual-licensed too

Will update.

>
>> +/*
>> + * Copyright (C) 2019 SiFive, Inc
>> + */
>> +
>
>Regards,
>Bin

  reply	other threads:[~2020-03-17 17:36 UTC|newest]

Thread overview: 53+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-11  7:03 [PATCH v5 00/14] RISC-V SiFive FU540 support SPL Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 01/14] misc: add driver for the SiFive otp controller Pragnesh Patel
2020-03-11 10:25   ` Bin Meng
2020-03-17 17:30     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 02/14] riscv: sifive: fu540: Use OTP DM driver for serial environment variable Pragnesh Patel
2020-03-11 13:32   ` Bin Meng
2020-03-11 14:52     ` Bin Meng
2020-03-17 15:45       ` Pragnesh Patel
2020-03-11 15:00   ` Bin Meng
2020-03-17 17:36     ` Pragnesh Patel [this message]
2020-03-11  7:03 ` [PATCH v5 03/14] riscv: Add _image_binary_end for SPL Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 04/14] lib: Makefile: build crc7.c when CONFIG_MMC_SPI Pragnesh Patel
2020-03-11 13:52   ` Bin Meng
2020-03-17 16:47     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 05/14] riscv: sifive: dts: fu540: Add board -u-boot.dtsi files Pragnesh Patel
2020-03-11 14:51   ` Bin Meng
2020-03-17 16:44     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 06/14] sifive: fu540: add ddr driver Pragnesh Patel
2020-03-13  7:48   ` Bin Meng
2020-03-17 13:00     ` Pragnesh Patel
2020-03-13 11:56   ` Giulio Benetti
2020-03-17 13:05     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 07/14] sifive: dts: fu540: Add DDR controller and phy register settings Pragnesh Patel
2020-03-13  7:51   ` Bin Meng
2020-03-17 15:35     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 08/14] clk: sifive: fu540-prci: Add clock enable and disable ops Pragnesh Patel
2020-03-13  7:57   ` Bin Meng
2020-03-13  8:15     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 09/14] clk: sifive: fu540-prci: Add clock initialization for SPL Pragnesh Patel
2020-03-13  8:11   ` Bin Meng
2020-03-17 17:47     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 10/14] riscv: sifive: fu540: add SPL configuration Pragnesh Patel
2020-03-13  8:28   ` Bin Meng
2020-03-17  7:41     ` Pragnesh Patel
2020-03-13 13:59   ` Bin Meng
2020-03-17  8:04     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 11/14] configs: fu540: Add config options for U-boot SPL Pragnesh Patel
2020-03-13  8:48   ` Bin Meng
2020-03-17 14:45     ` Pragnesh Patel
2020-03-11  7:03 ` [PATCH v5 12/14] riscv: sifive: fu540: enable all cache ways from u-boot proper Pragnesh Patel
2020-03-13  9:01   ` Bin Meng
2020-03-13 10:02     ` Anup Patel
2020-03-13 10:22       ` Bin Meng
2020-03-13 10:49         ` Anup Patel
2020-03-13 13:49           ` Bin Meng
2020-03-17  9:52             ` Pragnesh Patel
     [not found]               ` <752D002CFF5D0F4FA35C0100F1D73F3FA46E7F97@ATCPCS16.andestech.com>
2020-03-18  2:27                 ` Rick Chen
2020-03-13 10:54         ` Anup Patel
2020-03-11  7:03 ` [PATCH v5 13/14] sifive: fix palmer's email address Pragnesh Patel
2020-03-13  9:01   ` Bin Meng
2020-03-11  7:03 ` [PATCH v5 14/14] doc: update FU540 RISC-V documentation Pragnesh Patel
2020-03-13  9:22   ` Bin Meng
2020-03-17 14:31     ` Pragnesh Patel

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