From mboxrd@z Thu Jan  1 00:00:00 1970
From: Pragnesh Patel <pragnesh.patel@sifive.com>
Date: Wed, 13 May 2020 08:02:43 +0000
Subject: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock
 reset
In-Reply-To: <CAMty3ZC1v2F7QjOge9omEt5yg6JZVL2Au0CdAdsoRA0wcvb7-w@mail.gmail.com>
References: <20200513062617.19988-1-pragnesh.patel@sifive.com>
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>-----Original Message-----
>From: Jagan Teki <jagan@amarulasolutions.com>
>Sent: 13 May 2020 13:30
>To: Pragnesh Patel <pragnesh.patel@sifive.com>
>Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin
>Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>;
>Anup Patel <anup.patel@wdc.com>; Sagar Kadam
><sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Lukasz
>Majewski <lukma@denx.de>; Anatolij Gustschin <agust@denx.de>; Simon
>Glass <sjg@chromium.org>
>Subject: Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock
>reset
>
>[External Email] Do not click links or attachments unless you recognize the
>sender and know the content is safe
>
>On Wed, May 13, 2020 at 12:48 PM Pragnesh Patel
><pragnesh.patel@sifive.com> wrote:
>>
>> Hi Jagan,
>>
>> >-----Original Message-----
>> >From: Jagan Teki <jagan@amarulasolutions.com>
>> >Sent: 13 May 2020 12:21
>> >To: Pragnesh Patel <pragnesh.patel@sifive.com>
>> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra
>> ><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>;
>Bin
>> >Meng <bmeng.cn@gmail.com>; Paul Walmsley
><paul.walmsley@sifive.com>;
>> >Anup Patel <anup.patel@wdc.com>; Sagar Kadam
>> ><sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Lukasz
>> >Majewski <lukma@denx.de>; Anatolij Gustschin <agust@denx.de>; Simon
>> >Glass <sjg@chromium.org>
>> >Subject: Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release
>> >ethernet clock reset
>> >
>> >[External Email] Do not click links or attachments unless you
>> >recognize the sender and know the content is safe
>> >
>> >On Wed, May 13, 2020 at 11:57 AM Pragnesh Patel
>> ><pragnesh.patel@sifive.com> wrote:
>> >>
>> >> Release ethernet clock reset
>> >
>> >Please add a detailed commit message of why the ethernet clock is
>> >resetting in SPL code since ethernet won't need for SPL at all?
>>
>> Once the ethernet clock has been initialized ( set_rate() and
>> clk_enable() ), we need to take ethernet clock out of reset.
>>
>> This patch is necessary in this series otherwise U-Boot cannot use
>> ethernet and not able To boot.
>>
>> This ethernet reset __prci_ethernet_release_reset() is not depend on SPL or
>U-Boot proper.
>> Right now, U-Boot proper is using ethernet so this gets called only
>> for U-Boot proper and if SPL wants to use ethernet then function helps to
>take clock out of reset.
>
>But will __prci_ethernet_release_reset is called in SPL?

Right now no but if SPL wants to use ethernet in future then this function gets called.