From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.6 required=3.0 tests=BAYES_00, CHARSET_FARAWAY_HEADER,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59536C48BDF for ; Mon, 21 Jun 2021 01:59:56 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0A05B6112D for ; Mon, 21 Jun 2021 01:59:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0A05B6112D Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=mxic.com.tw Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 61D538291E; Mon, 21 Jun 2021 03:59:52 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=mxic.com.tw Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de Received: by phobos.denx.de (Postfix, from userid 109) id B73E48291E; Mon, 21 Jun 2021 03:59:50 +0200 (CEST) Received: from TWHMLLG3.macronix.com (twhmllg3.macronix.com [211.75.127.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 0F142801FD for ; Mon, 21 Jun 2021 03:59:44 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=mxic.com.tw Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=jaimeliao@mxic.com.tw Received: from twhfmlp1.macronix.com (twhfmlp1.macronix.com [172.17.20.91]) by TWHMLLG3.macronix.com with ESMTP id 15L1xTlb048769; Mon, 21 Jun 2021 09:59:29 +0800 (GMT-8) (envelope-from jaimeliao@mxic.com.tw) Received: from MXML06C.mxic.com.tw (mxml06c.mxic.com.tw [172.17.14.55]) by Forcepoint Email with ESMTP id E2A4F932393AEF2394D7; Mon, 21 Jun 2021 09:59:29 +0800 (CST) In-Reply-To: <20210618092512.grudqq6vjawt3y5w@ti.com> References: <20210618092512.grudqq6vjawt3y5w@ti.com> To: "Pratyush Yadav" Cc: chris.packham@alliedtelesis.co.nz, chunfeng.yun@mediatek.com, GSS_MTK_Uboot_upstream@mediatek.com, jagan@amarulasolutions.com, ryder.lee@mediatek.com, u-boot@lists.denx.de, vigneshr@ti.com, weijie.gao@mediatek.com, zhengxunli@mxic.com.tw Subject: =?Big5?B?pl6rSDogUmU6IFt2OSwyMy8yOF0gbXRkOiBzcGktbm9yLWNvcmU6IFBlcmZvcm0=?= =?Big5?B?IGEgU29mdCBSZXNldCBvbiBzaHV0ZG93bg==?= MIME-Version: 1.0 X-KeepSent: 35AF3B0B:C67AB0B0-482586FB:0009A5FD; type=4; name=$KeepSent X-Mailer: Lotus Notes Release 8.5.3FP6 SHF907 April 26, 2018 Message-ID: From: jaimeliao@mxic.com.tw Date: Mon, 21 Jun 2021 09:59:29 +0800 X-MIMETrack: Serialize by Router on MXML06C/TAIWAN/MXIC(Release 9.0.1FP10 HF265|July 25, 2018) at 2021/06/21 AM 09:59:29, Serialize complete at 2021/06/21 AM 09:59:29 X-MAIL: TWHMLLG3.macronix.com 15L1xTlb048769 Content-Type: text/plain; charset="US-ASCII" X-Content-Filtered-By: Mailman/MimeDel 2.1.34 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean Hi Pratyush > Hi, > > On 18/06/21 04:55PM, jaimeliao@mxic.com.tw wrote: > > > > Hi Pratyush > > > > > > +#ifdef CONFIG_SPI_FLASH_SOFT_RESET > > +/** > > + * spi_nor_soft_reset() - perform the JEDEC Software Reset sequence > > + * @nor: the spi_nor structure > > + * > > + * This function can be used to switch from Octal DTR mode to legacy mode > > on a > > + * flash that supports it. The soft reset is executed in Octal DTR mode. > > + * > > + * Return: 0 for success, -errno for failure. > > + */ > > +static int spi_nor_soft_reset(struct spi_nor *nor) > > +{ > > + struct spi_mem_op op; > > + int ret; > > + enum spi_nor_cmd_ext ext; > > + > > + ext = nor->cmd_ext_type; > > + nor->cmd_ext_type = SPI_NOR_EXT_REPEAT; > > According JEDEC, cmd_ext_type has two different types, REPEAT and INVERT. > > Some Flash vendor using "INVERT" as cmd_ext_type so that it is not > > suitable for hard coding the type as REPEAT. > > Sending twice reset command with different types is clumsy but useful > > before read ID for getting Flash information. > > It would be great if you have any other ideas for this part. > > It is possible to discover the extension type from BFPT (if the flash > supports it, that is). But this function is supposed to be called before > anything else to make sure the flash is in a sane state. For that > reason, I don't think SFDP would be a viable approach. > > Executing it twice might be a viable option. We need to see how flash > that expect invert react to a repeat opcode, and vice versa. > > Anyway, I don't think this is a problem for now. Both the 8D-8D-8D > capable flashes supported with this series expect a repeat opcode. According Macronix SPI-NOR octal bus Flash datasheet. https://www.mxic.com.tw/Lists/Datasheet/Attachments/7721/MX66UM1G45G,%201.8V,%201Gb,%20v1.1.pdf Most of SPI-NOR octal bus Flash are all need invert extension opcode in octal dtr mode. I think repeat and invert opcode are necessary for different vendor Flash. > > > > > + > > + op = (struct > > spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRSTEN, 0), > > + SPI_MEM_OP_NO_DUMMY, > > + SPI_MEM_OP_NO_ADDR, > > + SPI_MEM_OP_NO_DATA); > > + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); > > + ret = spi_mem_exec_op(nor->spi, &op); > > + if (ret) { > > + dev_warn(nor->dev, "Software reset enable > > failed: %d\n", ret); > > + goto out; > > + } > > + > > + op = (struct > > spi_mem_op)SPI_MEM_OP(SPI_MEM_OP_CMD(SPINOR_OP_SRST, 0), > > + SPI_MEM_OP_NO_DUMMY, > > + SPI_MEM_OP_NO_ADDR, > > + SPI_MEM_OP_NO_DATA); > > + spi_nor_setup_op(nor, &op, SNOR_PROTO_8_8_8_DTR); > > + ret = spi_mem_exec_op(nor->spi, &op); > > + if (ret) { > > + dev_warn(nor->dev, "Software reset > > failed: %d\n", ret); > > + goto out; > > + } > > + > > + /* > > + * Software Reset is not instant, and the delay varies > > from flash to > > + * flash. Looking at a few flashes, most range somewhere > > below 100 > > + * microseconds. So, wait for 200ms just to be sure. > > + */ > > + udelay(SPI_NOR_SRST_SLEEP_LEN); > > + > > +out: > > + nor->cmd_ext_type = ext; > > + return ret; > > +} > > > > > > Thanks > > Jaime > > -- > Regards, > Pratyush Yadav > Texas Instruments Inc. Thanks Jaime CONFIDENTIALITY NOTE: This e-mail and any attachments may contain confidential information and/or personal data, which is protected by applicable laws. Please be reminded that duplication, disclosure, distribution, or use of this e-mail (and/or its attachments) or any part thereof is prohibited. If you receive this e-mail in error, please notify us immediately and delete this mail as well as its attachment(s) from your system. In addition, please be informed that collection, processing, and/or use of personal data is prohibited unless expressly permitted by personal data protection laws. Thank you for your attention and cooperation. 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